Crossing Clock Domains

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Advanced FPGA Design Techniques- Designing Multiple Clock Domains

Navid Lashkarian, Ph.D.

San Jose State University

Electrical Engineering Department

Fall 2008

Navid Lashkarian, Ph.D. Designing Multiple Clock Domains 4/21/2006 1 / 19
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Designing Multiple Clock Domains

What is a Clock Domain

- Clock domain is referred a section of logic where all synchronous

elements (flip=flops, synchronous RAM blocks, pipelined multipliers)are clocked by the same net (clock).

- Phase coherency is not required for all the clocks in the same net;there might be offset between the rising edge of clocks that are on thesame net, however they all have the same frequency and duty cycle.

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Crossing Clock Domains

What makes crossing clock domains a challenge?

- The error patterns and failures are not easily repeatable. Typicalsetup: external clock source with random phase.

- Failures are technology dependent. Often higher speed devices withlower set-up and hold requirements are less sensitive and lessproblematic.

- EDA tools often can not detect and/or simulate the multiple clockdomain issues. Most static timing analysis are based individual clockzones Job Security for those who know what they are doing.

- Always thoroughly analyze the multiple clock designs and architectthe interface properly prior to the implementation.

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What is Meta-stability

- When the data input to a flip-flop transitions within Tsetup prior tothe rising edge of the clock it violates the setup requirement.

- When the data input to a flip-flop transitions within Thold after to therising edge of the clock it violates the hold time requirement.

- The setup and hold violations would cause a suspended node withinthe transistors; a node receive a voltage that it is not identifiable aslogic-0 or logic-1.

- The transistor voltage would dwell at intermediate voltage before

settling on a valid level.- The amount of time the output can stay meta-stable is probabilistic;

it is entirely possible that the data remains meta-stable for the entire


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Setup & Hold


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Scenario without Setup Violation


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Scenario with Setup Violation


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Static Timing Analysis

- Performing static timing analysis is the process of verifying that every

signal path in a design meets required clockcycle timing, whether ornot all of the signal paths are even possible.

- In theory, timing verification could be accomplished by runningexhaustive gate-level simulations with SDF backannotation of actual

timing values after a design is placed and routed. This is oftenreferred to as dynamic timing verification.

- Static timing analysis has three principal advantages over dynamictiming verification; static timing analysis tools verify every single path between any two

sequential elements. static timing analysis does not require the generation of any test

vectors. static timing analysis tools are orders of magnitude faster than trying

to do timing verification running exhaustive gate-level simulations


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Data-Path Synchronization

Passing data from one clock domain to another is an example of passingmultiple randomly changing signals between clock domains.

- Use handshake signals to pass data between clock domains.

- Use FIFO.


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Meta-stability Preventive Techniques

- RTL Simulation is unable of simulating and capturing meta-stability.

- Even gate-level simulations it is difficult to simulate a condition wheretwo asynchronous signals cause meta-stability.

- Like medicine; preventive methods are more effective that curingpatients.

- Solutions: DLL with Phase Control Double Flopping

FIFO Partitioning Synchronizer Blocks




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DLL Phase-control


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DLL Phase-control (2)

- DLL phase-control can be used when the frequency of the fast clockis multiple integers of the slow clock.

- To avoid setup violation

Tlogic+ Trouting+ Tsetup Tfastclock

- If the skew can not be tightly matched, the data can be captured atthe falling edge of the fast clock.

- If the phase between the slow and fast clocks can not be adjusted,alternative methods (as described subsequently) can be used.


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Double Flopping


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Double Flopping (2)

module Double_flopping (

input in,output reg fbr2);

reg fbr1;

always @(posedge clk) begin

fbr1


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FIFO


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FIFO


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FIFO (2)

- The empty and full flags are difficult features to implement. The flagsfor input control (FIFO Full) are often generated by the output anddepends on the amount of the data read from the output. Likewise,the logic that reads the data for output must know if there is any newdata available. This can be obtained from the write pointer of the

input stage.- To pass the necessary flags from one one clock domain to other,

designed need to revert to techniques such as double flopping. Thismethod works for single bit flags.

- However, there are multi-bit flags, such as read and write address,that need to exchanged between clock domains. If meta-stabilityhappens during multi-bit flag exchange, the address bit becomeinvalid.


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Good Coding Practice

- Always partition your design such that the synchronizers blocks arecontained in individual modules outside of any functional block.

- This would simply the timing analysis on each individual block.

- The timing exceptions (that are ignored during timing analysis) areeasily definable.

- Since the synchronizers and timing exceptions are brought up to a toplevel design, the probability of one being overlooked is lowered.

- Avoid clock gating as much as possible.


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Refernces

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Documents

Crossing Clock Domains