CRITICAL ALU PATH OPTIMIZATION AND IMPLEMENTATION CRITICAL ALU PATH OPTIMIZATION AND IMPLEMENTATION

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  • CRITICAL ALU PATH OPTIMIZATION

    AND IMPLEMENTATION IN A BICMOS

    PROCESS FOR GIGAHERTZ RANGE

    PROCESSORS By

    Matthew W. Ernest

    A Thesis Submitted to the Graduate Faculty of Rensselaer Polytechnic Institute in

    Partial Fulfillment of the Requirements of the Degree of

    Doctor of Philosophy

    Major subject: Electrical Engineering

    APPROVED:

    John F. McDonald, ECSE

    Committee Chair

    Mukkai Krishnamoorthy, CSCI

    Committee Member

    Michael Savic, ECSE

    Committee Member

    Paul Schoch, ECSE

    Committee Member

    Rensselaer Polytechnic Institute

    Troy, New York

    December 2002

  • ii

    © Copyright 2002, Matthew W. Ernest

    All Rights Reserved

  • iii

    TABLE OF CONTENTS

    TABLE OF CONTENTS ..........................................................................................................................III

    TABLE OF FIGURES............................................................................................................................. XI

    TABLE OF TABLES........................................................................................................................... XVII

    TABLE OF TABLES........................................................................................................................... XVII

    ACKNOWLEDGMENT ...................................................................................................................... XVIII

    ABSTRACT........................................................................................................................................ XIX

    CHAPTER 1: INTRODUCTION ................................................................................................................1

    1.1 WANTING A FAST ADDER..........................................................................................................1

    1.2 A METRIC FOR CYCLE TIME ......................................................................................................3

    1.3 PARALLEL CIRCUITS AND PREFIX COMPUTATION......................................................................5

    1.4 SILICON GERMANIUM BIPOLAR AND BICMOS FOR HIGH-SPEED PROCESSORS .........................6

    1.5 THE DARPA2 AND SMI00 RETICLES ......................................................................................8

    CHAPTER 2: ADDITION AS A PARALLEL PREFIX PROBLEM ....................................................10

    2.1 INTRODUCTION.......................................................................................................................10

    2.2 THE PREFIX OPERATOR..........................................................................................................10

    2.3 DEPTH/SIZE TRADEOFF IN PREFIX CIRCUITS ...........................................................................11

    2.4 THE CARRY IS A PREFIX OPERATION......................................................................................12

    2.5 RIPPLE CARRY .......................................................................................................................13

    2.6 CARRY SELECT .......................................................................................................................14

    2.7 CARRY LOOK-AHEAD .............................................................................................................16

    2.8 CARRY SKIP............................................................................................................................18

    2.9 THRESHOLD CIRCUITS............................................................................................................20

    2.10 CONCLUSIONS ........................................................................................................................22

    CHAPTER 3: DIGITAL CIRCUIT DESIGN WITH BIPOLAR TRANSISTORS AND CURRENT

    STEERING LOGIC....................................................................................................................................23

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    3.1 INTRODUCTION.......................................................................................................................23

    3.2 THE CURRENT SWITCH...........................................................................................................24

    3.2.1 Series Gating and Emitter Followers...........................................................................25

    3.2.2 Current Sources ...........................................................................................................27

    3.2.3 An Issue of Nomenclature ............................................................................................28

    3.3 BIPOLAR CIRCUITS AND DESIGNING LOGIC FOR SPEED..........................................................29

    3.3.1 fT and fM OSC ..................................................................................................................29

    3.3.2 Latency versus Bandwidth ...........................................................................................30

    3.4 NOISE MARGIN AND VOLTAGE SWING.....................................................................................32

    3.5 DEVICE SIZING IN LOADED BUFFERS .....................................................................................34

    3.5.1 Tail Current .................................................................................................................35

    3.5.2 Current-Switch Transistor Size ....................................................................................37

    3.5.3 Emitter-Follower Size ..................................................................................................38

    3.5.4 Interconnect Parasitics ................................................................................................41

    3.6 THE LOOK-AHEAD GATE .......................................................................................................42

    3.7 CONCLUSIONS ........................................................................................................................45

    CHAPTER 4: CARRY SELECT OPTIMIZATION ...............................................................................47

    4.1 INTRODUCTION AND BACKGROUND .......................................................................................47

    4.1.1 On adders and critical paths........................................................................................47

    4.1.2 On yield limited technologies.......................................................................................48

    4.2 ORIGIN AND THEORY OF CARRY SELECT ADDITION ..............................................................48

    4.3 OPTIMIZATION OF CARRY SELECT STAGE SIZES ....................................................................50

    4.4 OPTIMAL 32-BIT ALU WITH CARRY SELECT ADDITION.........................................................55

    4.4.1 Logic Design ................................................................................................................55

    4.4.2 Circuit Design..............................................................................................................57

    4.4.3 Layout of a Monolithic ALU ........................................................................................62

    4.5 CONSIDERATIONS AFFECTING THE LAYOUT...........................................................................67

    4.5.1 Simulation of the design...............................................................................................68

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    4.6 F-RISC BYTE-SLICE CARRY SELECT IMPLEMENTATION....................................................70

    4.6.1 A Multi-Chip Processor and Another Look at Yield Limitation...................................71

    4.6.2 Comparison to Optimized Adder, And Other Possibilities...........................................72

    4.7 CONCLUSIONS ........................................................................................................................75

    CHAPTER 5: THE PSEUDO-CARRY LOOK-AHEAD ADDER .........................................................76

    5.1 GOALS AND OBJECTIVES.........................................................................................................76

    5.1.1 Previous work: FRISC-G.............................................................................................76

    5.1.2 The next FRISC............................................................................................................76

    5.1.3 SiGe..............................................................................................................................77

    5.1.4 Pseudo-carry Look-ahead............................................................................................77

    5.2 PSEUDO-CARRY THEORY OF OPERATION ...............................................................................77

    5.2.1 Generalized pseudo-carry equations ...........................................................................81

    5.3 THE DARPA2 RETICLE .........................................................................................................82

    5.3.1 Logical structure of the carry