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EE 271 Lab 4 Create a Game: Dance Dance Revolution with a Twist

Amanda Loh

Design: 20 hours Test/Debug: 40 hours Documentation: 3 hours

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Grant Taylor Design: 20 hours

Test/Debug: 45 hours Documentation: 2 hours

_____________________________________________________ Meiling Wu

Design: 10 hours Test/Debug: 15 horus Documentation: 1 hour

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Table of Contents:

ABSTRACT……………………………………………………………………………………3 INTRODUCTION…………………………………………………………………………… 3 DESIGN SPECIFICATION…………………………………………………………………..3 DESIGN PROCEDURE……………………………………………………………………...4 HARDWARE IMPLEMENTATION…………………………………………………………10 TEST PLAN AND TEST RESULTS……………………………………………………….12 RESULTS……………………………………………………………………………………..15 ERROR ANALYSIS……………………………………………………………………….…15 SUMMARY……………………………………………………………………………………16 CONCLUSION………………………………………………………………………………..16 APPENDIX……………………………………………………………………………………16

Game Play and Rules….…………………………………………………………….16 Combined GameBoard, Random Number Generator, and Display Driver Module……………………………………………………………………………..17 Scoreboard Module..……………………………………………………………..24 Controller/Comparison Module………………………………………………….26 Fail Counter Module……………………………………………………………...38

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ABSTRACT This lab centered around producing a working video game. The game we chose to create was inspired by Dance Dance Revolution, which involves hitting a specific key combinations in synch with the moves scrolling down the display. The game keeps track of the player’s current score, and restarts itself when the player gets a “game over”. Our design was adapted for a unique finger dancing technique where four LEDs would shift down the screen and the player would have to hit matching buttons at the right time to score points. This design was implemented using a Cyclone II chip and a GAL 22V10D chip. Shift registers, multiplexers, counters, and adjustable timebase dividing techniques were used to synthesize our game’s functionality. The main challenge throughout the lab was figuring out the syntax to connect various registers and groups of vectorized wires together to attain the desired visual output for the LED matrix that was used. INTRODUCTION The purpose of this lab is to bring together everything that was learned during the quarter to make a functional and fun game. The game was made from scratch and it was up to our discretion as engineers to design the appropriate functionality and implementation of each part of the game, including which tool from class we would to use to execute our vision. We came up with a high level schematic for our game and split it up into five distinct parts: a pseudo­random number generator, a four stage four bit shift register, a display driver for our LED matrix visual output, a fail counter, and a scoreboard. The number generator involved generating a counter to count up through seemingly random numbers to create dance choreography. The shift register was built with four discrete d­flip flops grouped together one row of the scroll. The the data on these four flip flops was then shifted through three subsequent 4­bit registers representing various preview images followed by the current dance move. The LED matrix driver was implemented using a multiplexer to rapidly scan across the columns of LEDs to display the current contents of the shift registers so our users could actually see what was going on inside. The fail counter was created with a three bit up counter to track the player’s mistakes leading up to a game over state. Lastly, a scoreboard was implemented by creating four four bit up counters counting from 0­9, all connected through multiplexers to count and hold a score of 0­9999 in decimal. Each component was constructed on the Cyclone II chip with the exception the fail counter. This was because the fail counter was relatively simple and it did not involve many inputs and outputs. DESIGN SPECIFICATION There were very few design specifications but it was required that the game be: 1. Implemented on the DE1 board. 2. Incorporate at least one finite state machine utilizing at least one GAL22V10 3. Implement at least one finite state machine module for the Cyclone II FPGA using graphical schematic capture.

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DESIGN PROCEDURE Here is an overall block diagram of the system:

Here is a state diagram of the game:

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Number Generator: The first part of the design was creating a pseudo random number generator that would create seemingly random four bit numbers. This was achieved by using the Linear FeedbackShift Register Testbench application. It was decided that the shift register would hold four bits and would have the initial value of 15. A flip flop diagram was generated from the LFSR testbench which came from http://www.logicell.com/~jean/LFSR/. See below:

This flip flop design was then used to generate structural Verilog code to produce the correct random number configuration for the game. Shift Registers: The second part of the lab was creating a shift register to store each four bit dance move and allow the player ample time to see, prepare, and react to the incoming moves. We decided three preview stages would be sufficient warning, with the last stage of the shift register holding the current move which must be matched by the end of the current clock cycle. This was accomplished by creating four side­by­side D­flip flop based shift registers, each holding the required values for a single key in a given four key move.

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The shift register design was coded in Verilog, and attached to the random number generator as an input for the registers’ values. See structural diagram here: Note SR latches were used instead, but should represent D­flip flops with S representing data. R is not represented as anything in this model.

Display Driver: The next major component in our design was to develop a display driver to allow us and our future players to see the contents of the shift registers, and in turn know what moves needed to be performed. The multi LED display we chose to use used a matrix configuration, which meant that in order to control each individual LED separately we had to devise a method of scanning across the matrix one row at a time, faster than humanly visible, in order to generate a composite image of the entire game board. This was accomplished by vectorizing each of our shift register columns, feeding each of the four into a four to one multiplexer and then using the selector bits to both switch between the columns currently being driven and their corresponding data in column vector form. We then alternate through these selectors using a very fast clock, creating an effective refresh rate of 100Hz; so quick that the output looks like solid, individually controlled lights (only we know the amount of work that actually goes into this).

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Scoreboard: Next, we had to design a scoreboard to keep track of our players’ progress. It was around this point that we realized we still needed to make use of Quartus’ graphical design interface as per the specifications. So we decided that the task of checking our players’ moves against the current move in the shift register would be a prime opportunity to build a simple task with an unfamiliar tool. From this our “Comparison” module branched out of the scorekeeping module where we’d pictured it and into a top level connector module. After wiring the user input buttons and their corresponding “current move” flipflops through XNOR gates to determine if they matched, the comparison module took advantage of Quartus’ library of prebuilt megafunctions giving us a prebuilt four to sixteen decoder. An emulated 74154 decoder allowed us to isolate erroneous moves (2 or less keys correct) from “good” moves (3 keys correct) and “great” moves (all keys correct). We decided that good or great moves would earn the player a point, while bad moves would lead one step closer to a game over. Comparison portion of Scorekeeper:

The scoreboard module counted the good moves, incrementing a four digit decimal counter which we would use to display the current score on the DE1 board’s integrated seven segment display bank. This was coded in verilog and then converted to a symbol file to place within the larger block diagram we’d constructed. However along the way we’d need to convert the binary coded decimal score into individual signals to drive the bars of each seven segment display. Once again we made use of a pre built megafunction found within Quartus, this time an emulated 7448 BCD to seven segment decoder. Each of the four digits now had seven outputs tied to the board’s display, and our block diagram was becoming huge and complex, as can be seen below.

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Scorekeeper to Seven Segment Conversion Block:

Time Base: An iClk of 24MHz was used that needed to be divided down depending on the difficulty of the game: speed: beginner, medium, and hard. The changing time base was implemented using SR latches with the reset grounded so that they would never reset. When a score of 20 is reached, the time base is changed to an timebase index of 23 from 24. The same thing occurs when the score of 40 is reached so the time base index changes from 23 to 22.There were 2 SR latches implemented: one for the medium speed and one for the hard speed. The output of the SR latches were medspeed and hardspeed. An and gate was created to put the tbase at 24 when medspeed and hardspeed were both false. A similar thing was done for medspeed except the condition hardspeed was still 0 had to be true and qC2 was a 1. Then, hardspeed occurred when on the 10’s digit of the score, a 1 on the qA2 was detected. Grounding the R on the SR latch ensured the tbase was held permanently after a certain binary bit turned to a 1. See below for a better visual of the SR latches:

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Fail Counter

The picture above illustrates the process for making a failure counter (counting the mistakes a person makes while playing the game), and when client fail 4 times, (5th state reserved for game over state) the game shows game over. First, I decided use 5 states for counting, and use little endian to complete the state table, i.e. state 0 is 000, state 1 is 100, state 2 is 010, state 3 is 110, and state 4 is 001. According to the state table, I made a K­map and found the input equations for each flip flop.

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HARDWARE IMPLEMENTATION Cyclone II Chip Programming: The number generator, shift register, display driver, and scoreboard were all implemented on the Cyclone II chip. A pinout for all the I/O’s used are listed below. These pinouts were easily identifiable because Quartus was used to visually map out the I/O’s of each part of the system. See those diagrams above.

LED Matrix Connections: We chose 8X8 LED matrix as the display screen, and used four columns in the middle to display the pattern. From there, we found out the specific pins for the LED lights. See a diagram for our lights shifting relative to the 8X8 LED matrix below.

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From the picture, the orange highlighter shows the LEDs that were used for the game, which are in row 3­6, and column 2, 4, 6, 8. In the pin assignment spec sheet below(Figure 1), we found the pins for specific rows, and columns.

We took out the resistors because according to the specification sheet for the matrix board, the maximum current threshold was found to be greater than the current measured manually when the resistors were taken out and the current was measured. Fail Counter: For the fail counter, this was implemented on the GAL chip with a chip report shown below: This was first tested by attaching the clk input to the function generator and feeding it a 1Hz square wave to test it was counting correctly. Eventually, the outputs, clk, rest, and start were all

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connected to ports on the board so that they receive data coming from the Cyclone II chip programming.

TEST PLAN AND TEST RESULTS Number Generator: For the number generator portion, this was tested by initializing preset beforehand and letting preset go to zero for the actual simulation and turning reset off so that the random number generator could generate seemingly random numbers starting at fifteen (1111). A timing diagram for this is shown below.

A table was also produced due to the tester which was used to compare the expected output from the LFSR testbench to what the D­flip flops were doing for the design. The expecting counts and results from tester are shown below:

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Clearly, expected and tester output are the same. Shift Register: The shift register bank was tested by feeding our module a sequence of incrementing four bit numbers and then testing to see that they propagated through the stages in the proper sequence as the clock incremented. Essentially, this was testing how our random numbers would eventually propagate through the shifter, only here we input every possible four bit combination and could see if each was shifting properly and on time. Below are the waveform results of said testing.

Display Driver: The display driver was tested in Bughunter Pro by giving it arbitrary values for the shift register’s row vectors, and then was check to ensure that it could form column vectors from the first, second, third, and fourth element of each. We also watched the integrated four bit counter to ensure time was being divided down from a ridiculously fast clock input to something merely faster than the eye could see, all while watching the column power signals to see that the scan was progressing along with the timer properly. Finally, we also looked a Z, the vectorized output of the 4 to 1 multiplexer to make sure that the selector bits were transmitting the proper column vector data with their respective column power signal.

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Once we were satisfied the display driver was working correctly in simulation, we integrated it into the game board module, connecting it with the RNG and shift register and watched the moves shift down the display. Scoreboard: The scoreboard was tested by inputting for the first one’s place of the scoreboard 1 bit to enable the 1 to count. This was to ensure the scoreboard could count 0­9999. Part of the waveform, that demonstrates its ability to count up through the 1’s, 10’s and 1000’s place is shown below:

The one bit enable eventually became the increment input from the comparator and decoder that analyzed whether someone got a move right or not in order to increment the score. Fail Counter: The fail counter was tested in a similar fashion by making sure the counter could accurately count. Also, it was made certain that the counter had an accurately working start button that, when start was disabled, would maintain the count until start was enabled again. A timing diagram of such a counter is shown below:

Notice the flip flops hold their value when start is low. They continue counting when start goes high again.

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RESULTS The approach we took was to test each of the five parts of the Dance Dance Revolution separately before implementing it all together on the DE 1 board. That being said, when everything was connected together, the system worked as expected because we did debug each piece ahead of time. All waveforms shown above in the test plan and test results. We verified: ­When the reset is turned off the game begins ­When you get four fails the game resets as well as the score ­When 4/4 moves are correct: the fail resets if any fails were made previously, score increments ­When ¾ moves are correct: the fail DOES NOT reset if any fails made previously, score increments ­When 2/4 moves or less are correct: fail counter increments, no score increment ­When 4 fails commited game resets ­When you reset game from switch game resets ­When you reach a score of 20, game speeds up by index time base 23 ­When you reach a score of 40, game speeds up by index time base 22 ­Players get the four bonus points at the beginning of the game ERROR ANALYSIS We encountered two major errors that caused setbacks. One involved wiring and registers for allowing the binary states of each of the shift registers to be displayed on the 8X8 LED matrix display. The other error encountered was detecting a bug in the scorekeeper where when the one’s ten’s or hundred’s digit reached 9, when the player stopped pressing correct moves, the wrong digit place would start to increment. 8X8 LED matrix: The major difficulty in building the LED matrix display driver was in trying to wrangle the Verilog code to match our design. The anode side of our LED board corresponded to the columns, meaning we’d have to drive power down the columns and send grounding signals across the rows. This meant pulling column vector data from our shift register, but the data was already formatted into row vectors. Thus we’d have to concatenate together column vectors on the fly as the data continued to shift down with time. After a lot of reading, testing, and hand wringing we figured out this could be accomplished by putting the concatenation assignment statements inside an always loop tied to the refresh clock. From there we had to build a four channel multiplexer to swap active data channels when as the active columns cycled through the scan pattern. Again, due to our inexperience with handling vectorized signals in Verilog, this took some time and finessing. Scorekeeper Glitch: The problem with this glitch was that, when the counter reached the number 9 (let’s say in the one’s digit place), it would not go back to 0 until the player would get another move correctly. However, the clock is still running and the counter is stuck at nine which would give the “go

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ahead” to the tens column to start incrementing. The tens would start and the scorekeeper would display counts like 9, 19, 29, 39… and so forth. To fix this problem we simply added and gates to force the tens, hundreds, and thousands places to start counting only when the playing is getting a point, and when all the previous digits are at 9. This error gave great insight into how the counter is connected to the clock as well as the input that allows the go ahead to increment. SUMMARY Creating a game like Dance Dance Revolution was implemented by breaking up the game into five separate pieces and debugging them separately. This was proven to be effective because the bugs pertaining to specific pieces of the system could be easily identified. Each part of the system could also be handled by separate engineers without any one engineer having to know everything about the system. He/She only had to know about the desire I/Os desired to connect to other parts of the game. Despite separate pieces being easy to implement, the challenge was to put these pieces together and have the data from shift registers flow through the fail counter, scoreboard, and other components seamlessly to generate the desired outcome. Some of these challenges included loading data from the row matrix into the column vectors correctly and making sure the clock worked with an increment input to generate an accurate scorekeeper. CONCLUSION Overall, this version of the game was a success and has some very useful features. There is, as always, room for improvement with ideas such as making a multiplier for the score and attaching a different style keypad. This can be modified in later modifications of the game in the future. This project encompasses almost every aspect of digital logic. Bits had to be analyzed to determine whether a 1 or a 0 enabled something to run. Simple gates such as ands and ors had to be used to enable only certain signals to come through at certain times. SR latches had to be used to change the speed of the game. D­flip flops had to be used to store the various moves and shift registers had to be able to enable the scrolling design needed. Finite state machine algorithms were used to generate counters. A 7 segment decoder as well as a decoder were also implemented for the display and controlling what the consequences of a good,bad, and okay move are. Threshold current was analyzed in a spec. sheet to make sure not too much current was output for the LEDs. This proves the vast number of tools that were used to generate this game all working together to provide a visually appealing and well functioning game. APPENDIX Game Play and Rules: The game explanation is as follows: Small LED “moves” will slowly scroll down the screen. When they hit the bottom line it is your job to press down the buttons corresponding to the lit LEDs. The four game buttons lay in a row of four and match the layout of the LEDs coming down the screen.

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The Rules Are: If you press all four buttons correctly (“Great”), you get that “move” of choreography completely correct you earn a point. If you press three out of four buttons correctly (“Ok”) you still get a point. If you press two or fewer buttons correctly (“Fail”) you do not get any points for that round and you get a strike against you. Note on the strikes: You get four strikes until game over. If you can prove you can get one choreography move “perfect”, your strikes get reset and you go back to having 0 strikes. If you do reach the fourth strike and you get another incorrect move, the game is over and your score resets as well as the game itself. Also, note that getting only three out of four moves does not reset your strikes. Best Results: Hold down the buttons until the next move has shifted in, meaning do not release your fingers from the buttons until the next move. It makes it easier to play and you won’t get a strike against you for relaxing and letting your guard down! To start the game, user must flip the second to left most switch on the DE board. The max score you can achieve in this game is 9999. Bonus: Notice the speed of the game increases when you score 20 points. When you reach 40 points the game will suddenly increase to an even harder level of difficulty. Also, notice you get four free bonus points every start of the game! That’s a bonus feature to make the player feel good at the start of the game. Everybody wins! Combined GameBoard, Random Number Generator, and Display Driver Module (with submodules): module Game(qpreview1, qpreview2, qpreview3, qcurrmove,Z,col0,col1,col2,col3,qs0,qs1,A,B,C,D,Clk1,nqpreview1, nqpreview2, nqpreview3, nqcurrmove,easy,med,hard, Rst,iClk, medspeed,hardspeed);

input Rst, iClk; input medspeed,hardspeed; output wire easy,med,hard; output wire [0:3] qpreview1; output wire [0:3] qpreview2; output wire [0:3] qpreview3; output wire [0:3] qcurrmove; output wire [0:3] Z; output col0,col1,col2,col3;

output wire [0:3] nqpreview1;

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output wire [0:3] nqpreview2; output wire [0:3] nqpreview3; output wire [0:3] nqcurrmove;

output qs0,qs1,Clk1;

output wire [0:3] A; output wire [0:3] B; output wire [0:3] C; output wire [0:3] D; //timebase for shifting reg [32:0] tBase1=0; always@(posedge iClk) tBase1<=tBase1 +1'b1; //new and broken?

not n0001(nmedspeed, medspeed); not n0002(nhardspeed, hardspeed);

and and1(easy, tBase1[24], nmedspeed, nhardspeed); and and2(med, tBase1[23], medspeed, nhardspeed); and and3(hard, tBase1[22], hardspeed);

or orClock(Clk1, hard, med, easy); //old reliable //buf buf01(Clk1, tBase1[23]);

shiftRandom mything(qpreview1, qpreview2, qpreview3, qcurrmove, nqpreview1,

nqpreview2, nqpreview3, nqcurrmove, Clk1,Rst); displayDriver myDisp(Z,col0,col1,col2,col3,qs0,qs1,A,B,C,D, nqpreview1, nqpreview2,

nqpreview3, nqcurrmove, iClk, Rst); endmodule module shiftRandom(qpreview1, qpreview2, qpreview3, qcurrmove, nqpreview1, nqpreview2, nqpreview3, nqcurrmove, Clk1,Rst); input Clk1, Rst;

output wire [0:3] qpreview1; output wire [0:3] qpreview2;

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output wire [0:3] qpreview3; output wire [0:3] qcurrmove;

output wire [0:3] nqpreview1; output wire [0:3] nqpreview2; output wire [0:3] nqpreview3; output wire [0:3] nqcurrmove; wire [0:3] rng; parameter Pre = 1'b0; numGen myGen(rng, Clk1,Pre,Rst); gameboard myGame(qpreview1, qpreview2, qpreview3, qcurrmove, nqpreview1,

nqpreview2, nqpreview3, nqcurrmove, rng, Clk1, Rst); endmodule module gameboard(qpreview1, qpreview2, qpreview3, qcurrmove, nqpreview1, nqpreview2, nqpreview3, nqcurrmove, rng, Clk1, Rst);

output wire [0:3] qpreview1; output wire [0:3] qpreview2; output wire [0:3] qpreview3; output wire [0:3] qcurrmove; output wire [0:3] nqpreview1; output wire [0:3] nqpreview2; output wire [0:3] nqpreview3; output wire [0:3] nqcurrmove; input wire [0:3] rng; input Clk1, Rst; wire [0:3] dpreview1; wire [0:3] dpreview2; wire [0:3] dpreview3; wire [0:3] dcurrmove; parameter Pre = 1'b0; /*Generic Barrel of Shift Reg buf bufbarrelnum0(dpreview1[barrelnum], rng[barrelnum]);

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DFlipFlop preview1_barrelnum(qpreview1[barrelnum], nqpreview1[barrelnum], dpreview1[barrelnum], Clk, Rst);

buf bufbarrelnum1(dpreview2[barrelnum], qpreview1[barrelnum]); DFlipFlop preview2_barrelnum(qpreview2[barrelnum], nqpreview2[barrelnum],

dpreview2[barrelnum], Clk, Rst); buf bufbarrelnum2(dpreview3[barrelnum], qpreview2[barrelnum]); DFlipFlop preview3_barrelnum(qpreview3[barrelnum], nqpreview3[barrelnum],

dpreview3[barrelnum], Clk, Rst); buf bufbarrelnum3(dcurrmove[barrelnum], qpreview3[barrelnum]); DFlipFlop currmove_barrelnum(qcurrmove[barrelnum], nqcurrmove[barrelnum],

dcurrmove[barrelnum], Clk, Rst);*/ //barrel 0

buf buf00(dpreview1[0], rng[0]); DFlipFlop preview1_0(qpreview1[0], nqpreview1[0], dpreview1[0], Clk1, Pre, Rst); buf buf01(dpreview2[0], qpreview1[0]); DFlipFlop preview2_0(qpreview2[0], nqpreview2[0], dpreview2[0], Clk1, Pre, Rst); buf buf02(dpreview3[0], qpreview2[0]); DFlipFlop preview3_0(qpreview3[0], nqpreview3[0], dpreview3[0], Clk1, Pre, Rst); buf buf03(dcurrmove[0], qpreview3[0]); DFlipFlop currmove_0(qcurrmove[0], nqcurrmove[0], dcurrmove[0], Clk1, Pre, Rst); //barrel 1 buf buf10(dpreview1[1], rng[1]); DFlipFlop preview1_1(qpreview1[1], nqpreview1[1], dpreview1[1], Clk1, Pre, Rst); buf buf11(dpreview2[1], qpreview1[1]); DFlipFlop preview2_1(qpreview2[1], nqpreview2[1], dpreview2[1], Clk1, Pre, Rst); buf buf12(dpreview3[1], qpreview2[1]); DFlipFlop preview3_1(qpreview3[1], nqpreview3[1], dpreview3[1], Clk1, Pre, Rst); buf buf13(dcurrmove[1], qpreview3[1]); DFlipFlop currmove_1(qcurrmove[1], nqcurrmove[1], dcurrmove[1], Clk1, Pre, Rst); //barrel 2 buf buf20(dpreview1[2], rng[2]); DFlipFlop preview1_2(qpreview1[2], nqpreview1[2], dpreview1[2], Clk1, Pre, Rst); buf buf21(dpreview2[2], qpreview1[2]); DFlipFlop preview2_2(qpreview2[2], nqpreview2[2], dpreview2[2], Clk1, Pre, Rst); buf buf22(dpreview3[2], qpreview2[2]); DFlipFlop preview3_2(qpreview3[2], nqpreview3[2], dpreview3[2], Clk1, Pre, Rst); buf buf23(dcurrmove[2], qpreview3[2]); DFlipFlop currmove_2(qcurrmove[2], nqcurrmove[2], dcurrmove[2], Clk1, Pre, Rst);

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//barrel 3 buf buf30(dpreview1[3], rng[3]); DFlipFlop preview1_3(qpreview1[3], nqpreview1[3], dpreview1[3], Clk1, Pre, Rst); buf buf31(dpreview2[3], qpreview1[3]); DFlipFlop preview2_3(qpreview2[3], nqpreview2[3], dpreview2[3], Clk1, Pre, Rst); buf buf32(dpreview3[3], qpreview2[3]); DFlipFlop preview3_3(qpreview3[3], nqpreview3[3], dpreview3[3], Clk1, Pre, Rst); buf buf33(dcurrmove[3], qpreview3[3]); DFlipFlop currmove_3(qcurrmove[3], nqcurrmove[3], dcurrmove[3], Clk1, Pre, Rst);

endmodule module numGen(rng, Clk1,Pre,Rst);

output wire [0:3] rng; input Clk1,Pre,Rst; //wire Da,Db,Dc,Dd, Clk,Pre,Rst; not n000(nRst, Rst); //FF A DFlipFlop dffa(qA, nqA, Da, Clk1, nRst, 1'b1); //FF B DFlipFlop dffb(qB, nqB, Db, Clk1, nRst, 1'b1); //FF C DFlipFlop dffc(qC, nqC, Dc, Clk1, nRst, 1'b1); //FF D DFlipFlop dffd(qD, nqD, Dd, Clk1, nRst, 1'b1);

//assign bits: leftmost MSB in order ABCD so flip flops = backward left to right DCBA //left most one

buf buf1(Dd, qA); //Db xor xor1(Dc, qA, qD); //Dc buf buf2(Db,qC); //Dd buf buf3(Da,qB); //vectorize output buf buf00(rng[0],Dd); buf buf01(rng[1],Dc);

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buf buf02(rng[2],Db); buf buf03(rng[3],Da);

endmodule module DFlipFlop(q, nq, D, clk, Pre, Rst); input D, clk, Pre,Rst; output q, nq; reg q; not n1(nq, q); not n2(nrst, Rst); always@ (posedge nrst or posedge clk) begin if(nrst) q = 0; else if(Pre) q = 1; else q = D; end endmodule module displayDriver(Z,col0,col1,col2,col3,qs0,qs1,A,B,C,D, nqpreview1, nqpreview2, nqpreview3, nqcurrmove, iClk, Rst); output wire [0:3] Z;

output col0,col1,col2,col3; input wire [0:3] nqpreview1;

input wire [0:3] nqpreview2; input wire [0:3] nqpreview3; input wire [0:3] nqcurrmove;

input iClk, Rst; parameter pre = 0; output qs0,qs1;

output reg [0:3] A; output reg [0:3] B;

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output reg [0:3] C; output reg [0:3] D;

reg [32:0] tBase=0;

always@(posedge iClk) tBase<=tBase +1'b1; buf buf0(Clk2, tBase[14]);

//output reg [0:3] A = nqpreview1[0],nqpreview2[0],nqpreview3[0],nqcurrmove[0]; always@(posedge Clk2) begin A [0:3] = nqpreview1[0],nqpreview2[0],nqpreview3[0],nqcurrmove[0]; B [0:3] = nqpreview1[1],nqpreview2[1],nqpreview3[1],nqcurrmove[1]; C [0:3] = nqpreview1[2],nqpreview2[2],nqpreview3[2],nqcurrmove[2]; D [0:3] = nqpreview1[3],nqpreview2[3],nqpreview3[3],nqcurrmove[3]; end //Speedy 4 bit up counter

DFlipFlop S0(qs0, nqs0,Ds0,Clk2,Pre,Rst); DFlipFlop S1(qs1, nqs1,Ds1,Clk2,Pre,Rst); buf b1(Ds0,nqs0); xor x1(Ds1, qs0,qs1);

wire [0:3] temp1; wire [0:3] temp2; wire [0:3] temp3; wire [0:3] temp4;

//Ground Mux and a10(temp1[0], A[0], nqs0,nqs1); and a20(temp2[0], B[0], qs0,nqs1); and a30(temp3[0], C[0], nqs0,qs1); and a40(temp4[0], D[0], qs0,qs1);

and a11(temp1[1], A[1], nqs0,nqs1);

and a21(temp2[1], B[1], qs0,nqs1); and a31(temp3[1], C[1], nqs0,qs1); and a41(temp4[1], D[1], qs0,qs1);

and a12(temp1[2], A[2], nqs0,nqs1);

and a22(temp2[2], B[2], qs0,nqs1); and a32(temp3[2], C[2], nqs0,qs1);

24

and a42(temp4[2], D[2], qs0,qs1); and a13(temp1[3], A[3], nqs0,nqs1);

and a23(temp2[3], B[3], qs0,nqs1); and a33(temp3[3], C[3], nqs0,qs1); and a43(temp4[3], D[3], qs0,qs1); or o0(Z[0], temp1[0], temp2[0], temp3[0], temp4[0]);

or o1(Z[1], temp1[1], temp2[1], temp3[1], temp4[1]); or o2(Z[2], temp1[2], temp2[2], temp3[2], temp4[2]); or o3(Z[3], temp1[3], temp2[3], temp3[3], temp4[3]);

//Power Scanner and a5(col0, nqs0,nqs1); and a6(col1, qs0,nqs1); and a7(col2, nqs0,qs1); and a8(col3, qs0,qs1);

endmodule Scoreboard Module: module scoreKeeper(qA1,qB1,qC1,qD1,qA2,qB2,qC2,qD2,qA3,qB3,qC3,qD3,qA4,qB4,qC4,qD4, Clk, Rst, increment); output qA1,qB1,qC1,qD1, qA2,qB2,qC2,qD2,qA3,qB3,qC3,qD3, qA4,qB4,qC4,qD4; input Clk, Rst, increment; oneDecadeCounter myDecade1(z1,qA1,qB1,qC1,qD1, Clk, Rst, increment); and myAnd0(istrueand9, z1, increment); oneDecadeCounter myDecade2(z2,qA2,qB2,qC2,qD2, Clk, Rst, istrueand9); and myAnd1(areBothNine, z2, z1, increment); oneDecadeCounter myDecade3(z3,qA3,qB3,qC3,qD3, Clk, Rst, areBothNine); and myAnd2(areThreeNine, z1, z2, z3, increment); oneDecadeCounter myDecade4(z4,qA4,qB4,qC4,qD4, Clk, Rst, areThreeNine); endmodule

module oneDecadeCounter(z,qA,qB,qC,qD, Clk, Rst, sel);

output qA,qB,qC,qD, z; input Clk,Rst, sel;

25

wire Da,Db,Dc,Dd, sel, logicA, logicB, logicC, logicD; //mux for each flip flop myMux DFF1(Da, qA, logicA, sel); myMux DFF2(Db, qB, logicB, sel); myMux DFF3(Dc, qC, logicC, sel); myMux DFF4(Dd, qD, logicD, sel); //FF A dFlipFlop dffa(qA, nqA, Da, Clk, Rst); //FF B dFlipFlop dffb(qB, nqB, Db, Clk, Rst); //FF C dFlipFlop dffc(qC, nqC, Dc, Clk, Rst); //FF D dFlipFlop dffd(qD, nqD, Dd, Clk, Rst);

//A represents MSB //Da for flip flop A and myAnd1(out1,qA, nqD); and myAnd2(out2, qB, qC, qD); or myOr1(logicA, out1, out2); //Db for flip flop B and myAnd3(out3, nqA, qB, nqC); and myAnd4(out4, qB, qC, nqD); and myAnd5(out5, nqA, nqB, qC, qD); or myOr2(logicB, out3, out4, out5); //Dc for flip flop C and myAnd6(out6, qC, nqD); and myAnd7(out7, nqA, nqC, qD); or myOr3(logicC, out6, out7); //Dd for flip flop D not inv1(logicD, qD); //z output when the number is nine and finalAnd(z, qA, nqB, nqC, qD);

endmodule module myMux(data, same, logic, sel);

26

output data; input same, logic, sel;

wire data; //inverters not n1(nsel, sel); and and1(f1, same, nsel); and and2(f2, logic, sel);

or myOr1(data, f1, f2); endmodule

module dFlipFlop(q, nq, D, clk, rst); input D, clk, rst; output q, nq; reg q; not n1(nq, q); not n2(nrst, rst); always@ (posedge nrst or posedge clk) begin if(nrst) q = 0; else q = D; end endmodule Controler/Comparison Module: (this was designed graphically in Quartus and then converted to verilog, hence the ambiguous naming) // Copyright (C) 1991­2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License

27

// Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64­Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" // CREATED "Fri Aug 22 09:46:58 2014" module Comparator(

Button2, Button3, Button0, Button1, Rst, iClk, pin_name29, pin_name30, pin_name31, Fail, Good, Combo, col0, col1, col2, col3, pin_name1, pin_name2, pin_name3, pin_name4, pin_name5, pin_name6, pin_name7, pin_name8, pin_name9, pin_name10, pin_name11, pin_name12, pin_name13, pin_name14, pin_name15,

28

pin_name16, pin_name17, pin_name18, pin_name19, pin_name20, pin_name21, pin_name22, pin_name23, pin_name24, pin_name25, pin_name26, pin_name27, pin_name28, Clk1, pin_name32, pin_name33, pin_name34, pin_name35, RstFailCount, easy, hard, med, Z

); input wire Button2; input wire Button3; input wire Button0; input wire Button1; input wire Rst; input wire iClk; input wire pin_name29; input wire pin_name30; input wire pin_name31; output wire Fail; output wire Good; output wire Combo; output wire col0; output wire col1; output wire col2; output wire col3; output wire pin_name1;

29

output wire pin_name2; output wire pin_name3; output wire pin_name4; output wire pin_name5; output wire pin_name6; output wire pin_name7; output wire pin_name8; output wire pin_name9; output wire pin_name10; output wire pin_name11; output wire pin_name12; output wire pin_name13; output wire pin_name14; output wire pin_name15; output wire pin_name16; output wire pin_name17; output wire pin_name18; output wire pin_name19; output wire pin_name20; output wire pin_name21; output wire pin_name22; output wire pin_name23; output wire pin_name24; output wire pin_name25; output wire pin_name26; output wire pin_name27; output wire pin_name28; output wire Clk1; output wire pin_name32; output wire pin_name33; output wire pin_name34; output wire pin_name35; output wire RstFailCount; output wire easy; output wire hard; output wire med; output wire [0:3] Z; wire A; wire B; wire C; wire Clk_ALTERA_SYNTHESIZED1; wire Combo_ALTERA_SYNTHESIZED;

30

wire D; wire GameOver; reg hardspeed; reg medspeed; wire [0:3] nqcurrmove; wire qA2; wire qB2; wire qC2; wire [0:3] qcurrmove; wire qD2; wire Reset; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_3; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_6; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_11; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYNTHESIZED_WIRE_15; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_77; wire SYNTHESIZED_WIRE_19; wire SYNTHESIZED_WIRE_20; wire SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_22; wire SYNTHESIZED_WIRE_23; wire SYNTHESIZED_WIRE_24; wire SYNTHESIZED_WIRE_25; wire SYNTHESIZED_WIRE_26; wire SYNTHESIZED_WIRE_27; wire SYNTHESIZED_WIRE_78; wire SYNTHESIZED_WIRE_31; wire SYNTHESIZED_WIRE_32; wire SYNTHESIZED_WIRE_33; wire SYNTHESIZED_WIRE_34;

31

wire SYNTHESIZED_WIRE_35; wire SYNTHESIZED_WIRE_36; wire SYNTHESIZED_WIRE_37; wire SYNTHESIZED_WIRE_79; wire SYNTHESIZED_WIRE_41; wire SYNTHESIZED_WIRE_42; wire SYNTHESIZED_WIRE_43; wire SYNTHESIZED_WIRE_44; wire SYNTHESIZED_WIRE_45; wire SYNTHESIZED_WIRE_46; wire SYNTHESIZED_WIRE_47; wire SYNTHESIZED_WIRE_48; wire SYNTHESIZED_WIRE_49; wire SYNTHESIZED_WIRE_50; wire SYNTHESIZED_WIRE_51; wire SYNTHESIZED_WIRE_80; wire SYNTHESIZED_WIRE_55; wire SYNTHESIZED_WIRE_56; wire SYNTHESIZED_WIRE_57; wire SYNTHESIZED_WIRE_58; wire SYNTHESIZED_WIRE_59; wire SYNTHESIZED_WIRE_60; wire SYNTHESIZED_WIRE_61; wire SYNTHESIZED_WIRE_62; wire SYNTHESIZED_WIRE_63; wire SYNTHESIZED_WIRE_64; wire SYNTHESIZED_WIRE_65; wire SYNTHESIZED_WIRE_81; wire SYNTHESIZED_WIRE_69; wire SYNTHESIZED_WIRE_70; wire SYNTHESIZED_WIRE_71; wire SYNTHESIZED_WIRE_72; wire SYNTHESIZED_WIRE_73; wire SYNTHESIZED_WIRE_74; wire SYNTHESIZED_WIRE_75; wire SYNTHESIZED_WIRE_76; assign Good = SYNTHESIZED_WIRE_12; assign SYNTHESIZED_WIRE_77 = 0; assign SYNTHESIZED_WIRE_78 = 1; assign SYNTHESIZED_WIRE_79 = 1; assign SYNTHESIZED_WIRE_80 = 1; assign SYNTHESIZED_WIRE_81 = 1;

32

nand11 b2v_inst(

.in1(SYNTHESIZED_WIRE_0),

.in2(SYNTHESIZED_WIRE_1),

.in3(SYNTHESIZED_WIRE_2),

.in4(SYNTHESIZED_WIRE_3),

.in5(SYNTHESIZED_WIRE_4),

.in6(SYNTHESIZED_WIRE_5),

.in7(SYNTHESIZED_WIRE_6),

.in8(SYNTHESIZED_WIRE_7),

.in9(SYNTHESIZED_WIRE_8),

.in10(SYNTHESIZED_WIRE_9),

.in11(SYNTHESIZED_WIRE_10),

.out(Fail)); assign Combo_ALTERA_SYNTHESIZED = ~SYNTHESIZED_WIRE_11; assign SYNTHESIZED_WIRE_76 = Combo_ALTERA_SYNTHESIZED | SYNTHESIZED_WIRE_12; assign SYNTHESIZED_WIRE_12 = ~(SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14 & SYNTHESIZED_WIRE_15 & SYNTHESIZED_WIRE_16); always@(posedge Clk_ALTERA_SYNTHESIZED1 or negedge Reset) begin if (!Reset)

begin medspeed <= 0; end

else begin medspeed <= ~medspeed & qC2 | medspeed & ~SYNTHESIZED_WIRE_77; end

end Game b2v_inst14(

.Rst(Reset),

.iClk(iClk),

33

.medspeed(medspeed),

.hardspeed(hardspeed),

.col0(col0),

.col1(col1),

.col2(col2),

.col3(col3), .Clk1(Clk_ALTERA_SYNTHESIZED1), .easy(easy), .med(med), .hard(hard),

.nqcurrmove(nqcurrmove), .Z(Z));

always@(posedge Clk_ALTERA_SYNTHESIZED1 or negedge Reset) begin if (!Reset)

begin hardspeed <= 0; end

else begin hardspeed <= ~hardspeed & qB2 | hardspeed & ~SYNTHESIZED_WIRE_77; end

end assign SYNTHESIZED_WIRE_23 = ~Combo_ALTERA_SYNTHESIZED; assign pin_name32 = ~SYNTHESIZED_WIRE_19; assign pin_name33 = ~SYNTHESIZED_WIRE_20; assign A = nqcurrmove[0] ~^ Button3; assign pin_name34 = ~SYNTHESIZED_WIRE_21; assign pin_name35 = ~SYNTHESIZED_WIRE_22;

34

assign RstFailCount = Reset & SYNTHESIZED_WIRE_23; \7448 b2v_inst25(

.A(SYNTHESIZED_WIRE_24),

.C(SYNTHESIZED_WIRE_25),

.D(SYNTHESIZED_WIRE_26),

.B(SYNTHESIZED_WIRE_27),

.RBIN(SYNTHESIZED_WIRE_78),

.BIN(SYNTHESIZED_WIRE_78),

.LTN(SYNTHESIZED_WIRE_78),

.OC(SYNTHESIZED_WIRE_33),

.OE(SYNTHESIZED_WIRE_35),

.OD(SYNTHESIZED_WIRE_34),

.OF(SYNTHESIZED_WIRE_36),

.OG(SYNTHESIZED_WIRE_37),

.OB(SYNTHESIZED_WIRE_32),

.OA(SYNTHESIZED_WIRE_31) );

assign pin_name1 = ~SYNTHESIZED_WIRE_31; assign pin_name2 = ~SYNTHESIZED_WIRE_32; assign pin_name3 = ~SYNTHESIZED_WIRE_33; assign B = nqcurrmove[1] ~^ Button2; assign pin_name4 = ~SYNTHESIZED_WIRE_34; assign pin_name5 = ~SYNTHESIZED_WIRE_35; assign pin_name6 = ~SYNTHESIZED_WIRE_36; assign pin_name7 = ~SYNTHESIZED_WIRE_37; \7448 b2v_inst34(

.A(qD2),

.C(qB2),

.D(qA2),

35

.B(qC2),

.RBIN(SYNTHESIZED_WIRE_79),

.BIN(SYNTHESIZED_WIRE_79),

.LTN(SYNTHESIZED_WIRE_79),

.OC(SYNTHESIZED_WIRE_43),

.OE(SYNTHESIZED_WIRE_45),

.OD(SYNTHESIZED_WIRE_44),

.OF(SYNTHESIZED_WIRE_46),

.OG(SYNTHESIZED_WIRE_47),

.OB(SYNTHESIZED_WIRE_42),

.OA(SYNTHESIZED_WIRE_41) );

assign pin_name8 = ~SYNTHESIZED_WIRE_41; assign pin_name9 = ~SYNTHESIZED_WIRE_42; assign pin_name10 = ~SYNTHESIZED_WIRE_43; assign pin_name11 = ~SYNTHESIZED_WIRE_44; assign C = nqcurrmove[2] ~^ Button1; assign pin_name12 = ~SYNTHESIZED_WIRE_45; assign pin_name13 = ~SYNTHESIZED_WIRE_46; assign pin_name14 = ~SYNTHESIZED_WIRE_47; \7448 b2v_inst43(

.A(SYNTHESIZED_WIRE_48),

.C(SYNTHESIZED_WIRE_49),

.D(SYNTHESIZED_WIRE_50),

.B(SYNTHESIZED_WIRE_51),

.RBIN(SYNTHESIZED_WIRE_80),

.BIN(SYNTHESIZED_WIRE_80),

.LTN(SYNTHESIZED_WIRE_80),

.OC(SYNTHESIZED_WIRE_57),

.OE(SYNTHESIZED_WIRE_59),

.OD(SYNTHESIZED_WIRE_58),

.OF(SYNTHESIZED_WIRE_60),

36

.OG(SYNTHESIZED_WIRE_61),

.OB(SYNTHESIZED_WIRE_56),

.OA(SYNTHESIZED_WIRE_55) );

assign pin_name15 = ~SYNTHESIZED_WIRE_55; assign pin_name16 = ~SYNTHESIZED_WIRE_56; assign pin_name17 = ~SYNTHESIZED_WIRE_57; assign pin_name18 = ~SYNTHESIZED_WIRE_58; assign pin_name19 = ~SYNTHESIZED_WIRE_59; assign D = nqcurrmove[3] ~^ Button0; assign pin_name20 = ~SYNTHESIZED_WIRE_60; assign pin_name21 = ~SYNTHESIZED_WIRE_61; \7448 b2v_inst52(

.A(SYNTHESIZED_WIRE_62),

.C(SYNTHESIZED_WIRE_63),

.D(SYNTHESIZED_WIRE_64),

.B(SYNTHESIZED_WIRE_65),

.RBIN(SYNTHESIZED_WIRE_81),

.BIN(SYNTHESIZED_WIRE_81),

.LTN(SYNTHESIZED_WIRE_81),

.OC(SYNTHESIZED_WIRE_71),

.OE(SYNTHESIZED_WIRE_73),

.OD(SYNTHESIZED_WIRE_72),

.OF(SYNTHESIZED_WIRE_74),

.OG(SYNTHESIZED_WIRE_75),

.OB(SYNTHESIZED_WIRE_70),

.OA(SYNTHESIZED_WIRE_69) );

assign pin_name22 = ~SYNTHESIZED_WIRE_69;

37

assign pin_name23 = ~SYNTHESIZED_WIRE_70; assign pin_name24 = ~SYNTHESIZED_WIRE_71; assign pin_name25 = ~SYNTHESIZED_WIRE_72; assign pin_name26 = ~SYNTHESIZED_WIRE_73; assign pin_name27 = ~SYNTHESIZED_WIRE_74; \74154 b2v_inst6(

.C(C),

.D(D),

.B(B),

.A(A), .O0N(SYNTHESIZED_WIRE_0), .O12N(SYNTHESIZED_WIRE_10), .O15N(SYNTHESIZED_WIRE_11), .O10N(SYNTHESIZED_WIRE_9), .O11N(SYNTHESIZED_WIRE_15), .O1N(SYNTHESIZED_WIRE_1), .O13N(SYNTHESIZED_WIRE_16), .O14N(SYNTHESIZED_WIRE_14), .O4N(SYNTHESIZED_WIRE_4), .O3N(SYNTHESIZED_WIRE_3), .O2N(SYNTHESIZED_WIRE_2), .O7N(SYNTHESIZED_WIRE_13), .O6N(SYNTHESIZED_WIRE_6), .O5N(SYNTHESIZED_WIRE_5), .O9N(SYNTHESIZED_WIRE_8), .O8N(SYNTHESIZED_WIRE_7));

assign pin_name28 = ~SYNTHESIZED_WIRE_75; assign Reset = Rst & GameOver; scoreKeeper b2v_inst8(

.Clk(Clk_ALTERA_SYNTHESIZED1),

.Rst(Reset),

38

.increment(SYNTHESIZED_WIRE_76),

.qA1(SYNTHESIZED_WIRE_26),

.qB1(SYNTHESIZED_WIRE_25),

.qC1(SYNTHESIZED_WIRE_27),

.qD1(SYNTHESIZED_WIRE_24),

.qA2(qA2),

.qB2(qB2),

.qC2(qC2),

.qD2(qD2),

.qA3(SYNTHESIZED_WIRE_50),

.qB3(SYNTHESIZED_WIRE_49),

.qC3(SYNTHESIZED_WIRE_51),

.qD3(SYNTHESIZED_WIRE_48),

.qA4(SYNTHESIZED_WIRE_64),

.qB4(SYNTHESIZED_WIRE_63),

.qC4(SYNTHESIZED_WIRE_65),

.qD4(SYNTHESIZED_WIRE_62)); \74138 b2v_inst9(

.A(pin_name29),

.B(pin_name30), .C(pin_name31), .Y0N(SYNTHESIZED_WIRE_19), .Y1N(SYNTHESIZED_WIRE_20), .Y2N(SYNTHESIZED_WIRE_21), .Y3N(SYNTHESIZED_WIRE_22), .Y4N(GameOver) );

assign Combo = Combo_ALTERA_SYNTHESIZED; assign Clk1 = Clk_ALTERA_SYNTHESIZED1; endmodule Fail Counter Module: module testBench;

39

//connect the two modules wire rst; wire qA,qB,qC; wire clk; wire start; failcounter mycounter(qA,qB,qC, clk, rst,start); testIt aTester(clk,rst,start,qA,qB,qC); endmodule module failcounter(qA,qB,qC, clk,rst,start); output qA,qB,qC; input clk,rst,start; wire Da,Db,Dc,clk,rst,start; //FF A dFlipFlop dffa(qA, nqA, Da, clk, rst,start); //FF B dFlipFlop dffb(qB, nqB, Db, clk, rst,start); //FF C dFlipFlop dffc(qC, nqC, Dc, clk, rst,start); //Da and and1(Da, nqA, nqC); //Db xor xor1(Db, qA, qB); //Dc and and2(Dc, qA, qB); endmodule module dFlipFlop(q, nq, D, clk, rst,start); input D, clk,rst,start; output q, nq; reg q; not n1(nq, q); not n2(nrst,rst);

40

not n3(nstart, start); always@ (posedge nrst or posedge clk) begin if(nrst) q = 0;

else if(nstart) q = q;

else q = D; end endmodule