CPU Overview Computer Organization II 1 February 2009 ©2006-09 McQuain & Ribbens Introduction CPU performance factors – Instruction count n Determined

CS@VT February 2009 ©2006-09 McQuain & Ribbens

CPU Overview

Computer Organization II

1IntroductionCPU performance factors

– Instruction count Determined by ISA and compiler

– CPI and Cycle time Determined by CPU hardware

We will examine two MIPS implementations– A simplified version– A more realistic pipelined version

Simple subset, shows most aspects– Memory reference: lw, sw– Arithmetic/logical: add, sub, and, or, slt– Control transfer: beq, j


CPU Overview


2Instruction Execution

PC instruction memory, fetch instruction

Register numbers register file, read registers

Depending on instruction class– Use ALU to calculate

Arithmetic result Memory address for load/store Branch target address

– Access data memory for load/store– PC target address or PC + 4


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3CPU Overview


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4Need for Selection Mechanisms

Compute address for sequential execution.

Compute address for conditional branch.

Must choose which one goes back to PC. BUT, you cannot just

join wires together to achieve this…


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5Multiplexor

An 2n x 1 multiplexor receives 2n input bits and n selector bits, and outputs exactly one of the input bits, determined by the pattern of the selector bits.

2 x 1 multiplexor

C A S B S

4 x 1 multiplexor

103102101100 SSISSISSISSIOut


CPU Overview


6Need for Control Logic

There must be a combinational circuit that determines which input should be selected and passed through to the PC.

The 2x1 multiplexor must have a 1-bit control line to select between the two inputs.

So, under when should the conditional address be used?

… if we're executing a conditional branch instruction and the condition has evaluated to true.


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7Control Questions

What goes here? What control settings will the ALU need?

What's the logic for controlling the other MUXes?


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8Logic Design Basics

Information encoded in binary– Low voltage = 0, High voltage = 1– One wire per bit– Multi-bit data encoded on multi-wire buses

Combinational elements– Operate on data– Output is purely a function of input

State (sequential) elements– Store information– Output/state depends on input and on previous state


CPU Overview


9Combinational Elements

AND-gate– Y = A & B

AB Y

I0I1 Y

Mux

S

Multiplexer– Y = S ? I1 : I0

A

BY+

A

B

YALU

F

Adder– Y = A + B

Arithmetic/Logic Unit– Y = F(A, B)


CPU Overview


10Sequential Elements

Register: stores data in a circuit– Uses a clock signal to determine when to update the stored value– Edge-triggered: update when Clk changes from 0 to 1

D

Clk

QClk

D

Q


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11Sequential Elements

Register with write control– Only updates on clock edge when write control input is 1– Used when stored value is required later

D

Clk

QWrite

Write

D

Q

Clk


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12Clocking MethodologyCombinational logic transforms data during clock cycles

– Between clock edges– Input from state elements, output to state element– Longest delay determines clock period


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13Building a Datapath

Datapath– Elements that process data and addresses

in the CPU Registers, ALUs, mux’s, memories, …

We will build a MIPS datapath incrementally– Refining the overview design


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14Instruction Fetch

32-bit register

Increment by 4 for next instruction


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15R-Format Instructions

Read two register operandsPerform arithmetic/logical operationWrite register result


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16Load/Store InstructionsRead register operandsCalculate address using 16-bit offset

– Use ALU, but sign-extend offsetLoad: Read memory and update registerStore: Write register value to memory


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17Branch Instructions

Read register operandsCompare operands

– Use ALU, subtract and check Zero outputCalculate target address

– Sign-extend displacement– Shift left 2 places (word displacement)– Add to PC + 4

Already calculated by instruction fetch


CPU Overview


18Branch Instructions

Justre-route

wires

Sign-bit wire replicated

Documents

CPU Overview Computer Organization II 1 February 2009 ©2006-09 McQuain & Ribbens Introduction CPU performance factors – Instruction count n Determined