CPU Design ProjectCPU Design ProjectSynthesis ReportSynthesis Report

ELEC 7770-001 - Dr. AgrawalELEC 7770-001 - Dr. Agrawal

Lee W. LernerLee W. Lerner

April 24, 2007April 24, 2007

OutlineOutline

Synthesis GoalsSynthesis Goals Synthesis Design FlowSynthesis Design Flow

• Mentor Graphics IC Flow Design ToolsMentor Graphics IC Flow Design Tools• Various other software tools used for design Various other software tools used for design

debugging and verificationdebugging and verification Synthesis ResultsSynthesis Results

• Area and Delay reportsArea and Delay reports• Netlist verificationNetlist verification

ConclusionsConclusions• Suggestions for improvementSuggestions for improvement

Synthesis GoalsSynthesis Goals Take a verified design modeled in Take a verified design modeled in

hardware description language (VHDL in hardware description language (VHDL in our design project)our design project)

Generate a gate- level netlist for the Generate a gate- level netlist for the circuit that optimizes either:circuit that optimizes either:• 1. Area1. Area• 2. Delay2. Delay• 3. Both (to a lesser extent)3. Both (to a lesser extent)

Verify functionality of netlists generatedVerify functionality of netlists generated Decide on synthesized netlist to proceed Decide on synthesized netlist to proceed

with in project design flowwith in project design flow

Synthesis Design FlowSynthesis Design Flow

Mentor Graphics IC Design Flow tools Mentor Graphics IC Design Flow tools used:used:• Leonardo Spectrum 8Leonardo Spectrum 8

Synthesize gate-level netlists optimized for Synthesize gate-level netlists optimized for area and delay from provided VHDL CPU area and delay from provided VHDL CPU designdesign

• FlextestFlextest Verify that synthesized gate-level netlists Verify that synthesized gate-level netlists

compilecompile

Synthesis Design FlowSynthesis Design Flow Leonardo Spectrum 8Leonardo Spectrum 8

V. P. Nelson, V. P. Nelson, Tutorial Documents for Mentor Graphics ToolsTutorial Documents for Mentor Graphics Tools, , http://http://www.eng.auburn.edu/department/ee/mgc/mentor.htmlwww.eng.auburn.edu/department/ee/mgc/mentor.html

Synthesis Design FlowSynthesis Design Flow

Netlists generated and corresponding Netlists generated and corresponding reports:reports:• 1. Area Optimization (CPU_areaOpt.edf)1. Area Optimization (CPU_areaOpt.edf)

Area report: areaOpt_areaReportArea report: areaOpt_areaReport Delay report: areaOpt_delayReportDelay report: areaOpt_delayReport

• 1. Delay Optimization (CPU_delayOpt.edf)1. Delay Optimization (CPU_delayOpt.edf) Area report: delayOpt_areaReportArea report: delayOpt_areaReport Delay report: delayOpt_delayReportDelay report: delayOpt_delayReport

Synthesis ResultsSynthesis Results areaOpt_areaReportareaOpt_areaReport

Synthesis ResultsSynthesis Results areaOpt_delayReportareaOpt_delayReport

Synthesis ResultsSynthesis Results delayOpt_areaReportdelayOpt_areaReport

Synthesis ResultsSynthesis Results delayOpt_delayReportdelayOpt_delayReport

Synthesis ResultsSynthesis Results Netlist comparisonNetlist comparison

Area Optimization Number of ports 111

Number of nets 8249

Number of instances 7601

Number of references to this view 0

Number of gates 16264

Number of accumulated instances 7601

data arrival time 18.06 ns

Delay Optimization Number of ports 111

Number of nets 8343

Number of instances 7696

Number of references to this view 0

Number of gates 16280

Number of accumulated instances 7696

data arrival time 18.22 ns

Synthesis ResultsSynthesis Results Synthesis Verication: FlexTestSynthesis Verication: FlexTest

Need for Need for DFT (scan DFT (scan design)design)

Netlists Netlists compile compile correctlycorrectly

ConclusionsConclusions

Used Leonardo Spectrum 8 to Used Leonardo Spectrum 8 to generate gate-level netlists generate gate-level netlists optimized for area and delay optimized for area and delay independentlyindependently

Netlists compile correctlyNetlists compile correctly Due to area and delay similarity Due to area and delay similarity

between generated netlists it was between generated netlists it was decided that we could proceed with decided that we could proceed with either netlist in the design projecteither netlist in the design project

ConclusionsConclusions

Suggestions for improvementSuggestions for improvement• Improved communication between team Improved communication between team

members (i.e. weekly status members (i.e. weekly status reports/presentations)reports/presentations)

Every team member has input at each stage Every team member has input at each stage in the designin the design

Identify coding and design errors earlierIdentify coding and design errors earlier Identify need for and implement DFT before Identify need for and implement DFT before

synthesissynthesis Improved CPU design in a shorter timeImproved CPU design in a shorter time