CPT Week, Nov 2003, B. Paul Padley, Rice University1 CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003

CPT Week, Nov 2003, B. Paul Padley, Rice University 1

CSC Trigger Status, MPC and CSC Trigger Status, MPC and SorterSorter

CSC Trigger Status, MPC and CSC Trigger Status, MPC and SorterSorter

B. Paul Padley

Rice University

November 2003


Strip FE cards

Wire FE cards

Muon Port Card(Rice)

MPC

Sector Receiver/ Processor(U. Florida)

OPTICAL

SR/SP SP

CSC Muon Sorter(Rice)

Global Trigger

DTRPC

FE

FE

Global L1

2 / chamber

3 / port card

3 / sector

4

4

4 4

LCT

Trigger Motherboard

(UCLA)

Wire LCT card

In counting

house

TMB

LCT

RPC Interface Module

RIM

On-Chamber Trigger Primitives

3-D Track-Finding and Measurement

CSC Muon Trigger SchemeCSC Muon Trigger SchemeCSC Muon Trigger SchemeCSC Muon Trigger SchemeEMU Trigger


VME J1 CONNECTOR

CUSTOM PERIPHERAL BACKPLANE

9U x 400 MM BOARD

FINISAR FTRJ-8519-1-2.5OPTICAL TRANSCEIVERS

TLK2501 SERIALIZERS

CCBINTERFACE

SORTINGLOGIC

INPUTAND

OUTPUTFIFO

VMEINTERFACE

3 OPTICALCABLES TOSECTORPROCESSOR

TMB_1

TMB_2

TMB_3

TMB_4

TMB_5

TMB_6

TMB_7

TMB_8

TMB_9

SER

SER

SER

OPTO

OPTO

MPC Block Diagram

OPTO

SN74GTLP18612 GTLP TRANSCEIVERS

FPGA

CCB

CCB

UCLA MEZZANINE CARD (XCV600E)

MPC Block DiagramMPC Block DiagramMPC Block DiagramMPC Block DiagramRice


Mezzanine cardTLK2501 serializersOptomodules

GTLPReceivers

VMEInterface(glue logic)

Muon Port CardMuon Port CardMuon Port CardMuon Port CardRice


MPC Design StatusMPC Design StatusMPC Design StatusMPC Design Status

3 boards were fabricated and assembled in summer 2002

Tested MPC standalone (sorter logic) and with one and two Trigger Motherboards and full-size custom backplane

Rice


UCLA Cosmic Ray TestUCLA Cosmic Ray TestUCLA Cosmic Ray TestUCLA Cosmic Ray Test

Cosmic Ray tests were performed at UCLA in preparation for time structured test beam during spring 2003


Beam Test With 2 CSC’s at X5aBeam Test With 2 CSC’s at X5aBeam Test With 2 CSC’s at X5aBeam Test With 2 CSC’s at X5a

/


Beam Test SetupBeam Test SetupBeam Test SetupBeam Test Setup

Peripheral Crate2 DMB, 2 TMB1 CCB, 1 MPC

FED crate 1 DDU

PC

TTC crate

DAQ Data

Trigger primitives

S1 S2 S3

beam

CSC 1 CSC 2

Track Finder CrateTRIDAS

2 CSC’s, all on-chamber boards

Up to 80K events read out in 2.6s spill


CSC Peripheral CrateCSC Peripheral CrateCSC Peripheral CrateCSC Peripheral CrateFrom front-end cards

Muon Port Card (MPC), which sends trigger primitives on optical links

Clock & Control Board (CCB) with TTCrm


Test PerformedTest PerformedTest PerformedTest Performed

Compare• MPC output LCTs stored in FIFO on MPC

• TMB output LCTs extracted from DDU data

List of checks• Bit errors in data transmission

• Data acceptance from 2 TMBs

• Sending MPC winner bit to TMB

• Sorting of LCTs based on “Quality Bits”


Results from summer beam testResults from summer beam testResults from summer beam testResults from summer beam test

During time structured beam in the summer the set of tests were repeated successfully

Note this was using clock distribution from TTCmi->TTCvi->TTCrm on CCB

Existing TTCrm adequate for Intracrate functionality. Also adequate for DAQ path (which uses crystal oscillators to clock links since they are asynchronous)

However, MPC->SP communication failed.

TTC Jitter one of the problems.


TTC QPLL Mezzanine cardTTC QPLL Mezzanine cardTTC QPLL Mezzanine cardTTC QPLL Mezzanine card Three made available to

CSC group for testing during Sept.03 structured beam test

Provides stable clock signalsat 40, 80, and 160 MHz at correct LHC frequency

Installed on Clock and Control Board (CCB) with 40 MHz clean clock sent to backplane and 80 MHz clock sent by twisted pair to SP and MPC

• Noticed that CCB commands have 1 BX extra latency with TTCRq

TTCRq


PLL ResultsPLL ResultsPLL ResultsPLL Results

Using either the home-built VCXO+PLL solution or the CERN QPLL solution for the 80 MHz reference clock to TLK2501 receivers:

• PLL locks to incoming machine clock

• Measured frequency: 40.078893(1) MHz

• No errors on optical links reported over many hours of PRBS and data tests

Data successfully logged by both CSC DAQ and CSC Track-Finder readout

• SP data FIFO synchronized to L1A


TTCRq (QPLL) Test ResultsTTCRq (QPLL) Test ResultsTTCRq (QPLL) Test ResultsTTCRq (QPLL) Test Results

QPLL 80 MHz clock directly to MPC transmitters & home-built VCXO+PLL for SP receivers:

• No link errors for 20 minute PRBS test

QPLL 80 MHz clock directly to SP receivers andMPC uses default clock multiplier:

• No link errors for 15 minute PRBS test• Successfully logged data for 10K events (run 5151)

QPLL 40 MHz clock on TF crate backplaneand SP uses DLL in FPGA for clock multiplier:

• Solution tried for Phase 1 (May) structured beam running• Link errors observed in PRBS test

TTCRq on CCB in peripheral crate• Able to take data with same trigger efficiency

(i.e. TTCRq works for peripheral crate electronics as well and is compatible with TTCRm)


Results from Sept Beam testResults from Sept Beam testResults from Sept Beam testResults from Sept Beam test

Intracrate tests successfully repeated

This time PLL patch was used to stabilize clocking of optical links in the trigger path

MPC to SP communication now successful

Last day of run got hold of TTCrq an again the test was successful.


VME J1 CONNECTOR

CUSTOM BACKPLANE

9U * 400 MM BOARD

68-pin CONNECTORS

SN75LVDS387 DRIVERS

CCB INTERFACE

SORTERLOGIC

INPUT AND

OUTPUTFIFO

VME & JTAGINTERFACE

SP1

SP2

SP3

SP4

SP5

SP6

SP7

SP8

SP9

SP10

SP11

SP12

SHIELDED TWISTEDPAIR CABLES TO GMT CRATE

GTLP TRANSCEIVERS

MEZZANINE CARDVIRTEX XC2V4000

Muon Sorter Block DiagramMuon Sorter Block DiagramMuon Sorter Block DiagramMuon Sorter Block DiagramRice


VME/JTAG INTERFACE

GTLP BACKPLANEINTERFACE

MEZZANINECARDLVDS

DRIVERSAND SCSI-3CONNECTORS

Muon SorterMuon SorterMuon SorterMuon Sorter


Trackfinder crate at RiceTrackfinder crate at RiceTrackfinder crate at RiceTrackfinder crate at Rice

Sector Processor

CCB

Sorter


• Comprises: - Sorter “4 out of 36” based on 7-bit Rank - Output LUT - Input and output FIFO buffers for testing purposes - “Winner” logic - CCB interface - VME interface (A24D16 slave + Geographical Address)

• Based on Xilinx XC2V4000-5FF1152C, common mezzanine card with the Sector Processor

• Latency – 135 ns

FPGA DesignFPGA DesignFPGA DesignFPGA Design


Muon Sorter Status and PlansMuon Sorter Status and PlansMuon Sorter Status and PlansMuon Sorter Status and Plans

Have 4 boards in hand, one is stuffed (except backplane interface)

Have a dedicated Wiener 9U crate with VME J1 backplane and custom

Track Finder backplane installed

Sector Processor – to – MS interface test currently underway


MilestonesMilestonesMilestonesMilestones

Sep-02 Prototype construction:

• MPC done,

• CCB done • waiting for new TTCrq, and will then redo

• As a result of TTCrx Jitter problem need resdesign with TTcrq

• Muon Sorter Done

Rice


More MilestonesMore MilestonesMore MilestonesMore Milestones

• Apr-03 Prototype testing done: Underway

• Sep-03 Final designs done

• MPC significantly delayed (until summer ’04)

• Although MPC prototype was completed summer ’02, integration testing of it will not be completed until spring ‘04

• Oct-04 Production done

• At risk given the final design schedule

• Apr-05 Installation done

Documents

CPT Week, Nov 2003, B. Paul Padley, Rice University1 CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003