CprE 288 – Introduction to Embedded Systems

CprE 288 – Introduction to Embedded Systems

http://class.ece.iastate.edu/cpre288 1

Instructors:

Dr. Phillip Jones

Announcements


• HW 6: Due Sunday (10/03)

• Quiz 6: Tuesday (10/5) – First 10 minutes of class using

Canvas

– Class lectures

– HW 4 & 5 & 6 material

– Notes: Once sheet of notes (1-side)

• Exam 1: Thursday 10/7

Overview

• Announcements

• Interrupts

– Tiva TM4C123GH6PM Datasheet (~8 pages) • Chapter 2.5 – 2.54 (focus on Interrupt type Exceptions)

– Table 2.9

• Chapter 3. 4 NVIC registers

– Enable (ENx)

– Priority (PRIx)

• GPIO Interrupt Control : 10.2.2

– Textbook reading:

• Section 2.4 (pg. 34-37)

• Chapter 5.1, 5.3.2


Microcontroller / System-on-Chip (SoC)


CPU Program

Memory

Microcontroller Outside

World

NVIC UART

ADC

Timers

CFG|DATA|STATUS

CFG|DATA|STATUS

CFG|DATA|STATUS

GPIO

GPIO_DATA

Port X

(8-b

its)

7 6

5

4

3

2

1

0

Devices Interrupts

AFSEL

PCTL

0 1

0

X

Y

Data

Memory

ISR (INTERRUPT SERVICE ROUTINES)


Interrupts and Interrupt Service Routines (ISRs)


• Interrupt: A mechanism that allows hardware to inform the CPU that an event has occurred. Example hardware events:

– Button connected to an GPIO port pressed

– Data arrives to the system. e.g. new byte on UART interface, new sample from analog to digital converter (ADC)

– Timer expires or Timer becomes equal to a given value

– CPU tries to execute an invalid assembly instruction

• Interrupt Service Routine (ISR): code to be executed to deal with the hardware event that has occurred. Also referred to as an Interrupt handler.

General Interrupt to ISR flow


1. Hardware event causes an interrupt to occur

2. Interrupt notifies the CPU

3. CPU pauses the program

4. CPU disables interrupts and saves its “state”

–The CPU state is the information the CPU needs to un-pause the program properly. e.g. location of the instruction when the paused occurred, current CPU register values

5. CPU re-enables interrupts and executes the proper ISR

6. Once the ISR completes, the CPU disables interrupts and restores its state to what it was before the interrupt occurred

7. CPU re-enables interrupts, and continues the program from where it paused.

Nested Vector Interrupt Controller (NVIC)


•NVIC: the name of the hardware on the CPRE 288 microcontroller chip that manages interrupts

– Notifies CPU when an interrupt occurs

– Programmer configures to enable/disable specific interrupts

– Programmer configures to give interrupts priorities

– Provides the CPU with information for accessing an Interrupt Vector Table, which stores the starting address (i.e. entry point) of each ISR.

• Interrupt Vector Table: Each row in this table (located in memory) contains the address of the starting instruction for each ISR. The CPU uses this information to start execution of the ISR that has been “triggered” by a corresponding Interrupt (i.e. hardware) event)

Interrupt Service Routine (ISR) Setup


1. Enable the interrupt: (every interrupt has an enable bit): Use the datasheet to find the register name and bit position you need to set.

• Find the interrupt number on page 104 of the datasheet and set a 1 to its bit in the NVIC_ENn_R register. Where n is 0-4 and indicates a group of 32 interrupts (i.e. 0 -> 0-31, 1-> 32-63, etc). The bit you set is the (interrupt number - (32*n))th bit.

2. Bind the handler (i.e. indicate where to go when an interrupt event occurs)

• Find the corresponding Interrupt vector number for your interrupt. (datasheet, page 104). Alternatively the timer interrupt vectors are defined as INT_TIMERxn where x is 0-5 and n is A or B.

• Call IntRegister(interrupt vector number, handler name) to bind the interrupt(s) to your handler (i.e. ISR name). IntRegister can be found in interrupt.h

3. Write the ISR (Interrupt Service Routine) • The ISR is a function, or block of code, the CPU will call for you

whenever the interrupt event occurs. You define/program what type of processing should occur for a given type of interrupt event.

15

Microcontroller / System-on-Chip (SoC)


CPU Program

Memory

Microcontroller Outside

World

NVIC UART

ADC

Timers

CFG|DATA|STATUS

CFG|DATA|STATUS

CFG|DATA|STATUS

GPIO

GPIO_DATA

Port X

(8-b

its)

7 6

5

4

3

2

1

0

Devices Interrupts

AFSEL

PCTL

0 1

0

X

Y

Data

Memory

Generic Interrupt Controller


Global Interrupt.

⋯ Local Interrupt Control Reg.

⋯

Local Interrupt Flag Reg.

⋯

Interrupt Controller

Control Reg

CPU Program

Memory Data

Memory

Microcontroller

ISR

NVIC – GPIO Example


NVIC_ENx_R

⋯

GPIO_PORTx_IM_R

⋯

GPIO_PORTx_RIS_R

⋯

NVIC

GPIO_PORTx_MIS_R

Local Device



NVIC_ENx_R

⋯

NVIC

⋯

⋯

⋯

GPIO_PORTx_RIS_R

⋯

GPIO_PORTx_IEV_R

⋯

GPIO_PORTx_IBE_R

⋯

GPIO_PORTx_IS_R High

Level

Low

Level

Rising

Edge Falling

Edge

Bit-wise OR

Bit-wise OR

⋯

GPIO_PORTx_IM_R

GPIO_PORTx_MIS_R



⋯ ⋯

⋯

GPIO_PORTx_RIS_R

⋯ GPIO_PORTx_IEV_R

⋯ GPIO_PORTx_IBE_R

⋯ GPIO_PORTx_IS_R

High

Level

Low

Level

Rising

Edge Falling

Edge

Bit-wise OR

Bit-wise OR

⋯

GPIO_PORTx_IM_R

GPIO_PORTx_MIS_R Which input triggers an interrupt?

GPIO_PORTx_IS_R: Interrupt Sense Reg

1 => level-sensitive interrupts

0 => edge-sensitive interrupts

(pg. 664)

24

GPIO_PORTx_IBE_R: Interrupt Both Edges Reg.

0 => Interrupt generation via GPIO_PORTx_IEV register

1 => Both edges trigger interrupt

(pg. 665)

25

GPIO_PORTx_IEV_R: Interrupt Event Reg.

0 => Interrupt generation via Low level or falling edge

1 => Interrupt generation via High level or rising edge

(pg. 666)

26

GPIO_PORTx_IM_R: Interrupt Mask Reg.

0 => Interrupt is masked

1 => Interrupt can be sent to interrupt controller

(pg. 667)

27

GPIO_PORTx_RIS_R: Raw Interrupt Status Reg.

0 => An interrupt has not occurred

1 => An interrupt has occurred

(pg. 668)

28

GPIO_PORTx_MIS_R: Masked Interrupt Status Reg.

0 => Interrupt is masked or has not occurred

1 => An interrupt has occurred and was sent to the interrupt controller

(pg. 669)

29

GPIO_PORTx_ICR_R: Interrupt Clear Reg.

0 => Interrupt is unaffected

1 => An interrupt has been cleared

(pg. 670)

30

NVIC_Enx_R: NVIC Enable Reg.

Four register groups (EN0 → EN3) which indicate whether an interrupt is enabled or disabled in the NVIC

• Table 2-9 (pg 104) has interrupt assignments

31

IntRegister(INT_GPIOx, gpiox_handler)

Function that binds interrupts between “GPIOx” and the handler function “gpiox_handler”

32

Documents

CprE 288 – Introduction to Embedded Systems