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CPLB management

April 2007Jerry Zeng

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What is CPLB ?

CPLB: Cacheability Protection Lookaside BufferCache:

collection of data duplicating original values stored elsewhere or computed earlier, where the original data is expensive (usually in terms of access time) to fetch or compute relative to reading the cache

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Cache

Direct mapped cache 2-way cache

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Instruction CacheBank

Only one bank can be set as cacheBank size is 16K bytes.

Sub-bank Each sub-bank is 4k bytes.One bank has 4 sub-banks.Needs 2-bits to identify each sub-bank.

4-way cacheEach sub-bank is organized as 4-way cache.Each way is 1K bytes.Each way is independent with each other.Each way has 32 lines, needs 5-bits to identify.Each lines has 64 words. These words are continuous in memory.

Diagram of instruction cache

Instruction cache line

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Data Cache

BankEach bank is 16K bytes size. May set one or two banks as data cache.

Half-bank Each sub-bank is 8k bytes.One bank has 2 half-banks.

Sub-bankEach sub-bank is 4k bytes.Each sub-bank is organized as 2-way cache.Each way is independent with each other.

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Data Cache Configuration – DCBS=1Independent cache

Each bank can be configured as one 16k bytes, 2-way cache.Bank A and bank B can be set as two 16k bytes, 2-way cache at

the same time, A[23] selects the cache.Each bank serves an alternating 8M byte blocks of memory.

Data cache configuration – DCBS=0One 32K, 2-way cache

Only when two banks are set as cache and DCBS=0.A[14] selects cache.Each bank serves an alternating 16K byte blocks of memory.Two blocks of memory are continuous.

I-Cache OperationsHits and Misses

Address for an instruction request from the core does or not match a valid entry in the cache.

Line FillsFetching 32 bytes from memory.4x64 bits from line buffer, 8x32 bits from EAB.

Line ReplacementFirst check invalid entries. Priority: Way0,Way1,Way2,Way3.LRU (least recently used) algorithm when no invalid entries.

D-Cache OperationsCache status

Invalid.Exclusive (valid and clean).Modified (valid and dirty).

Write methodWrite-through : write to external memory upon write to cacheWrite-back: write to external memory when replace or load the line

Data cache flushSynchronize the specified cache line with external memory.

Data cache invalidationCase 1: flush is required.Case 2: flush is not required.

CPLB and CPLB managementCache

Disable/Enable I-cache and D-cache.Register: DMEM_CONTROL

MemoryBased on page management. Consists of CPLB descriptors. One descriptor, one page.Total 16 ICPLB and 16 DCPLB descriptors.

I-CPLB descriptorTotal 16 descriptors (entries).Registers: ICPLB_ADDR, ICPLB_DATA

D-CPLB descriptorTotal 16 DCPLB descriptors (entries).Registers: DCPLB_ADDR, DCPLB_DATA

CPLB and CPLB managementPage attributes

Be configured in ICPLB_DATA and DCPLB_DATAPage size: 1K, 4K, 1M, 4M bytes.Page cacheable or non-cacheable.Write-through or write-back when cacheable.Dirty or modified.Super and user write access permission.User read access permission.Entry data valid or invalid.Lock (no permit replacement).

Address comparingEvery fetch, load, store operation

CPLB managementHardware

Address compare.Trigger exception when no valid CPLB descriptor.Writes exception trigger source in register SEQSTAT.Writes faulting address in ICPLB_FAULT_ADDR or

DCPLB_FAULT_ADDR.Place CPU into supervisor mode.Place PC to vector of exception.

SoftwareCheck exception trigger source.

Data CPLB protection violationData access multiple CPLB hitsData access CPLB missInstruction CPLB protection violationInstruction access multiple CPLB hitsInstruction access CPLB miss

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Critical Registers

DMEM_CONTROL ICPLB_DATAx ICPLB_ADDRxDCPLB_DATAxDCPLB_ADDRx ICPLB_STATUSDCPLB_STATUSDCPLB_FAULT_ADDR ICPLB_FAULT_ADDR

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External Memory - SDRAM Kernel

Page size: 4M bytesCacheableUser read access permission for InstructionUser read, write and super write access permission for dataFor data, write back or write through.For data, cache line read and write permissionCPLB validLockDirty for data, replacement permission

GenericThe same with kernel except lock

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External Memory - Flash Instruction

Page size: 4M bytesUser read access permissionCPLB valid

DataPage size: 4M bytesCPLB validNon-cacheable

External Memory – MAC buffer

Page size: 4M bytesCPLB validNon-cacheable

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External Memory – External Device Register

Page size: 4M bytesCPLB validNon-cacheable

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Blackfin KernelL1 Memory Instruction

Page size: 1M bytesUser read permissionLockCPLB validNon-cacheable

DataPage size: 4M bytesUser read and write permissionSuper write permissionCPLB validNon-cacheable