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CPE/EE 421 Microcomputers: Introduction Instructor: Dr Aleksandar Milenkovic Lecture Notes

CPE/EE 421 Microcomputers: Introduction Instructor: Dr Aleksandar Milenkovic Lecture Notes

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Page 1: CPE/EE 421 Microcomputers: Introduction Instructor: Dr Aleksandar Milenkovic Lecture Notes

CPE/EE 421 Microcomputers:Introduction

Instructor: Dr Aleksandar MilenkovicLecture Notes

Page 2: CPE/EE 421 Microcomputers: Introduction Instructor: Dr Aleksandar Milenkovic Lecture Notes

CPE/EE 421/521 Microcomputers

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CPE/EE 421 Microcomputers

Syllabus textbook & other references grading policy important dates course outline

Prerequisites memory organization decoding combinatorial and sequential logic important for system architecture

Microcomputer Lab (EB 106) Introduction sessions Lab instructor

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CPE/EE 421 Microcomputers

LAB Session on-line LAB manual Access cards Accounts

Lab Assistant: Joel Wilder Lab sessions

Lab session #1: Monday 6:00 – 8:00 PM Lab session #2: Monday 8:00 – 10:00 PM

Sign-up sheet - if needed

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Outline

Embedded systems: structure and organization

Applications Technology Trends Historical perspective

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Microcomputers

Stand alone system based on a microprocessor

An embedded system – dedicated to a specific application control system/monitoring system optimization for a single function

(system resources, extension, …) block diagram

inputs processing outputs Number of microprocessors

in our environment?

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A Microcontroller-Based System

LCD

Switches

RS232 controller

Thermistor

Analog I/O

RS232

2-axes joystick

Adj. Vol. Regul.

LEDs

CKeypad

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Wireless Body Area Network

PersonalServer

Em ergency Server

Physic ian’s Server

M edical Server(M ayo C lin ic)

GP R S

ZigBee orcustom w ire less

I nternet

BodyArea

N etw ork

P PG &m ovem ent sensor

M ovem entsensors

ECG &tilt sensor

W ire less gatew ay &tem perature/

hum id ity sensor

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Data Flow

P 78 ºINPUT PROCESSING OUTPUT

control signalsTemperature sensor

t, states A/DP

systemD/A

Input Processing Output

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Microcomputer Block Diagram

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Microprocessor System Architecture

System Architecture Single Board Computers (SBC) block diagram (modules, cards)

System bus Multibus, VME, ISA, PCI, … Multiple masters

CPU Clock and CPU Control Circuits

1 MHz - 1 GHz power-up and reset circuits

Address Decoder Address and Data Bus Buffers Bus Arbitration Control Memory management

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Microprocessor System Architecture

Memory Module Virtual memory / Physical memory ROM, RAM, video memory static/dynamic

Peripheral Module serial interface

RS232 (CRT, mouse), USB, Firewire (IEEE 1394)

parallel interface printer interface

timer time/frequency measurement

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Microprocessor System Architecture

PC architecture

ISA

PCI

Memory

CPU

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Von Neumann Architecture

Processing Elements sequential execution

Read/Write Memory linear array of fixed size cells Data and instruction store

I/O unit Address/Data/Control bus

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Von Neumann Architecture

Von Neumann Architecture

PE(Processing Element)

Control Unit

ALU

Read/WriteMemory

I/O(peripherals)

address

control

data

0

1

2

3

N

Memory

log2N

W bits

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Von Neumann vs. Harvard

PE(Processing Element)Read/Write

Memory

address

data

PE(Processing Element)

ProgramMemory

DataMemory

Von Neumann Architecture

Harvard Architecture

address

data

data

address

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Block Diagram of a Personal Computer

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A Typical Small Embedded System – Digital Thermometer

Todd D. MortonEmbedded Microcontrollers

Copyright ©2001 by Prentice-Hall Inc.

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A Microcontroller-Based System

Todd D. MortonEmbedded Microcontrollers

Copyright ©2001 by Prentice-Hall Inc.

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Computing History

Eniac, 1946 (first stored-program computer)Occupied 50x30 feet room, weighted 30 tonnes, contained 18000 electronic valves, consumed 25KW of electrical power;capable to perform 100K calc. per second

PlayStation Portable (PSP) Approx. 170 mm (L) x 74 mm (W) x 23 mm (D) Weight: Approx. 260 g (including battery) CPU: PSP CPU (clock frequency 1~333MHz) Main Memory: 32MB Embedded DRAM: 4MB Profile: PSP Game, UMD Audio, UMD Video

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Understanding computers ….

User perspective Applications: What do we do with them? Price: How much do they cost?

To purchase and to operate Convenience: How difficult is to use them?

Designer perspective Size: How large are they? (UP) Speed: How many operations …? (UP) Power: What is energy consumed? (UP) Complexity: How complex are they to

build?

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Engineering Computers

Evaluate ExistingEvaluate ExistingSystems for Systems for BottlenecksBottlenecks

Simulate NewSimulate NewDesigns andDesigns and

OrganizationsOrganizations

Implement NextImplement NextGeneration SystemGeneration System

TechnologyTrends

Benchmarks

Workloads

ImplementationComplexity

ApplicationsMarket

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Intel: First 30+ Years

Intel 4004 November 15, 1971 4-bit ALU, 108 KHz, 2,300 transistors,

10-micron technology Intel Pentium 4

August 27, 2001 32-bit architecture, 1.4

GHz (now 3.08), 42M transistors (now 55+M), 0.18-micron technology (now 0.09)

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Technology Directions: SIA Roadmap

Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735 .580 .255 .110 .049 .022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm2) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183

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Trends & Challenges

Processor/memory discrepancy Memory hierarchy On-chip/off-chip memory

Microprocessor execution Fetch > Decode > Execute

System on a chip - Microcontroller Cost, smaller PCB, reliability, power. Applications

Evolution Microprocessor Microprocessor-on-a-chip System-on-a-chip Distributed-system-on-a-chip

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More on Challenges

Scalability billions of small devices performance

Availability hardware changes system upgrade failures code enhancements

Fault tolerance

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Performance Trends

Year Proc. MIPS1969 4004 0.061970’s 808x 0.641982 286 11985 386 51989 486 201993 Pentium 1001996 P II 2501999 P III 5002000 P 4 1500

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Performance TrendsP

erfo

rman

ce

0.1

1

10

100

1965 1970 1975 1980 1985 1990 1995

Supercomputers

Minicomputers

Mainframes

Microprocessors

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Clock Frequency Growth Rate

• 30% per year

0.1

1

10

100

1,000

19701975

19801985

19901995

20002005

Clo

ck r

ate

(M

Hz)

i4004i8008

i8080

i8086 i80286i80386

Pentium100

R10000

P4

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Transistor Count Growth Rate

Moore’s Law

Transis

tors

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

19701975

19801985

19901995

20002005

i4004i8008

i8080

i8086

i80286i80386

R2000

Pentium R10000

R3000

P4

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General Technology Trends

DEC AlphaHP 9000

750

IBMRS6000

540MIPS M2000MIPS

M/ 120Sun 4260

0

20

40

60

80

100

120

140

160

180

1987 1988 1989 1990 1991 1992

I ntegerFP

• Microprocessor performance increases 50%-100% per year• Transistor count doubles every 3 years• DRAM size quadruples every 3 years• Huge investment per generation is carried by huge

commodity market

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Storage

Divergence between memory capacity and speed more pronounced

Capacity increased by 1000x from 1980-95, speed only 2x Gigabit DRAM by c. 2000, but gap with processor speed much

greater Larger memories are slower, while processors get faster

Need to transfer more data in parallel Need deeper cache hierarchies How to organize caches? Speed Size

ns ~KB

10ns ~MB

100ns ~100MB

10ms ~10GB

>100ms ~TB

Registers

Cache

Main memory

Hard disk

Archive

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Instruction Sets

Software costs growing faster than hardware costs (1970s) Machine language v.s. HLL Support for high-level languages Gap between high level languages

and computer hardware - semantic gap CISC - Complex Instruction Set

Architecture Variety of instructions and addressing modes DEC VAX

HLLCA - High Level Language Computer Architecture

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RISC Architectures

Resolve problems using simpler architecture "The case for the reduced instruction set

computers" Patterson & Ditzel [1980] Stanford MIPS (Hennessy, 1981) Commercial processors: MIPS R2000

(1986), IBM RS6000, SPARC, PowerPC, etc. Good design methodology Efficient pipelining and compiler-assisted

scheduling of pipeline Make the Common Case Fast

favor the frequent case

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cycleii

i TCPInT

Program Execution Time

For all instructionsin the instruction set processor cycle time [s]

cycles per instruction

instruction count

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80x86 Instruction Mix for SPECint92 Programs [PatHen96]

70%

42%

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Instruction Execution

IF ID OF EX ST IF

Mem

PC 1000 1000

A=B+C A+=C

result = op1 OPERATION op2 ADD R1, M(1000)

t

100ns 100ns1ns 1ns

When f = 5MHz (’70s) Tcycle = 200nsTmem = 200ns

When f = 1000MHz (’90s) Tcycle = 1nsTmem = 50ns

3 × 100ns = 300ns2 × 1ns = 2ns 302ns

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Pipeline

timeIF

program

ID

IF

OF

ID

IF

EX

OF

ID

IF

ST

EX

OF

ID

IF

IF

ST

EX

OF

ID#1if( ) …

#2#3#4

#100

CPI = 1

INSTR

#1

#2

#4

#2

#5