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7/29/2019 Course File Final Heena a Digital
1/23
Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Rungta College of Engineering and Technology, Bhilai
Department of Electronics and Telecommunication Engineering
Course File (Theory + Lab)
Name of Subject - Digital Electronic Circuits
Subject Code - 328414(28) [T], 328422(28) [P]
Semester - 4th
Section - A
Discipline - Electronics and Telecommunication
Academic Year - 2012-2013
Name of Professor-
Prof. Heena Parveen,
Lecturer,Department of Electronics and Telecommunication Engineering,
Contact No. & Mail Id-Contact No. 0788-6666666 (O)
7/29/2019 Course File Final Heena a Digital
2/23
Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Department of Electronics and Telecommunication Engineering
1. Programe Education Objectives (PEOs)-I. The Graduates of the programe will have Strong foundation in mathematics, basic
sciences and engineering fundamentals to successfully compete for various entry level
positions or pursue higher studies in Electronics Engineering and/or allied fields.
II. The Graduates of the programe will have contemporary knowledge and lifelong learningskill, familiarity with modern hardware and software tools and practices in Electronics
and related domain.
III. The Graduates of the programe will possess the required skills to perceive successivelythe engineering profession including communication skill, working efficiently in
multidisciplinary teams, understanding of ethical and environmental issues.
2. Programe Outcomes (POs)a) An ability to apply knowledge of Mathematics, Science, and Engineering.b) An ability to design and conduct experiments as well as analyze and interpret data.c) An ability to design a system, component, or process to meet desired needs.d) An ability to function on multidisciplinary teams.e) An ability to identify, formulates, and solves engineering problems.f) An understanding of professional and ethical responsibility.g) An ability to communicate effectively.h) The broad education necessary to understand the impact of engineering solutions in a
global/social context
i) A recognition of the need for and an ability to engage in life-long learningj) Knowledge of contemporary issues.k) An ability to use the techniques, skills and modern engineering tools necessary for
engineering practice.
7/29/2019 Course File Final Heena a Digital
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Course Syllabus
UNIT I: CODES
Binary codes: Introduction & usefulness, Weighted & Non-weighted codes, Sequential codes, self complementing
codes, Cyclic codes, 8-4-2-1 BCD code, Excess-3 code, Gray code: Binary to Gray and Gray to binary code
conversion, Error detecting code, Error correcting code, 7-bit Hamming code, ASCII code, EBCDIC code.
Realization of Boolean Expressions: Reduction of Boolean expressions using laws, theorems and axioms of
Boolean Algebra, Boolean expressions and logic diagram, Converting AND/OR/Invert logic to NAND/NOR logic,
SOP and POS Forms and their Realization.
UNITII: MINIMIZATION TECHNIQUES
Expansion of a Boolean expression to SOP form, Expansion of a Boolean expression to POS form, Two, Three &
Four variable K-Map: Mapping and minimization of SOP and POS expressions. Completely and Incompletely
Specified Functions - Concept of Don't Care Terms, Quine Mc Clusky Method.
UNIT-III: COMBINATIONAL CIRCUITS
Adder & Subtractor: Half adder, Full adder, half Subtractor, Full Subtractor, Parallel Binary adder, Look Ahead
carry adder, Serial adder, BCD adder. Code converter, Parity bit generator/Checker, Comparator. Decoder: 3-line to
8-line decoder, 8-4-2-1 BCD to Decimal decoder, BCD to Seven segment decoder. Encoder: Octal to binary and
Decimal to BCD encoder. Multiplexer: 2-input multiplexer, 4-input multiplexer, 16-input multiplexer. De-
multiplexer:1-line to 4-line & 1-line to 8-line de-multiplexer, Multiplexer as Universal Logic Function Generator,
Programmed Array Logic (PAL), PLA and PLD.
UNITIV: SEQUENTIAL CIRCUITS
Flip-Flops & Timing Circuit: S-R Latch; Gated S-R Latch; D Latch; J-K flip-Flop; T Flip-Flip: Edge Triggered S-
R, D, J-K and T Flips-Flops; Master - Slave Flip-Flops; Direct Preset and Clear Inputs. Shift Registers: PIPO,SIPO, PISO, SISO, Bi-Directional Shift Registers; Universal Shift register. Counter: Asynchronous Counter:
Ripple Counters; Design of asynchronous counters, Effects of propagation delay in Ripple counters, Synchronous
Counters: 4-bit synchronous up counter, 4-bit synchronous down counter, Design of synchronous counters, Ring
counter, Johnson counter, Pulse train generators using counter, Design of Sequence Generators; Digital Clock using
Counters.
UNITV: DIGITAL LOGIC FAMILIES
Introduction : Simple Diode Gating and Transistor Inverter; Basic Concepts of RTL and DTL; TTL: Open
collector gates, TTL subfamilies, IIL, ECL; MOS Logic: CMOS Logic, Dynamic MOS Logic, Interfacing: TTL to
ECL, ECL to TTL, TTL to CMOS, CMOS to TTL, Comparison among various logic families, Manufacturers
specification.
7/29/2019 Course File Final Heena a Digital
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Textbook Recommended:
1. Digital Logic and Computer Design M. Morris Mano.
2. Fundamentals of Digital Circuits A. Anand Kumar, PHI
Reference Book Recommended:
1. Digital Fundamentals: Floyd & Jain, Pearson Education.2. Digital Circuits & Design- Salivahanan, Vikas Publication.
Digital Electronic Circuits (Lab) - 328422(28)
List of Experiments to be performed
1. To Verify The Properties of NOR & NAND Gates As Universal Building Block. 2. Realization of Boolean Expression Using NAND Or NOR Gates.3. To Construct X- OR Gate Using Only NAND Or NOR Gates Only. 4. To Construct A Half Adder Circuit. And Logic Gates And Verify its Truth table. 5. To Construct A Full Adder Circuit. And Verify its truth table (Using Two X-OR And 3 NAND Gates). 6. To Construct A Half Subtractor Circuit. By Using Basic Gates And Verify its truth table. 7. To Construct a Full Subtractor Circuit by Using Basic Gates and Verify its truth table. 8. To Construct A Circuit of 4 -Bit Parity Checker & Verify its truth table.9. To Design a Comparator Circuit & Verify its truth table.10. To Construct A RS Flip Flop Using Basic & Universal Gates (NOT,NOR & NAND). 11. To Verify The Operation of A Clocked S-R Flip Flop And J. K. Flip Flop. 12. To Construct a T & D Flip Flop Using J K.Flip Flop and Verify Its Operations & truth table. 13. To Verify The Operation of A Synchronous Decade Counter.
7/29/2019 Course File Final Heena a Digital
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Time Table-
Class Schedule (3L+1T+4P)-
Days/Periods 1 (9:40
10:30)
2 (10:30
11:20)
3 (11:40
12:30)
4 (12:30
01:20)
5 (02:00
02:50)
6 (02:50
03:40)
7 (03:40
04:30)
Monday
Tuesday P
Wednesday L P T
Thursday T P
Friday L P
Saturday L
L- Lecture T- Tutorial P- Practical
i) Course Educational Objective-The Course Educational Objectives are:(1) The students of the programme will have contemporary knowledge about Digital Electronics and lifelong
learning skills familiarity with modern hardware and software tools and practices used in Electronics and
Telecommunication related domain.
(2) The students of the programme will get knowledge about Digital Electronics and the required interfacingskills in embedded systems and working efficiently in multidisciplinary teams for its applications in various
fields.
ii) Once the student has successfully complete this course, he/she will be able to answer the followingquestions or perform following activities:
The Course Outcomes are:
(a) An ability to apply the basic knowledge of science and Digital Electronics in Electronics andTelecommunication Engineering.
(b) An ability to design and conduct experiments, as well as to analyze and interpret data with the helpof Digital Electronics.
(c) An ability to design a system, component or process to meet desired needs within realisticconstraints such as economic, environmental, social, political, ethical, health and safety,
manufacturability and sustainability of Telecommunication Engineering.
(d) An ability to function on multidisciplinary teams.(k) An ability to use the techniques, skills and modern engineering tools necessary for engineeringpractice.
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
iii) Mapping of Course Objectives and Course Outcomes:Course Educational Objectives Course Outcomes
a b c d kI X X
II X X X X
iv) Mapping of Course Contents with Course Education Objective (CEOs) and Course Outcomes(COs):
Unit No. CEOs Course Outcomes
I II a b c d k
Unit 1 X X X X X
Unit 2 X X
Unit 3 X X X X X X X
Unit 4 X X X X X X
Unit 5 X X X X
v) Adopted Grading System:Modes Percentage
Covered
Date of
Performance
Mid Term Exam 40% 18.02.13 20.02.13
Pre-Semester Exam 40% 12.04.13 18.04.13
Assignment 10%
Teacher Assessment 10%
Note-All the examinations are compulsory. The homework is scheduled to be due on the specified dates. No
homework will be accepted after the due date.
7/29/2019 Course File Final Heena a Digital
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
vi) Instructional Schedule (Lecture):Instructional Schedule (Lecture)
Subject- Digital Electronic Circuits
Code- 328414 (28)
Semester 4th
Discipline- Electronics & TelecommunicationS. No. Lecture No. Date ofDelivery
Topic to be Covered Remarks if any
UNIT-1 : CODES
1 1 02/01/13 Introduction & usefulness, Types of codes
2 2 04/01/13 Types of codes
3 3 05/01/13 Gray code : Binary to Gray & Gray to Binary
code conversion
4 4 09/01/13 Error Detecting Code, error correcting code (7-bit
hamming code)
5 5 11/01/13 Realization of expressions, Boolean expressions &
Logic diagram
6 6 12/01/13 Converting AND/OR/INVERT logic to
NAND/NOR logic
Topic related to Lab
Experiment No. 1, 2 and3
7 7 16/01/13 SOP & POS forms and their realization Assignment 1 dueUNIT-2 : MINIMIZATION TECHNIQUES
8 8 18/01/13 Expansion of a Boolean expression to SOP form
& POS form
9 9 19/01/13 K-map
10 10 23/01/13 K-map
11 11 25/01/13 Concept of dont care terms
12 12 30/01/13 Quine Mc-Clusky method
13 15 01/02/13 Quine Mc-Clusky method Assignment 2 dueUNIT-3 : COMBINATIONAL CIRCUITS
14 14 02/02/13 Adder & Subtractor Topic related to Lab
Experiment No. 4, 5, 6and 7
15 15 06/02/13 Adder & Subtractor, Parallel binary adder
16 16 08/02/13 Look ahead carry adder
17 17 09/02/13 Serial adder
18 18 13/02/13 BCD adder
19 19 15/02/13 Code converter
20 20 16/02/13 Parity bit generator/checker, Comparator Topic related to Lab
Experiment No. 8 and 9
21 21 20/02/13 Decoder & Encoder
22 22 22/02/13 Multiplexer
23 23 23/02/13 De-multiplexer
24 24 27/02/13 PLD
25 25 01/03/13 PLD Assignment 3 dueUNIT-4 : SEQUENTIAL CIRCUITS
26 26 02/03/13 Latch
27 27 06/03/13 Flip-flop types
28 28 08/03/13 Flip-flop types
29 29 09/03/13 Flip-flop types Topic related to Lab
Experiment No. 10, 11
and 12
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Instructional Schedule (Lecture)
Subject- Digital Electronic Circuits
Code- 328414 (28)
Semester 4th
Discipline- Electronics & Telecommunication
S. No. Lecture No. Date ofDelivery Topic to be Covered Remarks if any
30 30 13/03/13 Shift registers & its types
31 31 15/03/13 Types of shift registers
32 32 16/03/13 Asynchronous counter & its design
33 33 20/03/13 Asynchronous counter & its design
34 34 22/03/13 Synchronous counter & its design Topic related to Lab
Experiment No. 13
35 35 23/03/13 Ring & Johnson counter
36 36 29/03/13 Design of sequence generators Assignment 4 due
UNIT-5 : DIGITAL LOGIC FAMILIES
37 37 30/03/13 Introduction, Fabrication & packaging process of
digital ICs.Topic Beyond Syllabus
38 38 03/04/13 RTL,DTL39 39 05/04/13 TTL, TTL subfamilies
40 40 06/04/13 IIL, ECL
41 41 10/04/13 MOS Logic, Interfacing Assignment 5 due
vii) Instructional Schedule (Tutorial):Instructional Schedule (Tutorial)
Subject- Digital Electronic Circuits
Code- 328414 (28)
Semester 4th
Discipline- Electronics & Telecommunication
S. No. Date ofDelivery
(Batch 1)
Date ofDelivery
(Batch 2)
Topic to be Covered Remarks if any
1 02/01/13 03/01/13 Numerical + Doubt Clearing
2 09/01/13 10/01/13 Numerical + Doubt Clearing
3 16/01/13 17/01/13 Solving Previous Year Question Papers
4 23/01/13 24/01/13 Numerical + Doubt Clearing
5 30/01/13 31/01/13 Numerical + Doubt Clearing
6 06/02/13 07/02/13 Solving Previous Year Question Papers
7 13/02/13 14/02/13 Numerical + Doubt Clearing
8 20/02/13 21/02/13 Numerical + Doubt Clearing
9 27/02/13 28/02/13 Solving Previous Year Question Papers
10 06/03/13 07/03/13 Numerical + Doubt Clearing
11 13/03/13 14/03/13 Numerical + Doubt Clearing12 20/03/13 21/03/13 Solving Previous Year Question Papers
13 03/04/13 28/03/13 Numerical + Doubt Clearing
14 10/04/13 04/04/13 Solving Previous Year Question Papers
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Asignment addressing POs, and Blooms Taxonomy Level:
S. No Assignment
No.
Remarks PO addressed Blooms Taxonomy Level
1. 1 Questions related to codes,
Boolean Algebra and Booleanexpression realization
a, b, k Cognitive Domain- Leve-
1, Level-2,Level-3(Remember,
Understanding,
Application)
2. 2 Questions related to Minimization
Techniques
a Cognitive Domain-Level-
2,Level-3 (Understanding,
Application)
3. 3 Questions related to designing of
combinational circuits
a, b, c, d, k Cognitive Domain- Level-
1, Level-2,Level-5
(Remember,
Understanding, Creativity)
4. 4 Questions related to flip flop and
counters
a, b, c, k Cognitive Domain- Level-
1, Level-2,Level-5
(Remember,Understanding, Creativity)
5. 5 Questions related to functioning of
different ICs and comparison
among them
a, d, k Cognitive Domain- Level-
1, Level-2,Level-4, Level-
5 (Remember,
Understanding, Analysis,
Creativity)
7/29/2019 Course File Final Heena a Digital
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
viii)Instructional Schedule (Laboratory):INSTRUCTIONAL SCHEDULE (PRACTICAL)
Subject- Digital Electronic Circuits Lab
Code- 328422 (28)
Semester 4th
Discipline- Electronics & TelecommunicationS. No. Experiment
No.
Date of Experiment Experiment to be Performed Remarks if any
Batch I Batch II
1 1 02/01/13 03/01/13
To Verify The Properties of NOR & NAND Gates
As Universal Building Block.
Related to Unit-1
2 2 05/01/13 08/01/13
Realization of Boolean Expression Using NAND Or
NOR Gates.
Related to Unit-1
3 3 09/01/13 10/01/13
To Construct X- OR Gate Using Only NAND Or
NOR Gates Only.
Related to Unit-1
4 4 12/01/13 15/01/13
To Construct A Half Adder Circuit. And Logic Gates
And Verify its Truth table.
Related to Unit-3
5 5 16/01/13 17/01/13
To Construct A Full Adder Circuit. And Verify its
truth table (Using Two X-OR And 3 NAND Gates).
Related to Unit-3
6 6 19/01/13 22/01/13
To Construct A Half Subtractor Circuit. By Using
Basic Gates And Verify its truth table.
Related to Unit-3
7 7 23/01/13 24/01/13
To Construct a Full Subtractor Circuit by Using
Basic Gates and Verify its truth table.
Related to Unit-3
8 8 29/01/13 30/01/13
To Construct A Circuit of 4 -Bit Parity Checker &
Verify its truth table.
Related to Unit-3
9 9 31/01/13 02/02/13
To Design a Comparator Circuit & Verify its truth
table.
Related to Unit-3
10 10 05/02/13 06/02/13
To Construct A RS Flip Flop Using Basic &
Universal Gates (NOT, NOR & NAND).
Related to Unit-4
11 11 07/02/13 09/02/13
To Verify The Operation of A Clocked S-R Flip
Flop And J. K. Flip Flop.
Related to Unit-4
12 12 12/02/13 13/02/13
To Construct a T & D Flip Flop Using J K Flip Flop
and Verify Its Operations & truth table.
Related to Unit-4
13 13 14/02/13 16/02/13
To Verify The Operation of A Synchronous Decade
Counter.
Related to Unit-4
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
ix) Mapping of Course Educational Objectives and Course Outcomes for Laboratory Experiments:
Experiment
No.
Experiment to be performed CEOs
Covered
COs Achieved
I II a b c d k
1 To Verify The Properties of NOR & NANDGates As Universal Building Block. X X X X X X
2 Realization of Boolean Expression Using
NAND Or NOR Gates.
X X X X X
3 To Construct X- OR Gate Using Only NAND
Or NOR Gates Only.
X X X X
4 To Construct A Half Adder Circuit. And Logic
Gates And Verify its Truth table.
X X X X
5 To Construct A Full Adder Circuit. And
Verify its truth table (Using Two X-OR And 3
NAND Gates).
X X X X
6 To Construct A Half Subtractor Circuit. By
Using Basic Gates And Verify its truth table.
X X X X
7 To Construct a Full Subtractor Circuit by
Using Basic Gates and Verify its truth table.
X X X X
8 To Construct A Circuit of 4 -Bit Parity
Checker & Verify its truth table.X X X
9 To Design a Comparator Circuit & Verify its
truth table.X X X X X X X
10 To Construct A RS Flip Flop Using Basic &Universal Gates (NOT, NOR & NAND).
X X X X X
11 To Verify The Operation of A Clocked S-R
Flip Flop And J. K. Flip Flop.X X X
12 To Construct a T & D Flip Flop Using J K Flip
Flop and Verify Its Operations & truth table.
X X X X
13 To Verify The Operation of A Synchronous
Decade Counter.
X X X X X
7/29/2019 Course File Final Heena a Digital
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
x) Teaching plan (Unit Wise):
UNIT PLAN
UNIT : 1
UNIT CONTENTS:
Binary codes: Introduction & usefulness, Weighted & Non-weighted codes, Sequential codes, self complementing
codes, Cyclic codes, 8-4-2-1 BCD code, Excess-3 code, Gray code: Binary to Gray and Gray to binary code
conversion, Error detecting code, Error correcting code, 7-bit Hamming code, ASCII code, EBCDIC code.
Realization of Boolean Expressions: Reduction of Boolean expressions using laws, theorems and axioms of
Boolean Algebra, Boolean expressions and logic diagram, Converting AND/OR/Invert logic to NAND/NOR logic,
SOP and POS Forms and their Realization.
Unit Objectives:
Broad Objectives of the unit are:
1. Gaining Knowledge about the Codes2. Code Conversion3. Boolean Algebra & realization of Boolean Expression4. SOP & POS form
By fulfilling the objective the student will satisfy POs (a), (b) and (k) and first three levels of Blooms Taxonomy
Cognitive Domain i.e. Remember, Understand and Application.
Once the student has completed this unit he/she will be able to answer following questions/perform the
following activities:
1. Different types of codes used in digital circuits & their conversions.2. Difference between Ordinary Algebra & Boolean Algebra.3. Employ Boolean algebra to describe the function of logic circuits.4. Circuits from Boolean Expressions.
With the above POs (a), (b) and (k) is expected to be achieved.
Methodology:
This unit will be taught by providing basic the information regarding digital electronics which includes its
introduction, various binary codes and Boolean algebra.
Related laboratory experiments as per the curriculum
1. To Verify The Properties of NOR & NAND Gates As Universal Building Block. 2. Realization of Boolean Expression Using NAND Or NOR Gates. 3. To Construct X- OR Gate Using Only NAND Or NOR Gates Only.
Assignment 1:
1. Simplify the Boolean Expressions and draw the logic diagram:xyz + xyz + xyz + xyz + xyz+ xyz + xyz
2. Explain with examples how hamming code is useful for detecting and correcting errors in digitalcommunication system.
3. Explain and state principle of duality.4. Implement the following function by using only NOR gate.
F = a(b + cd)+ bc
5. Using Boolean Algebra, show thatAB+ABD+ABD+(ACD)+ABC=(A+BC)+CD
The above assignment is designed to address PO (a), (b) and (k) and level (1), (2) and (3) of Blooms Taxonomy of CognitiveDomain
7/29/2019 Course File Final Heena a Digital
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
UNIT PLAN
UNIT : 2
UNIT CONTENTS:
Expansion of a Boolean expression to SOP form, Expansion of a Boolean expression to POS form, Two, Three &
Four variable K-Map: Mapping and minimization of SOP and POS expressions. Completely and IncompletelySpecified Functions - Concept of Don't Care Terms, Quine Mc Clusky Method.
Unit Objectives:
Broad Objectives of the unit are:
1. Expansion of Boolean Expression to SOP & POS form2. Minimization Using K-Maps & Quine Mc Clusky Method3. Incompletely Specified Functions
By fulfilling the objective the student will satisfy PO (a) and two levels of Blooms Taxonomy Cognitive Domain i.e.
Understand and Application.
Once the student has completed this unit he/she will be able to answer following questions/perform the
following activities:
1. Understand the minimization techniques of Boolean Expression2. Solve questions on K-Map and Quine Mc-Clusky method
With the above PO (a) is expected to be achieved
Methodology:This unit will be covered by explaining how Boolean functions can be simplified in order to achieve economical
gate implementations.
Related laboratory experiments as per the curriculum
No laboratory experiments.
Assignment 2:
1. Minimize the logic function by using K-map.Y= M (0,1,3,5,6,7,10,14,15)
3. Why is it essential to use minimization techniques before designing any digital circuit? Differentiatebetween expansion in SOP form and POS form.
4. Reduce the following function using K-map.F=m(1,5,6,12,13,14)+d(2,4)
5. Using the Quine Mc-Clusky method, solve the following functions.F(w,x,y,z)=m(0,1,5,7,8,10,14,15)
F(A,B,C,D)=m(0,2,3,6,7,8,9,10,13)
6. (a) Differentiate between combinational and sequential circuits.(b) Simplify the expression.
F=xy+xy+xy
The above assignment is designed to address PO (a) and level (2) and (3) of Blooms Taxonomy of Cognitive Domain.
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
UNIT PLAN
UNIT : 3
UNIT CONTENTS:
Adder & Subtractor: Half adder, Full adder, half Subtractor, Full Subtractor, Parallel Binary adder, Look Ahead
carry adder, Serial adder, BCD adder. Code converter, Parity bit generator/Checker, Comparator. Decoder: 3-line to8-line decoder, 8-4-2-1 BCD to Decimal decoder, BCD to Seven segment decoder. Encoder: Octal to binary and
Decimal to BCD encoder. Multiplexer: 2-input multiplexer, 4-input multiplexer, 16-input multiplexer De-
multiplexer:1-line to 4-line & 1-line to 8-line de-multiplexer, Multiplexer as Universal Logic Function Generator,
Programmed Array Logic (PAL), PLA and PLD.
Unit Objectives:
Broad Objectives of the unit are:
1. Adder & Subtractor2. Parity bit generator/Checker3. Comparator4. Decoder & Encoder5. Multiplexer & De-multiplexer6. Knowledge of Programmable Logic Devices
By fulfilling the objective the student will satisfy POs (a), (b), (c), (d) and (k) and three levels of Blooms Taxonomy
Cognitive Domain i.e. Remember, Understand and Creativity.
Once the student has completed this unit he/she will be able to answer following questions/perform the
following activities:
1. Designing combinational logic circuits.2. Implementation of combinational circuits using decoders, Multiplexers and PLA.3. Understand the function of PLDs.
With the above POs (a), (b), (c), (d) and (k) is expected to be achieved
Methodology:
This unit will utilize the concept built in previous units and formulate various systematic designs and procedural
analysis of combinational circuits. PLDs and their usefulness in the design of complex combinational circuits willalso be discussed.
Related laboratory experiments as per the curriculum
1. To construct and verify Half Adder and Full Adder Circuit with its truth table.2. To construct and verify Half Subtractor and Full Subtractor Circuit with its truth table.3. To Construct A Circuit of 4 -Bit Parity Checker & Verify its truth table.4. To Design a Comparator Circuit & Verify its truth table.
Assignment 3:
1. Design a 4-bit BCD adder.2. Design a 4-bit comparator circuit.3. Construct a 4x16 decoder using 3x8decoder.4. Describer operation of PLA.5. Explain the operation of 4-bit carry look ahead adder circuit. What are its merits?The above assignment is designed to address PO (a), (b), (c), (d) and (k) and level (1), (2) and (5) of Blooms Taxonomyof Cognitive Domain.
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
UNIT PLAN
UNIT : 4
UNIT CONTENTS:
Flip-Flops & Timing Circuit: S-R Latch; Gated S-R Latch; D Latch; J-K flip-Flop; T Flip-Flip: Edge Triggered S-R, D, J-K and T Flips-Flops; Master - Slave Flip-Flops; Direct Preset and Clear Inputs. Shift Registers: PIPO,
SIPO, PISO, SISO, Bi-Directional Shift Registers; Universal Shift register. Counter: Asynchronous Counter:
Ripple Counters; Design of asynchronous counters, Effects of propagation delay in Ripple counters, Synchronous
Counters: 4-bit synchronous up counter, 4-bit synchronous down counter, Design of synchronous counters, Ring
counter, Johnson counter, Pulse train generators using counter, Design of Sequence Generators; Digital Clock using
Counters.
Unit Objectives:
Broad Objectives of the unit are:
1. Latches
2. Clock Signals and Clocked Flip-Flops
3. Data transfer using shift registers
4. Counters
By fulfilling the objective the student will satisfy POs (a), (b), (c) and (k) and three levels of Blooms Taxonomy
Cognitive Domain i.e. Remember, Understand and Creativity.
Once the student has completed this unit he/she will be able to answer following questions/perform the
following activities:
1. Understand and construct various flip flops.2. Transfer binary information.3. Designing of counters.
With the above POs (a), (b), (c) and (k) is expected to be achieved
Methodology:
This unit proceeds with explaining latches, various types of flip flops and the way they are triggered. Different shift
registers, counters and their designing will also be covered in this unit.
Related laboratory experiments as per the curriculum
1. To Construct A RS Flip Flop Using Basic & Universal Gates (NOT, NOR & NAND).2. To Verify The Operation of A Clocked S-R Flip Flop And J. K. Flip Flop.3. To Construct a T & D Flip Flop Using J K Flip Flop and Verify Its Operations & truth table.4. To Verify The Operation of A Synchronous Decade Counter.
Assignment 4:
1. Design mod-10 asynchronous counter.2. Design mod-6 synchronous counter.3. What is race around condition for J-K flip flop? How it can be avoided in master slave flip flop?4. Draw & describe the working of PISO shift register. Explain how a number can be shifted in and out from
such registers.
5. Do conversion of S-R flip flop to J-K flip flop.The above assignment is designed to address PO (a), (b), (c) and (k) and level (1), (2) and (5) of Blooms Taxonomy ofCognitive Domain.
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
UNIT PLAN
UNIT : 5
UNIT CONTENTS:
Introduction : Simple Diode Gating and Transistor Inverter; Basic Concepts of RTL and DTL; TTL: Opencollector gates, TTL subfamilies, IIL, ECL; MOS Logic: CMOS Logic, Dynamic MOS Logic, Interfacing: TTL to
ECL, ECL to TTL, TTL to CMOS, CMOS to TTL, Comparison among various logic families, Manufacturers
specification.
Unit Objectives:
Broad Objectives of the unit are:
1. Knowledge of various Logic Families
2. Interfacing Logic Families
3. Comparison among various logic families characteristics
By fulfilling the objective the student will satisfy POs (a), (d) and (k) and four levels of Blooms Taxonomy
Cognitive Domain i.e. Remember, Understand, Analysis and Creativity..
Once the student has completed this unit he/she will be able to answer following questions/perform the
following activities:
1. Analyzing various logic families in digital circuits, and evaluating their performance by measuringpropagation delay, noise margins, and fan-out.
With the above POs (a), (d) and (k) is expected to be achieved
Methodology:
This unit will be taught by presenting the basic electronic circuits in each IC digital logic family and analyzing their
electrical operation.
Related laboratory experiments as per the curriculumNo laboratory experiments.
Reading Material to be recommended/required beyond syllabus to cover latest technological advancements
related to the topic
Fabrication & packaging process of digital ICs.
Assignment 5:
1. Draw the circuit diagram of two input NAND gate using TTL logic & explain.2. Design inverter by using CMOS logic and explain.3. Explain characteristics of digital ICs.4. Define the following parameters.
a) Noise marginb) Propagation delayc) Power dissipationd) Speed power producte) Threshold voltagef) Fan in & Fan out
5. Give comparison among various logic families.The above assignment is designed to address PO (a), (d) and (k) and level (1), (2), (4) and (5) of Blooms Taxonomy ofCognitive Domain.
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Department of Electronics and Telecommunication Engineering,
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CEO #
addressed
Related PEO
# the CEO
addresses
Unit Title Knowledge Skill Attitude &
Values
1, 2 1, 2 Codes X X
1 1 Minimization
Techniques
X
1, 2 1, 2 CombinationalCircuits
X X
1, 2 1, 2 Sequential
Circuits
X X
1 1 Digital Logic
Families
X
CO #
addressed
Related PO #
the CO
addresses
Unit Title Cognitive Domain
(level #)
Psychomotor
Domain (Skills)
level #
Affective Domain
(Level #)
a, b, k a, b, k Codes 1, 2, 3A a Minimization
Techniques
2, 3
a, b, c, d, k a, b, c, d, k Combinational
Circuits
1, 2, 5
a, b, c, k a, b, c, k Sequential
Circuits
1, 2, 5
a, d, k a, d, k Digital Logic
Families
1, 2, 4, 5
xi) Mapping of Mid-term and Final Examination with PEOs, POs, CEOs and COs:Examination CEOs Course Outcomes
I II a b c d k
Mid Term Examination X X X X X
Final Examination X X X X X X
Examination PEOs Programme Outcomes
I II a b c d k
Mid Term Examination X X X X X
Final Examination X X X X X X
The one set of mid-term examination paper is included in Annexure 1(a) and its model solution is included inAnnexure 1(b).
The one set of final-examination paper is included in Annexure 2(a) and its model solution is included in Annexure
2(b).
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
xii)Mapping of Assignments with CEOs and COs:A series of homework questions are provided as the course proceeds as mentioned in the unit plan. The mapping
with CEOs and COs of each homework collectively is given below.
Assignment No. CEOs COs
I II a b c d k
Assignment 1 X X X X X
Assignment 2 X X
Assignment 3 X X X X X X X
Assignment 4 X X X X X X
Assignment 5 X X X X
xiii)University Question Papers:A complete set of 3 year question papers of university exams is provided in Annexure 3.
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
xiv)Mapping of Course contents with PEOs and POs (Theory):Mapping Instructional Schedule (Lecture) with PEOs and Pos
Subject- Digital Electronic Circuits
Code- 328414 (28)
Semester 4th
Discipline- Electronics & Telecommunication
SNo. Syllabus Covered Blooms Level PEOs POs
Re Un Ap An Cr Ev I II III a b c D e f g h i j k
UNIT-1 : CODES
1 Introduction & usefulness, Types ofcodes
X X X X X X
2 Types of codes X X X X X X
3 Gray code : Binary to Gray & Gray to
Binary code conversion
X X X X X X
4 Error Detecting Code, error correcting
code (7-bit hamming code)
X X X X X X X
5 Realization of expression, Booleanexpressions & Logic diagram
X X X X X X X
6 Converting AND/OR/INVERT logic to
NAND/NOR logic
X X X X
7 SOP & POS forms and their realization X X
UNIT-2 : MINIMIZATIONTECHNIQUES
8 Expansion of a Boolean expression to
SOP form & POS form
X X X X X
9 K-map X X X X X
10 K-map X X X X X
11 Concept of dont care terms X X X X X
12 Quine Mc-Clusky method X X X X X
13 Quine Mc-Clusky method X X X X X
UNIT-3 : COMBINATIONAL
CIRCUITS
14 Adder & Subtractor X X X X X X X X X X
15 Adder & Subtractor, Parallel binary adder X X X X X X X X X X
16 Look ahead carry adder X X X X X X X X
17 Serial adder X X X X X X X X
18 BCD adder X X X X X X X X
19 Code converter X X X X X20 Parity bit generator/checker, Comparator X X X X X X X X X X
21 Decoder & Encoder X X X X X X X X X X
22 Multiplexer X X X X X X X X X
23 De-multiplexer X X X X X X X X X
24 PLD X X X X
25 PLD X X X X
UNIT-4 : SEQUENTIAL CIRCUITS
26 Latch X X X X X
27 Flip-flop types X X X X X X X X
28 Flip-flop types X X X X X X X X
29 Flip-flop types X X X X X X X X
30 Shift registers & its types X X X X X X X X
31 Types of shift registers X X X X X X X X
32 Asynchronous counter & its design X X X X X X X
33 Asynchronous counter & its design X X X X X X X
34 Synchronous counter & its design X X X X X X X X X35 Ring & Johnson counter X X X X X X X
36 Design of sequence generators X X X X X
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Mapping Instructional Schedule (Lecture) with PEOs and PosSubject- Digital Electronic Circuits
Code- 328414 (28)
Semester 4th
Discipline- Electronics & TelecommunicationS No. Syllabus Covered Blooms Level PEOs POs
Re Un Ap An Cr Ev I II III a b c D e f g h i j k
UNIT-5 : DIGITAL LOGICFAMILIES
37 Introduction, Fabrication &
packaging process of digital
ICs.
X X X
38 RTL,DTL X X X X X X
39 TTL, TTL subfamilies X X X X X X
40 IIL, ECL X X X X
41 MOS logic, Interfacing X X X X X X
Re- Remember Un- Understanding Ap- Application An- Analysis Cr- Creativity Ev- Evaluation
Mapping Instructional Schedule (Tutorial) with PEOs and PosSubject- Digital Electronic Circuits
Code- 328414 (28)
Semester 4th
Discipline- Electronics & TelecommunicationS No. Syllabus Covered Blooms Level PEOs POs
Re Un Ap An Cr Ev I II III a b c D e f G h i j k
1 Solving Previous Year Question
Papers (Apr. May. 2009)
X X X X X X X X X X X
2 Solving Previous Year Question
Papers (Apr. May 2010)
X X X X X X X X X X X
3 Solving Previous Year Question
Papers (Nov. Dec 2010)
X X X X X X X X X X
4 Solving Previous Year Question
Papers (Apr. May. 2011)
X X X X X X X X X X
5 Solving Previous Year QuestionPapers (Nov. Dec. 2011) X X X X X X X X X X X
Re- Remember Un- Understanding Ap- Application An- Analysis Cr- Creativity Ev- Evaluation
Mapping Assignment with PEOs and PosSubject- Digital Electronic Circuits
Code- 328414 (28)
Semester 4th
Discipline- Electronics & TelecommunicationS No. Syllabus Covered Blooms Level PEOs POs
Re Un Ap An Cr Ev I II III a b c D e f G h i j k
1 Assignment 1 X X X X X X X X
2 Assignment 2 X X X X
3 Assignment 3 X X X X X X X X X X
4 Assignment 4 X X X X X X X X X5 Assignment 5 X X X X X X X X
Re- Remember Un- Understanding Ap- Application An- Analysis Cr- Creativity Ev- Evaluation
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Department of Electronics and Telecommunication Engineering,
RCET, Bhilai
Mapping Instructional Schedule (Laboratory) with PEOs and POsSubject- Digital Electronic Circuits Lab
Code- 328422 (28)
Semester 4th
Discipline- Electronics & TelecommunicationS No. Name of Experiment Blooms Level PEOs POs
Re Un Ap An Cr Ev I II III a b c D e f G h i j k
1 To Verify The Properties of NOR &NAND Gates As Universal Building
Block.
X X X X X X X X
2 Realization of Boolean Expression UsingNAND Or NOR Gates.
X X X X X X X
3 To Construct X- OR Gate Using Only
NAND Or NOR Gates Only.
X X X X X X
4 To Construct A Half Adder Circuit. And
Logic Gates And Verify its Truth table.
X X X X X X X
5 To Construct A Full Adder Circuit. And
Verify its truth table (Using Two X-OR
And 3 NAND Gates).
X X X X X X X
6 To Construct A Half Subtractor Circuit.
By Using Basic Gates And Verify its
truth table.
X X X X X X X
7 To Construct a Full Subtractor Circuit byUsing Basic Gates and Verify its truth
table.
X X X X X X X
8 To Construct A Circuit of 4 -Bit ParityChecker & Verify its truth table.
X X X X X
9 To Design a Comparator Circuit &Verify its truth table.
X X X X X X X X X X
10 To Construct A RS Flip Flop Using Basic
& Universal Gates (NOT,NOR &NAND).
X X X X X X X
11 To Verify The Operation of A ClockedS-R Flip Flop And J. K. Flip Flop.
X X X X X
12 To Construct a T & D Flip Flop Using JK Flip Flop and Verify Its Operations &
truth table.
X X X X X X X X
13 To Verify The Operation of ASynchronous Decade Counter.
X X X X X X X
Re- Remember Un- Understanding Ap- Application An- Analysis Cr- Creativity Ev- Evaluation
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xv) Rubrics for Assessment of Course Outcomes:The course outcomes will be assessed based on the following rubrics as course proceeds as per unit plan
and instructional schedule. Course feedback will be taken at regular intervals during the semester.
Levels Exemplary Competent Developing Novice Points
Able to
understand theconcept and
importance of
Number System
and Codes in
Digital Logic
Design
Student knows the
significance ofvarious codes andnumber system.
Also, he/ she caneasily employ
Boolean algebra to
describe thefunction of logic
circuits.
Students have
knowledge aboutvarious gates andimplementation ofswitching function
using basic anduniversal gates.
Students are
capable ofrealizing theBoolean
expression byusing various
postulates and
axioms of Booleanalgebra.
Students can
distinguish betweendifferent codes andnumber system.
Also, he/she is ableto answer questions
based on that.
Expansion
methods and
different
minimization
techniques of
BooleanExpression
Students know themapping and
minimization ofSOP and POS
expression; and theconcept of
completely andincompletely
specified functions.
Students canminimize the
Booleanexpression by any
of the giventechniques.
Students are ableto simplify the
given expressionby at least one of
the methods.
Students can identifySOP and POS
expression; and canat least expand it into
minterms andmaxterms.
Able to study
different
combinational
circuits and its
designing using
logic gates
Studentssuccessfully
comprehend the
knowledge ofCombinational
logic circuits andalso programmable
logic devices.
Studentsunderstand and can
design different
combinationalcircuits.
Students knowsome of the
combinational
circuits and areable to design to
them.
He/ she can at leastdifferentiate between
combinational and
sequential circuits.
Able to study
different
Sequential
circuits and itsdesigning using
logic gates.
Studentssuccessfully
comprehend theknowledge of
Sequential logiccircuits
Studentsunderstand and can
design differentflip flops and
counters.
Students candescribe the
functioning ofdifferent flip flops,
counters andregisters.
Students can identifydifferent types of flip
flops and counters
Able to gain
knowledge of
Digital logic
families and its
comparison
considering
various factors
Studentsunderstand the
need of ICs andhave complete
knowledge abouttheir families.
Students know thefunctioning and
characteristics ofdigital logic
families. Alsohe/she is able to
interface differentlogic families.
Students candifferentiate
among differentlogic families
depending upontheir important
parameters orproperties.
Students are able tounderstand the
electrical operationof some of the digital
logic familiesbecause of the prior
knowledge of basic
electronics.
Overall
Performance
Exemplary Competent Developing Novice Total
Point Required 31-40 21-30 11-20 1-10
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xvi)Rubrics for Assessment at the end of Course:Level Exemplary Competent Developing Novice
Mid-Term Exam
Final Exam
Assignment
Teacher
Assessment
The above assessment is carried out on a class of 60 students. 75% students are expected to clear the university
examination in this subject after the declaration of results.
Prepared By-
Prof. Heena Parveen,
Lecturer,
Department of Electronics and Telecommunication Engineering,
Rungta College of Engineering and Technology, Bhilai.