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Counters design in Cadence

By

Gonugunta saiphani kumar

Roll num:1421908

M.tech VLSI 2nd sem

NIT jalandhar

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Counters

The major work of counter is counting of

time / frequency

electronic pulse

Applications: Alarm clock

Set an AC/TV timer

Set a timer for taking picture

Flashing indicator lights of your vehicle

Counting the time allotted for a "process" 

The finite state  machines

In various ADC

Communication (serial to parallel ,parallel to serial)

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Real time applications

Shipment quantities are counted to

control the conveyor line flow.

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Incoming and outgoing cars are counted

to switch the FULL and VACANT signs.

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Rotary encoder signals are counted to

control a valve aperture.

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Teamed up with a rotary encoder, the counter is used to

control the cutting length of pipes.

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Labeled cans alone are counted up.

Rejected cans are not counted.

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Medicine tablets are packed in specified

quantities.

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Printed matter is counted to package a

specified number of copies.

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Extra leader sheet that is now wound is counted by a rotary

encoder and a color detecting sensor.

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Incoming and outgoing parts are counted

to keep parts feeders well-stocked.

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Types of counters

Asynchronous/Ripple counters: counter that is formed from n cascaded flip-flops. The clock input to each of the individual flip-flops, with the exception of the first, is taken from the output of the preceding one.

Ex: Binary up counter, Binary down counter, Binary up/down counter, Mod-N counter, BCD counter(Mod-10)

synchronous counters: A counter consisting of an interconnected series of flip-flops in which all the flip-flop outputs change state at the same instant, normally on application of a pulse at the counter input

Ex: Binary up counter, Binary down counter, Binary up/down counter, Mod-N counter, BCD counter(Mod-10), Ring counter, Johnson counter, Binary presettable counter

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Asynchronous Johnson counter

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Positive edge triggered D-FF

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Cadence schematic diagram

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Cadence simulation

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Power consumption

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Properties of Johnson counter Simulator--Cadence

Technology--180nm

W/L of pmos = 600nm/180nm

W/L of nmos = 240nm/180nm

No. of transistors = 104

Clock range 1.8v - 0v

Clock ON time =10nnm

Clock time period = 25nm

Rise & fall time = 1fs

VDD = 1.8V

GND = 0v

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Results of Johnson counter

Avg.Power consumption = 6.10μw

High to low delay (at every stage) = 219.5ps

Low to high delay(at every stage) = 136ps

Max. frequency of operation = 7.35 Ghz

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Asynchronous up counter

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Negative edge triggered j-k FF

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Cadence schematic

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Cadence simulation

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Delay at each stage

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Power consumption

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Properties of up counter

Simulator--Cadence

Technology--180nm

W/L of pmos = 600nm/180nm

W/L of nmos = 240nm/180nm

No. of transistors = 152

Clock range 1.8v - 0v

Clock ON time =10nnm

Clock time period = 20nm

Rise & fall time = 1fs

VDD = 1.8V

GND = 0v

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Results of up counter

Avg. power consumption = 11.3μw

Delay at first stage = 176.1ps

Delay at second stage = 467.5ps

Delay at third stage = 762.1ps

Delay at fourth stage = 1.025ns

Max. frequency of operation = 5.67Ghz

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References

www.wikipedia.org/counters.

http://wearcam.org/lectureflipflop.

http://smartsim.org.uk/examples projects.

www3.panasonic.biz /applications of counters

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