Counter & Register 2

7/30/2019 Counter & Register 2

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EECC341 - ShaabanEECC341 - Shaaban#1 Lec # 18 Winter 2001 2-13-2002

Registers.

Shift Registers: Serial in, serial out shift register

Serial in, parallel out shift register

Parallel in, serial out shift register Parallel in, parallel out shift register

Shift Register Applications

Counters: Ripple Counters

Synchronous Counters

Counter Applications

Registers & CountersRegisters & Counters


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RegistersRegisters An n-bit register is a collection of n D flip-flops with a

common clock used to store n related bits.

D1Q

CLR

Q

Q/1Q

1D

D 2Q

CLR

Q

Q/2Q

2D

D3Q

CLR

Q

Q/3Q

3D

D4Q

CLR

Q

Q/4Q

4D

CLK

/CLR

74LS175Example: 74LS175

4-bit register

CLKCLR

4Q

4Q

3Q

3Q2Q

2Q

1Q

1Q

74LS175

1D

2D

3D

4D


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Shift RegistersShift Registers

Multi-bit register that moves stored data bits left/right

( 1 bit position per clock cycle)

Shift Left is towards MSB

0 1 1 1 LSI

Q3 Q2 Q1 Q0

1 1 1 LSI

Q3 Q2 Q1 Q0

RSI 0 1 1 1

Q3 Q2 Q1 Q0

RSI 0 1 1

Q3 Q2 Q1 Q0

Shift Right (or Shift Up) is towards MSB


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Serial In, Serial Out Shift RegisterSerial In, Serial Out Shift Register

D Q

CLK

D Q

CLK

D Q

CLK

SERIN

CLOCK

SEROUT

For a n-bit SRG:

Serial Out = Serial In delayed

by n clock period

4-bit shift register example:

serin: 1 0 1 1 0 0 1 1 1 0

serout: - - - - 1 0 1 1 0 0

clock:

SRG n>

SI SO


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Serial In, Parallel Out Shift registerSerial In, Parallel Out Shift register

D Q

CLK

D Q

CLK

D Q

CLK

SERIN

CLOCK

nQ

2Q

1Q

Serial to Parallel Converter

4-bit shift register example:

serin: 1 0 1 1 0 0 1 1 1 0

1Q: - 1 0 1 1 0 0 1 1 12Q: - - 1 0 1 1 0 0 1 1

3Q: - - - 1 0 1 1 0 0 1

4Q: - - - - 1 0 1 1 0 0

clock:

SRG n

>

SI 1Q

2Q

nQ (SO)


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Parallel In, Serial Out Shift RegisterParallel In, Serial Out Shift Register

SERIN

CLOCK

D Q

CLK

D Q

CLK

D Q

CLK

SEROUT

LOAD/SHIFT

1D

2D

ND

S

L

S

L

S

L

1Q

2Q

NQ

Parallel to Serial

Converter

Load/Shift=1

Di QiLoad/Shift=0

Qi Qi+1


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Parallel In, Parallel Out Shift RegisterParallel In, Parallel Out Shift Register

SERIN

CLOCK

D Q

CLK

D Q

CLK

D Q

CLK

LOAD/SHIFT

1D

2D

ND

1Q

2Q

NQ

S

L

S

L

S

L

General Purpose:

Makes any kind of

(left) shift register


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BiBi-directional Universal Shift Registers-directional Universal Shift Registers

4-bit Bi-directional Universal (4-bit) PIPO

CLK

CLR

S1S0

LIN

D QD

C QC

B QB

A QA

RIN

11

1

10

9

7

6

4

5

3

2

12

13

14

15

74x194

Modes:Hold

Load

Shift Right

Shift Left

R L

Mode Next state

Function S1 S0 QA* QB* QC* QD*Hold 0 0 QA QB QC QD

Shift right/up 0 1 RIN QA QB QC

Shift left/down 1 0 QB QC QD LIN

Load 1 1 A B C D


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Universal SR Circuit

RIGHT

CLK

/CLR

LIN

D

(11)

(1)

(7)

(6) D Q

CLK

CLR

10

00

11

01

(12)

QD

S1 S0

SL

HO

LD

SR

LEFT

74x194

D Q

CLK

CLR01

11

00

10

(15)

QA

S1

S0

A

RIN

(10)

(9)

(3)

(2)


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Shift Register ApplicationsShift Register Applications

State Registers

Shift registers are often used as the state register in a sequential

device. Usually, the next state is determined by shifting right and

inserting a primary input or output into the next position (i.e. a finite

memory machine)

Very effective for sequence detectors

Serial Interconnection of Systems keep interconnection cost low with serial interconnect

Bit Serial Operations

Bit serial operations can be performed quickly through device

iteration

Iteration (a purely combinational approach) is expensive (in terms of

# of transistors, chip area, power, etc).

A sequential approach allows the reuse of combinational functional

units throughout the multi-cycle operation


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Shift Register Applications:Shift Register Applications:

Serial Interconnection of SystemsSerial Interconnection of Systems

Serial DATAParallel-

to-serial

converter

Parallel

Datafrom

A-to-D

converter

Serial-to-

parallel

converter

ParallelData to

D-to-A

converter

Control

Circuits

CLOCK

/SYNC

TransmitterControl

Circuits

Receiver

n nOne bit


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Shift Register Applications Example:Shift Register Applications Example:

8-Bit Serial Adder8-Bit Serial Adder

...7 6 5 0>

x7 x6 x5 x0

...7 6 5 0>

y7 y6 y5 y0

...7 6 5 0>

FACout S

Cin A BD Q

CLK

CLR

CLK

CLEAR_Cz7 z6 z5 z0...

CTL Sequential Implementation of:

Z[7..0] = X[7..0] + Y[7..0]

V


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CountersCounters Clocked sequential circuit with single-cycle state

diagram

Modulo-m counter = divide-by-m counter

Most Common:

n-bit binary counter, where m = 2n n flip-flops,

counts 0 2n-1

S3

S2

S1

Sm


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Q

QT

Q

Q

T

Q

Q

T

Q

Q

T

CLK

Q0

Q1

Q2

Q3

1 bit

divide-by-2

2 bit

divide-by-4

3 bit

divide-by-8

4 bit

divide-by-16

Uses

MinimalLogic

4-bit Ripple Counter4-bit Ripple Counter


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Ripple Counter TimingRipple Counter Timing

CLK

Q0

Q1

Q2

0 1 2 3 4

1

2

3


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Ripple Counter ProblemRipple Counter Problem

n

TCQ for MSB change for n-bit ripple counter => minimum clk period

CLK

Q0

Q1

Q2

7 Should be 0 1 2

1

2

3


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Synchronous CountersSynchronous Counters

All clock inputs connected to common CLKsignal

All flip-flop outputs change simultaneously

tCQ

after CLK

Faster than ripple countersripple counters

More complex logic

Most frequently used type of counter


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Synchronous Serial CounterSynchronous Serial Counter

Flip-flops enabled

when all lower

flip-flops = 1.

Enable propagates

serially limits

speed

Requires

(n-1) t < TCLK

All outputs change

simultaneously tCQafter CLK

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3

QEN

>T

QEN

>T

QEN

>T

t

t

t


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Synchronous Parallel CounterSynchronous Parallel Counter

Single-level enable logic

per flip-flop

Fastest and most

complex type of counter

Requires t < TCLK

All outputs change

simultaneously tCQ after

CLK

>T

QEN

>T

QEN

>T

QEN

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3


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74X163 4-bit Synchronous Parallel Counter74X163 4-bit Synchronous Parallel Counter

>CLK

CLR

LD

ENP

ENTA

B

C

D

QA

QB

QC

QD

RCO

74X163

LSB

MSB

RCO = Ripple Carry Out,when Count = 1111 and ENT

= 1

Common Clock

Synchronous Clear

Synchronous Load

Count Enable = ENP ENT

Load Data Inputs


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74X163 State Table74X163 State Table

Inputs Current State Next State

/CLR /LD ENT ENP QD QC QB QA QD* QC* QB* QA*

0 X X X1 0 X X1 1 0 X1 1 1 01 1 1 1

1 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 1

X X X XX X X XX X X XX X X X0 0 0 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

0 0 0 0D C B A

QD QC QB QAQD QC QB QA

0 0 0 1

0 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 0 0 0

ClearLoadHoldHoldCount

..

.


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>CLK

UP/DN

LD

ENPENTA

B

C

D

QA

QB

QC

QD

RCO

74X169 UP/DN = 1 = up RCO = 15

UP/DN = 0 = down RCO = 0

up down up

Ex: 0,1,2, 1,0,15,14, 15,0,1,2

RCO RCO

74X169 Up/Down Counter74X169 Up/Down Counter


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EECC341 - ShaabanEECC341 - Shaaban

Counter ApplicationsCounter Applications

Count the number of times an event takes place

Control the number of steps in a sequence of fixedactions (a sequencer)

Generate timing signals (frequency divider, etc.)

ENTER

EXIT>

UP

DOWN COUNTER

# of spaces Comparator

< =

Lot

Open

Lot

Full

CLKCTR DIV 6

>

EN

Decoder

12

4

01

6

2345

7

CLR_RIN_AIN_B

EXEEXEOUT_C

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Counter & Register 2