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CoreUPROMIF_APB v2.0 Handbook

2 CoreUPROMIF_APB v2.0 Handbook

Revision History Date Revision Change March 2016 1 First release

Confidentiality Status This is a non-confidential document.

CoreUPROMIF_APB v2.0 Handbook 3

Table of Contents

Preface ............................................................................................................................ 4 About this Document ..................................................................................................................................... 4 Intended Audience ......................................................................................................................................... 4

Introduction .................................................................................................................... 5 Overview ........................................................................................................................................................ 5 Key Features ................................................................................................................................................. 5 Core Version .................................................................................................................................................. 5 Supported Families ........................................................................................................................................ 5 Device Utilization and Performance .............................................................................................................. 6

Functional Description .................................................................................................. 7

Interface Descriptions ................................................................................................... 9 Signal Descriptions ........................................................................................................................................ 9 Configuration Parameters ............................................................................................................................ 10

Timing Diagrams .......................................................................................................... 11

Register Map and Descriptions .................................................................................. 12

Tool Flows .................................................................................................................... 13 Licenses ....................................................................................................................................................... 13 RTL .............................................................................................................................................................. 13 SmartDesign ................................................................................................................................................ 13 Simulation Flows.......................................................................................................................................... 14 Synthesis in Libero ...................................................................................................................................... 15 Place-and-Route in Libero ........................................................................................................................... 15

Test-bench Operation and Modification .................................................................... 16

System Integration ....................................................................................................... 18

Design Constraints ...................................................................................................... 19

List of Changes ............................................................................................................ 25

Product Support ........................................................................................................... 26


Preface

About this Document This handbook describes the CoreUPROMIF_APB IP Core and how to use it.

Intended Audience FPGA designers using Libero® System-on-Chip (SoC).


Introduction

Overview CoreUPROMIF_APB is an APB wrapper core that provides read-only access to the uPROM memory block within RTG4™ over the APB interface. This facilitates easy access to the uPROM for APB masters.

Key Features CoreUPROMIF_APB is a highly configurable core with the following features: • Provides an APB slave interface to the uPROM memory • Maps uPROM locations to word aligned address • Prescaler for generating uPROM clock from PCLK • Provides 36-bit read data output port • Supports APB data bus width of 32-bits • Presents upper 4-bits from previously read 36-bit location • Prevents reads of invalid uPROM locations

Core Version This handbook applies to CoreUPROMIF_APB version 2.0.

Supported Families • RTG4™

Introduction


Device Utilization and Performance Utilization and performance data is listed in Table 1 for the RTG4 (RT4G150) device family. The data listed in this table is indicative only. The overall device utilization and performance of the core is system dependent.

Device Utilization and Performance Table 1

The data in this table is achieved using Verilog RTL, typical synthesis, and layout settings with a ‘-1’ speed grade part.

Family CLK_DIV

Logic Elements

PCLK Frequency (MHz) Sequential Combinatorial Total %

RTG4 1 57 71 128 0.08 158.63

RTG4 2 62 63 125 0.08 165.95

RTG4 4 62 64 126 0.08 185.53

RTG4 6 61 62 123 0.08 113.47

RTG4 8 61 63 124 0.08 166.92

RTG4 10 62 63 125 0.08 165.95

RTG4 12 62 64 126 0.08 185.53

RTG4 14 62 63 125 0.08 161.79


Functional Description

CoreUPROMIF_APB makes RTG4’s uPROM memory block appear as a transparent memory on the APB interface. Address translation is performed within CoreUPROMIF_APB to allow APB masters to address the uPROM using word aligned addressing (native uPROM memory address increments by 1 for every 36-bit location). To access the uPROM memory within RTG4, CoreUPROMIF_APB requires users to instantiate the RTG4UPROM SgCore in SmartDesign alongside CoreUPROMIF_APB and map the cores together as described in the System Integration section. The RTG4UPROM SgCore imposes a maximum frequency constraint of 30 MHz on the uPROM clock. To support this, CoreUPROMIF_APB implements a clock prescaler, which generates the uPROM clock from PCLK. The CLK_DIV generic/parameter must be updated with the associated value for the design’s PCLK frequency. Note: CoreUPROMIF_APB requires custom timing constraints to perform timing-driven Place-and-Route.

These constraints must be applied to the design to achieve timing closure. Refer to the Design Constraints section for information on the required constraints.

The size and valid address range of RTG4’s uPROM memory is die dependent, as detailed in Table 2.

RTG4 Die Specific uPROM Capacities Table 2

Die Size (Bytes) No. of 36-bit Locations

Valid Address Range

(Word Aligned)

Invalid Address Range

(Word Aligned)

RT4G150 46,800 10,400 0x0000 – 0xA27C 0xA280 – 0xFFFC

The core guards against reading from the uPROM locations in the invalid address space by returning the upper 4-bits stored from the previous read operation on a valid uPROM location for any address within the invalid address space. This also provides a means of reading the upper 4-bits of the previously addressed 36-bit uPROM location even though the APB data width of CoreUPROMIF_APB is fixed at 32-bits. Figure 1 shows the CoreUPROMIF_APB’s address map when instantiated in an RTG4 RT4G150 die. A read is performed from the address 0xA278, which returns the lower 32-bits from the addressed uPROM location. Once this operation is complete, a read of any address in the invalid address range (0xA280 - 0xFFFC for the RT4G150 die) will return the lower 4-bits held in the CoreUPROMIF_APB’s internal buffer, read from the previously addressed location in the valid address range, 0xA278 in this example.

Functional Description


Bits 31-0Bits 35-32

36-bit uPROM location

0xA27C

Bits 31-0Bits 35-320xA278

Bits 31-0Bits 35-320x0004

Bits 31-0Bits 35-320x0000

...

PADDR[15:0]

uPROM address (word aligned)

0xFFFC

UprDataBits register[3:0](contains bits 35-32 of uPROM

location 0xA278 in this example)0xA280

...

Valid address range

Invalid address range (returns upper 4 bits)

PRDATA[31:0]

Zero’s

UprDataBits register[3:0](contains bits 35-32 of uPROM

location 0xA278 in this example)Zero’s

Address pointer

Figure 1 CoreUPROMIF_APB Address Map (instantiated in RT4G150 die)


Interface Descriptions

Signal Descriptions Signal descriptions for CoreUPROMIF_APB are defined in Table 3.

CoreUPROMIF_APB I/O Signals Table 3

Port Name Width Direction Description

APB Slave Interface Ports

PCLK 1 In APB system clock. Reference clock for all internal logic. PRESETN 1 In APB active low synchronous reset. Resets all registers within

CoreUPROMIF_APB. PADDR[15:2] 14 In APB address bus. Maps directly to UPROM_ADDR [13:0]

output, making the uPROM addressing appear word-aligned. PSEL 1 In APB slave select. Select signal to registers for APB reads. PENABLE 1 In APB strobe. Indicates the second cycle of an APB transfer. PWRITE 1 In APB write or read. If low, an APB read takes place. PRDATA[31:0] 32 Out APB read data. If PADDR is addressing a valid uPROM word

aligned location, PRDATA returns the lower 32-bits from the 36-bit uPROM location. Otherwise, if PADDR is outside of the valid address range for the uPROM, PRDATA returns the upper 4-bits from the previous read operation on a valid uPROM location.

PREADY 1 Out APB ready. Used to insert wait states to extend read transfers. PSLVERR 1 Out APB Slave Error. Indicates that an error occurred during an

APB transfer. uPROM Interface Ports

UPROM_CLK 1 Out uPROM read clock. Derived from PCLK such that the maximum frequency is less than the 30 MHz constraint imposed by the RTG4UPROM SgCore. Requires user specification of the ratio between PCLK and the UPROM_CLK to the CLK_DIV parameter.

UPROM_ADDR[13:0] 14 Out Address output to uPROM. Selects the target word aligned location within the uPROM to read data from.

UPROM_RDEN 1 Out Read-enable output to uPROM. Must remain high throughout a read transfer.

UPROM_DATAR[35:0] 36 In uPROM Data Input. Data received from the addressed 36-bit location within the uPROM.

UPROM_BUSY 1 In uPROM Busy Signal. Active high signal indicating that the uPROM is busy. Read operations are not permitted when this signal is asserted.

Fabric Ports RDATA[35:0] 36 Out uPROM read data output. Data stored in the previously

addressed word location within uPROM. The RDATA output retains its value until a subsequent read of a valid uPROM location is performed.

Interface Descriptions


Configuration Parameters There are a number of configurable options, which are applied to CoreUPROMIF_APB (as shown in Table 4). If a configuration other than the default is required, then the configuration dialog box in the SmartDesign should be used to select appropriate values for the configurable options.

CoreUPROMIF_APB Configuration Options Table 4Name Valid Range Default Description

CLK_DIV 1-14 1

Specify the ratio between the design’s PCLK frequency and the UPROM_CLK frequency such that UPROM_CLK is no more than the 30 MHz maximum frequency.

PCLK Frequency (in MHz)

CLK_DIV

0 < PCLK ≤ 30 1

30 < PCLK ≤ 60 2

60 < PCLK ≤ 120 4

120 < PCLK ≤ 180 6

180 < PCLK ≤ 240 8

240 < PCLK ≤ 300 10

300 < PCLK ≤ 360 12

360 < PCLK ≤ 420 14


Timing Diagrams

Figure 2 shows typical read timing relationships when accessing RTG4 uPROM memory over the APB interface through CoreUPROMIF_APB and the RTG4UPROM SgCore. It shows the case when the system PCLK frequency is 50 MHz (UPROM_CLK = PCLK/2).

APB InterfacePCLK

PADDR[15:2]

UPROM_ADDR[13:0]

XXXX

UPROM_RDENUPROM_DATAR[35:0]

PRDATA[31:0]PREADY

UprDataBits[3:0]

XXXXRDATA[35:0]

PSEL

PENABLEPWRITE

VALIDXXXX

XXXX

VALID

VALID

XXXX

XXXX VALID XXXX

UPROM_CLK

VALIDXXXX XXXX

UPROM_BUSY

PSLVERR

uPROM Interface

Miscellaneous Signals and Registers

VALID XXXX

Figure 2 uPROM Read Transfer

Figure 3 shows the relationships between signals on the APB interface when an APB read transfer is performed on the Upper Data Bits register. The upper 4-bits read from the previously addressed 36-bit uPROM location are returned to the APB master through PRDATA.

APB InterfacePCLK

PADDR[15:2]

PRDATA[31:0]PREADY

PSEL

PENABLEPWRITE

XXXX VALID

VALIDXXXX

PSLVERR

Figure 3 Upper Data Bits Register Read Transfer


Register Map and Descriptions

The CoreUPROMIF_APB and UprDataBits registers are listed in Table 5 and Table 6.

CoreUPROMIF_APB Register Table 5Offset Register Name Type Width Reset Value Description

0xA280 – 0xFFFC

UprDataBits Read-only 32 0x0 Upper Data Bits register.

UprDataBits Register Table 6Bit(s) Name Type Description

3:0 dataBits Read-Only Upper 4-bits from the previous read operation on a valid 36-bit uPROM location. The content of this register gets updated when a subsequent read is performed on a 36-bit location within the uPROM.


Tool Flows

Licenses No license is required for the use of this core.

RTL Complete RTL source code is provided for the core and testbenches.

SmartDesign CoreUPROMIF_APB is available for download in the Libero® IP Catalog through the web repository. After it is listed in the catalog, the core can be instantiated using the SmartDesign flow. For more information on using SmartDesign to configure, connect, and generate cores, refer to the Libero Online Help. SmartDesign instantiated view is shown in Figure 4. After configuring and generating the core instance, basic functionality can be simulated using the testbench supplied with the CoreUPROMIF_APB. The testbench parameters automatically adjust to the CoreUPROMIF_APB configuration. Note: The RTG4UPROM SgCore must be instantiated with CoreUPROMIF_APB in SmartDesign and

connected to it as described in the System Integration section to provide CoreUPROMIF_APB access to the uPROM memory block.

The combination of CoreUPROMIF_APB and RTG4UPROM can be instantiated as a component of a larger design.

Figure 4 SmartDesign CoreUPROMIF_APB Instance View

Tool Flows


Figure 5 SmartDesign CoreUPROMIF_APB Configuration Dialog Box

Simulation Flows To run simulations, select the user testbench flow from SmartDesign and click Save and Generate on the Generate pane. The user testbench is selected through the Core Testbench Configuration GUI. When SmartDesign is generated in the Libero SoC project, it installs the user testbench files. To run the user testbench, set the design root to the CoreUPROMIF_APB instantiation in the Libero SoC design hierarchy pane and click Simulation in the Libero SoC design flow window. This invokes ModelSim® and automatically launches the simulation. In order for the CoreUPROMIF_APB user testbench to execute an instantiation of the RTG4UPROM SgCore must coexist in SmartDesign. Otherwise, the message as shown in Figure 6 is displayed in the ModelSim Transcript window when the user testbench is launched.

Figure 6 CoreUPROMIF_APB User Testbench RTG4UPROM Transcript Message

To allow the user testbench to execute, instantiate the RTG4UPROM SgCore from the Catalog in SmartDesign and connect it up to CoreUPROMIF_APB as described in the System Integration section. If a UPROM.mem file is not present in the simulation folder of the Libero project, the simulation will pause and a message is displayed as shown in Figure 7 in the ModelSim Transcript window.

Figure 7 CoreUPROMIF_APB user testbench UPROM.Memory Transcript Message

For the user testbench simulation to progress, a client needs to be created in the RTG4UPROM configurator. For more information about configuring the RTG4UPROM SgCore and generating a UPROM.mem file into the simulation folder of the Libero project, refer to the Testbench Operation and Modification section.

Tool Flows


Synthesis in Libero To run synthesis on the CoreUPROMIF_APB, set the design root to the IP component instance and run the synthesis tool from the Libero design flow pane. Note: The design constraints that are detailed in the Design Constraints section must not be associated with

the Synthesis stage of the design flow, as errors may get generated due to the differences between the SDC syntax supported by Libero and Synplify.

Place-and-Route in Libero After the design is synthesized, run the compilation and then place-and-route the tools. Note: CoreUPROMIF_APB requires that the Repair Minimum Delay Violations option is selected along

with the Timing-driven layout. These options are selected by default, but right-clicking on the Place-and-Route entry in the Design Flow window and selecting Configure Options allows these settings to be verified/configured.


Test-bench Operation and Modification

The testbench packaged along with CoreUPROMIF_APB includes an instantiation of CoreUPROMIF_APB, connected up to the RTG4UPROM SgCore as shown in Figure 8. In order for the user testbench to execute an instantiation of the RTG4UPROM component must exist in SmartDesign alongside the CoreUPROMIF_APB instance, with a valid memory client defined for RTG4UPROM.

User Testbench

BFM_APB

APB Master BFM Script

(.bfm file)

APB I/F

bfmtovec.exe compiler

APB Master Vectors

(.vec file)

File I/O

CoreUPROMIF_APB

APB I/F

RTG4UPROM

UPROM macro

UPROM(.mem file)

UPROM I/F

Figure 8 User Testbench

The CoreUPROMIF_APB testbench environment consists of the following components: • BFM_APB: The APB_BFM component is a bus functional model (BFM), which emulates the operation of an

APB bus master. The operations carried out by the APB master are issued from the APB Master BFM script (user_tb.bfm file in the simulation folder of the Libero project). This BFM script is compiled into a vectorfile and passed to the BFM_APB component in the testbench. The default user_tb.bfm file, packaged along with CoreUPROMIF_APB performs a number of APB reads from the specific uPROM locations. Users can

Test-bench Operation and Modification


modify this script in order to simulate custom cases. For more information about modifying the contents of the user_tb.bfm script, refer to the DirectCore Advanced Microcontroller Bus Architecture – Bus Function Model User’s Guide.

• CoreUPROMIF_APB: Instantiation of the CoreUPROMIF_APB (DUT). Simulation is performed using the custom configuration of CoreUPROMIF_APB configured in SmartDesign.

• RTG4UPROM: An instantiation of the RTG4UPROM SgCore is required to provide access to RTG4’s uPROM memory. The content of the uPROM memory for simulation is determined by that of the UPROM.mem file (Microsemi binary format). The following procedure must be followed in order to generate a UPROM.mem file into the simulation folder of the Libero project:

1. Launch the uPROM client configurator for RTG4UPROM by right-clicking on the RTG4UPROM component in SmartDesign and selecting Configure.

2. Create a client as per the procedure defined in the RTG4 uPROM Configuration User Guide, and select the Use content for simulation checkbox in the Add/Edit Data Storage Client window.

3. Set the SmartDesign component as the root of the build by right-clicking on the SmartDesign component in the Design Hierarchy window and select Set as root.

4. Launch a Pre-Synthesis simulation from the Design Flow window. The dialog box as shown in Figure 9 is displayed. Select Yes to continue to launch the simulation.

Figure 9 Pre-synthesis Simulation Warning (No stimulus file in the project)

5. Alternatively, if a stimulus file for another testbench already exists in the project, the dialog box as shown in Figure 10 is displayed. Select No to continue to launch the simulation.

Figure 10 Pre-synthesis Simulation Warning (No associated stimulus)

6. A ModelSim window gets launched but the simulation will pause due to the absence of an active stimulus. Close the ModelSim window and return to Libero. The purpose of steps 4-6 was to force the UPROM.mem file to be generated into the simulation folder of the Libero project.

7. Set the CoreUPROMIF component as the root of the build by right-clicking on the CoreUPROMIF_APB component in the Design Hierarchy window and select Set as root.

8. Launch a Pre-Synthesis simulation from the Design Flow window. A ModelSim window gets launched, executing CoreUPROMIF_APB’s user testbench. Information of the APB read transactions performed are displayed in ModelSim’s Transcript window.

Note: The entire procedure outlined above needs to be reiterated, if any changes are made in the RTG4UPROM client configurator or user specified .mem file.

http://www.actel.com/ipdocs/CoreAMBA_BFM_UG.pdf

http://www.actel.com/ipdocs/CoreAMBA_BFM_UG.pdf

http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=135673


System Integration

To access RTG4’s uPROM memory block, CoreUPROMIF_APB needs to be instantiated with the RTG4UPROM SgCore and connected up, as shown in Figure 11.

Figure 11 CoreUPROMIF_APB Instantiation and Mapping the RTG4UPROM SgCore

To configure the uPROM memory contents users can right-click on the RTG4UPROM component in SmartDesign and select Configure. For more information on how to configure the RTG4UPROM component, refer to the RTG4 uPROM Configuration User Guide.

http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=135673


Design Constraints

Designs that contain CoreUPROMIF_APB and the RTG4UPROM SgCore require the following constraints to be applied in the design flow to prevent timing violations occurring in the design. The procedure for adding the constraints is as follows:

1. If the Enhanced Constraint flow in Libero v11.7 or later is used, double-click Constraints > Manage Constraints in the Design Flow window and click the Timing tab. Otherwise, go to step 3. If the design sources PCLK from a PLL, select Derive to automatically create a constraints file containing the PLL constraints, otherwise go to step 2. Select No when prompted to prevent the constraints being automatically included for Synthesis, Place-and-Route, and Timing Verification stages. If changes are made to the PLL configuration in the design, update the contents of this file by clicking Derive. Select Yes when prompted to allow the constraints to be overwritten. If the design’s PCLK frequency is not more than 30 MHz, go to step 11. Otherwise, in the Timing tab of the Constraint Manager window, select New to create a new SDC file, and name it. Design constraints other than the clock source constraints can be entered in this blank SDC file. Go to step 7.

2. If the Enhanced Constraint flow in Libero v11.7 or later is used and PCLK is sourced externally via a clock pad, in the Timing tab of the Constraint Manager window, select New to create a new SDC file and name it. The design constraints along with the clock source constraints can be entered in this blank SDC file. Go to step 4.

3. If Libero v11.6 or the Classic Constraint flow in Libero v11.7 or later is used, right-click Create Constraints > Timing Constraint in the Design Flow window and click Create New Constraint. This creates a new SDC file. The design constraints including the clock source constraints can be entered in this blank SDC file. Go to step 4.

4. If PCLK is sourced from a PLL in the design, go to step 5. Otherwise, if the design sources PCLK externally, calculate the PCLK period and half period. After completion, enter the following constraints in the SDC file:

create_clock -name { PCLK } \

-period PCLK_PERIOD \

-waveform { 0 PCLK_HALF_PERIOD } \

[ get_ports { PCLK } ]

For example, the following constraints need to be applied for a design that uses a PCLK frequency of 80 MHz:

create_clock -name { PCLK } \

-period 12.5 \

-waveform { 0 6.25 } \

[ get_ports { PCLK } ]

If the design’s PCLK frequency is greater than 30 MHz go to step 8, otherwise go to step 11 as PCLK is fed through as UPROM_CLK.

5. As the design sources PCLK from a PLL, constraints need to be applied to specify the frequency of the clock source to the PLL. The output of the PLL is determined by the PLL configuration.

Design Constraints


Clock Prescaler

CoreUPROMIF_APB

RTG4UPROM

GBRBuffer

Dedicated clock pad

RGBBuffer

APB Slave Logic

UPROM_CLK generated clock constraint

CLK_INPUTclock constraint

On-chipOscillator

Fabricinput

RTG4FCCC(PLL)

Source/Reference

Source/Reference

PCLK generated

clock constraint

(Buffers automatically inferred by tools)

Figure 12 Constraining a Design Sourcing PCLK from a PLL

Add the following constraints to specify the frequency of the clock input to the PLL. This input can be sourced from a dedicated clock pad input, a fabric input, or from the on-chip oscillator.

create_clock -name { CLK_INPUT } \

-period CLK_INPUT_PERIOD \

-waveform { 0 CLK_INPUT_HALF_PERIOD } \

[ get_ports { CLK_INPUT_PORT_PIN } ]

Where: CLK_INPUT_PERIOD is the period of the input source to the PLL CLK_INPUT_HALF_PERIOD is the half period of the input source to the PLL CLK_INPUT_PORT_PIN is the external port from which the clock is sourced when

using an external clock input routed through the fabric or when using a dedicated clock pad. If using a fabric generated clock or an on-chip oscillator, get_pins must be used in place of the get_ports command in the constraint shown above.

For example, if the CLK0 dedicated input pad is connected to an external 100 MHz oscillator, apply the following constraint:


-period 10 \

-waveform { 0 5 } \

[ get_ports { CLK0_PAD } ]

Alternatively, if the on-chip 50 MHz RC oscillator is used, apply the following constraint:


-period 20 \

-waveform { 0 10 } \

[ get_pins { RCOSC_50MHZ_0*CLKOUT } ]

6. Apply the following constraint to the output of the PLL that PCLK is sourced from:

create_generated_clock -name { PCLK } \

-multiply_by MULTI_VAR \

-divide_by DIV_VAR \

-source [ get_pins { RTG4FCCC_HIER_INST/CCC_INST*FCCC_INPUT } ] \

Design Constraints


[ get_pins { RTG4FCCC_HIER_INST/CCC_INST*FCCC_OUTPUT } ]

Where: MULTI_VAR is the factor by which the input clock is multiplied within the PLL (FCCC)

to achieve the output clock frequency DIV_VAR is the factor by which the input clock is divided within the PLL to achieve

the output clock frequency RTG4FCCC_HIER_INST is the hierarchical instance name and path to the

RTG4FCCC instantiation FCCC_INPUT is the name of the FCCC input from which PCLK is derived FCCC_OUTPUT is the FCCC output that PCLK is sourced from.

The MULTI_VAR and DIV_VAR arguments to the constraint specified above are determined by the configuration of the FCCC. Changes made to the PLL configuration must be reflected in these arguments. For example, if an 80 MHz PCLK is sourced from the GL0 output of a PLL connected to an external 100 MHz RC oscillator routed through the CLK0_PAD dedicated clock pad, the following constraint needs to be applied:

create_generated_clock -name { PCLK } \

-multiply_by 4 \

-divide_by 5 \

-source [ get_pins { RTG4FCCC_0/CCC_INST*CLK0_PAD } ] \

[ get_pins { RTG4FCCC_0/CCC_INST*GL0 } ]

If the design uses a PCLK frequency of more than 30 MHz go to step 7. Otherwise, go to step 11 as PCLK is fed through as UPROM_CLK.

7. As the design’s PCLK frequency is greater than 30 MHz, UPROM_CLK is generated using a register-based clock prescaler. As PCLK is sourced from the output of a PLL, apply the following constraint to UPROM_CLK:

create_generated_clock -name { UPROM_CLOCK } \

-divide_by CLK_DIV \

-source [ get_pins { RTG4FCCC_HIER_INST/CCC_INST*FCCC_OUTPUT } ] \

[ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_CLK_reg*Q } ]

Where: CLK_DIV mirrors the value specified for the CLK_DIV parameter in the Core

Configuration window. Refer to the Configuration Parameters section to determine the value of CLK_DIV.

RTG4FCCC_HIER_INST is the hierarchical instance name and path to the RTG4FCCC instantiation

FCCC_OUTPUT is the FCCC output that PCLK is sourced from COREUPROMIF_APB_HIER_INST is the hierarchical instance name and path to the

CoreUPROMIF_APB instantiation The generated clock constraints must not be applied from the source of the master clock in this instance. This preserves the clock insertion delay from the master clock source for timing analysis. For example, a design uses an 80 MHz PCLK sourced from the GL0 output of RTG4FCCC with instance name RTG4FCCC_0. A CoreUPROMIF_APB instance exists one level down in TOP_0, with an instance name COREUPROMIF_APB_0. In this case, the following constraints need to be applied to UPROM_CLK:


-divide_by 4 \

-source [ get_pins { RTG4FCCC_0/CCC_INST*GL0 } ] \

[ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_CLK_reg*Q } ]

Go to step 9, as step 8 is irrelevant because PCLK is sourced from a PLL.

Design Constraints


8. As PCLK is sourced from an external input and has a frequency of greater than 30 MHz, UPROM_CLK is generated from PCLK using a register-based clock divider and must be constrained using the following constraint:


-divide_by CLK_DIV \

-source [ get_ports { PCLK } ] \

[ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_CLK_reg*Q } ]

Where: CLK_DIV mirrors the value specified for the CLK_DIV parameter in the Core

Configuration window. Refer to the Configuration Parameters section to determine the value of CLK_DIV.

COREUPROMIF_APB_HIER_INST is the hierarchical instance name and path to the CoreUPROMIF_APB instantiation.

For example, CoreUPROMIF_APB is instantiated one level down from the root of the design in TOP_0. The CoreUPROMIF_APB instance name is COREUPROMIF_APB_0, and the design’s PCLK frequency is 80 MHz:


-divide_by 4 \

-source [ get_ports { PCLK } ] \

[ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_CLK_reg*Q } ]

9. Add the constraints to the paths from the PCLK domain to the UPROM_CLK domain as shown:

set_min_delay MIN_DELAY \

-from { [ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_RDEN_reg*CLK } ] } \

-to { [ get_pins { RTG4UPROM_HIER_INST/UPROM_0*RDEN } ] }

set_max_delay MAX_DELAY \

-from { [ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_RDEN_reg*CLK } ] } \

-to { [ get_pins { RTG4UPROM_HIER_INST/UPROM_0*RDEN } ] }


-from { [ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_ADDR_reg*CLK* } ] } \

-to { [ get_pins { RTG4UPROM_HIER_INST/UPROM_0*ADDR* } ] }


-from { [ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_ADDR_reg*CLK* } ] } \

-to { [ get_pins { RTG4UPROM_HIER_INST/UPROM_0*ADDR* } ] }

Where: COREUPROMIF_APB_HIER_INST is the hierarchical instance name and path to the

CoreUPROMIF_APB instantiation. RTG4UPROM_HIER_INST is the hierarchical instance name and path to the

RTG4UPROM SgCore instantiation. MIN_DELAY specifies when the hold time check occurs. The value specified must be

zero for all cases. MAX_DELAY specifies when the setup time check occurs. The value specified must

be calculated using the following formula: 𝑀𝑀𝑀𝑀𝑀𝑀_𝐷𝐷𝐷𝐷𝐷𝐷𝑀𝑀𝐷𝐷 = 𝑃𝑃𝑃𝑃𝐷𝐷𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 ∗ 𝑃𝑃𝐷𝐷𝐾𝐾_𝐷𝐷𝐷𝐷𝐷𝐷

SmartTime adds the clock skew associated with generating UPROM_CLK to the MAX_DELAY value specified for setup time checking and subtracts the skew from the MIN_DELAY value for hold time checking.

Design Constraints


For example, CoreUPROMIF_APB is instantiated one level down from the root of the design in ‘TOP_0’. The CoreUPROMIF_APB instance name is COREUPROMIF_APB_0. The RTG4UPROM instance name is RTG4UPROM_0, and the design’s PCLK frequency is 80 MHz.

set_min_delay 0 \

-from { [ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_RDEN_reg*CLK } ] } \

-to { [ get_pins { TOP_0/RTG4UPROM_0/UPROM_0*RDEN } ] }

set_max_delay 50 \

-from { [ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_RDEN_reg*CLK } ] } \

-to { [ get_pins { TOP_0/RTG4UPROM_0/UPROM_0*RDEN } ] }

set_min_delay 0 \

-from { [ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_ADDR_reg*CLK* } ] } \

-to { [ get_pins { TOP_0/RTG4UPROM_0/UPROM_0*ADDR*} ] }

set_max_delay 50 \

-from { [ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_ADDR_reg*CLK* } ] } \

-to { [ get_pins { TOP_0/RTG4UPROM_0/UPROM_0*ADDR*} ] }

These constraints enable the setup and hold time checking on the paths from the PCLK domain to the UPROM_CLK domain in SmartTime.

PCLK

UPROM_CLK

Skew due to clock generation

Hold check edge Setup Check Edge

Figure 13 Setup and Hold Checking – PCLK to UPROM_CLK

10. Add the following constraints to the paths from the UPROM_CLK domain to the PCLK domain:


-from { UPROM_CLOCK } \

-to { [ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_DATAR_reg*D* } ] }



-to { [ get_pins { COREUPROM_IF_APB_HIER_INST/UPROM_DATAR_reg*D* } ] }

Where: COREUPROMIF_APB_HIER_INST is the hierarchical instance name and path to the

CoreUPROMIF_APB instantiation. MIN_DELAY specifies when the hold time check occurs. The value specified must be

zero for all cases. MAX_DELAY specifies when the setup time check occurs. The value specified must

be calculated using the following formula: 𝑀𝑀𝑀𝑀𝑀𝑀_𝐷𝐷𝐷𝐷𝐷𝐷𝑀𝑀𝐷𝐷 = 𝑃𝑃𝑃𝑃𝐷𝐷𝐾𝐾𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 ∗ 𝑃𝑃𝐷𝐷𝐾𝐾_𝐷𝐷𝐷𝐷𝐷𝐷

SmartTime subtracts the clock skew associated with generating UPROM_CLK from the MAX_DELAY value specified for setup time checking and adds the skew to the MIN_DELAY value for hold time checking.

Design Constraints


For example, CoreUPROMIF_APB is instantiated one level down from the root of the design in TOP_0. The CoreUPROMIF_APB instance name is COREUPROMIF_APB_0. The design’s PCLK frequency is 80 MHz:

set_min_delay 0 \


-to { [ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_DATAR_reg*D* } ] }

set_max_delay 50 \


-to { [ get_pins { TOP_0/COREUPROMIF_APB_0/UPROM_DATAR_reg*D* } ] }

These constraints enable the setup and hold time checking results on the paths from the UPROM_CLK domain to the PCLK domain in SmartTime.

PCLK

UPROM_CLKSkew due to

clock generation

Hold check edge Setup check edge

Figure 14 Setup and Hold Checking – UPROM_CLK to PCLK

11. Associate all constraints files with the Place-and-Route and Timing Verification stages in the Constraint Manager > Timing tab by selecting the related check boxes for the SDC file(s) in which the constraints were entered in.


List of Changes

The following table lists important changes that were made in each revision of the document. Date Change Page March 2016 Initial release. N/A


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mailto:[email protected]

http://www.microsemi.com/soc/mycases/


Product Support


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Documents

CoreUPROMIF APB v2 - Actel › ipdocs › CoreUPROMIF_APB_HB.pdf · CoreUPROMIF_APB is an APB wrapper core that provides read-only access to the uPROM memory block within RTG4™