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Copyright © Am Road Electronics Co., Ltd.
TMS320C24x OverviewTMS320C24x Overview
Max Chyou
Engineering Manager
AmRoad Co.Ltd.
ContentsContents
Introduction
Architectural Overview
Clocks
Power Management
Interrupts
Timer
PWM Architecture
Space Vector
Q&A
IntroductionIntroduction
IntroductionIntroduction
Why DSP?
Benefits of Digital System
Reliability, flexibility
Time sharing / task switching
Freedom from environmental effects
Bandwidth and resolution of analog system
IntroductionIntroduction
Why DSP?
Optimized Architecture
Instruction set tailored for signal processing functions
Architecture minimizes numerical problems in processing discrete signals
IntroductionIntroduction
Why DSP?
High Performance
Implementation of complex algorithms in real-time
Implementation of high sampling rates
Minimizes computational delay
Performance to implement multiple functions
IntroductionIntroduction
FeaturesFeatures Single-cycle instruction
DSP instruction set
Multiple buses
Hardware multiplier
Hardware scaling shifters
BenefitsBenefits High sampling rates /
control of high bandwidth system
Real-time execution of advanced control algorithms
Simultaneous access of data and instructions
Minimize computational delays
IntroductionIntroduction
FeaturesFeatures Hardware scaling shifters
16-bit word length
32-bit ALU / ACC
Hardware stack
Saturation mode
BenefitsBenefits Fast scaling / dynamic
range
Minimize quantization errors
Minimize truncation errors
Fast interrupt processing
Prevent wrap around of ACC
IntroductionIntroduction
FunctionFunction Notch filter algorithms
Adaptive Kalman filter algorithms
State estimator algorithms
Vector control algorithms
Pulse width modulation (PWM)
BenefitsBenefits Cancel mechanical
resonance
Reduce sensor noise
Estimate multiple variables
Real-time axis transformation
Improve motor control
IntroductionIntroduction
FunctionFunction Notch filter algorithms
Adaptive Kalman filter algorithms
State estimator algorithms
Vector control algorithms
Pulse width modulation (PWM)
BenefitsBenefits Cancel mechanical
resonance
Reduce sensor noise
Estimate multiple variables
Real-time axis transformation
Improve motor control
IntroductionIntroduction
FunctionFunction High order PID control
loop
High sample rate
Time division multiplexing
Fuzzy set control algorithms
BenefitsBenefits Precise control
High system bandwidth
Several control system implementations with 1 DSP device
“Intelligent” control
IntroductionIntroduction
FunctionFunction Dead band controller
State controller
Power factor correction
FFT algorithms
Adaptive control algorithms
BenefitsBenefits Quick settling time
Control many variables
Reduce motor power loss
Analyze mechanical resonance
Reduce disturbance effects
DSP COREDSP CORE
Core ArchitectureCore Architecture
MultiplierMultiplierMultiplierMultiplier
DataData
MemoryMemory
DataData
MemoryMemory
Program Program
MemoryMemory
Program Program
MemoryMemory
ALU/ShiftersALU/ShiftersALU/ShiftersALU/Shifters
Per
iph
eral
sP
erip
her
als
Con
trol
ler
Con
trol
ler
A(15-0)A(15-0)
D(15-0)D(15-0)
Program BusProgram Bus
Data BusData Bus
••
••MemoryMemory
MappedMapped
RegistersRegisters
MemoryMemory
MappedMapped
RegistersRegisters
SystemSystemInterfaceInterfaceModule *Module *
* ‘* ‘C240 OnlyC240 Only
PeripheralsPeripherals(Event Mgr)(Event Mgr)
Core ArchitectureCore Architecture
MUXMUXT (16)T (16)MULTIPLIERMULTIPLIER
P (32)P (32)
SHIFTER (-6, 0, 1, 4)SHIFTER (-6, 0, 1, 4)
SHIFTER (0-16)SHIFTER (0-16)
MUXMUX
ACCH (16)ACCH (16)
SFL (0-7)SFL (0-7)
CC
Data BusData Bus
Data BusData Bus
1616
3232
ALU (32)ALU (32)
3232
3232
3232
1616
1616
1616
3232
3232
ACCL (16)ACCL (16)
1616 1616
1616
1616
3232
••
Core ArchitectureCore Architecture
Data BusData Bus
STACKSTACK(8(8x16)x16)
PCPC
ProgramProgramROM /ROM /FLASHFLASH
AddressAddress
InstructionInstruction
To Data MemoryTo Data Memory
MU
XM
UX
MU
XM
UX
MUXMUX
D(15-0)D(15-0)
A(15-0)A(15-0)
••
••
••12-1512-15
1616
16161616
1616
1616
1616
1616
1616
1616
1616
1616
1616
Program BusProgram Bus
PeripheralPeripheral
Clock SignalsClock Signals
crystalcrystalx4x4
PLLPLLClock ModuleClock Module
x4x4PLLPLL
Clock ModuleClock Module
39.0625 39.0625 kHzkHzPrescalerPrescaler
WatchdogWatchdogWDCLKWDCLK
CPUCLKCPUCLK
XTAL1XTAL1
XTAL2XTAL2
Event ManagerEvent Manager
Core MemoryCore Memory
External Memory External Memory InterfaceInterface
SPISPISCISCI
CANCANCPUCPU
PrescalerPrescaler ADCADCADCCLKADCCLK
CLKOUTCLKOUT
ArchitectureArchitectureData BusData Bus
Program BusProgram BusAR0(16)AR0(16)AR1(16)AR1(16)AR2(16)AR2(16)AR3(16)AR3(16)AR4(16)AR4(16)AR5(16)AR5(16)AR6(16)AR6(16)AR7(16)AR7(16)
ARAU(16)ARAU(16)
ARP(3)ARP(3)
ARB(3)ARB(3)
DP(9)DP(9)
DataData
RAMRAM
MUXMUX
MUXMUX MUXMUX
MUXMUX
From Program MemoryFrom Program Memory
Data / ProgramData / Program
RAMRAM
••••••
16161616
16161616
1616
1616
1616
1616
1616
1616 1616
1616
997 7 LSBLSBFrom IRFrom IR
1616
33
99
1616
33
33
33
ArchitectureArchitecture
Event ManagerEvent ManagerGP TimersGP Timers
Compare UnitCompare Unit
PWM OutputsPWM Outputs
Dead-Band LogicDead-Band Logic
Capture UnitCapture Unit
QuadratureQuadratureEncoderEncoder
Pulse (QEP)Pulse (QEP)
Dat
a B
us
Dat
a B
us
Watchdog TimerWatchdog Timer
SCISCI
SPISPI
A/D ConverterA/D Converter
I /O PinsI /O Pins
CANCAN
Non-EV ManagerNon-EV Manager
SystemSystemInterfaceInterfaceModuleModule
(‘F/C240 only)(‘F/C240 only)
Watchdog TimerWatchdog Timer
6 - 6 - BitBitFree -Free -RunningRunningCounterCounter
CLRCLR/2/2/4/4/8/8/16/16/32/32/64/64
WDCLKWDCLK
SystemSystemResetReset
101101100100011011010010001001
000000
111111110110
••
••
••
••
8 - 8 - Bit WatchdogBit WatchdogCounterCounter
CLRCLR
One-CycleOne-CycleDelayDelay
WatchdogWatchdogReset KeyReset KeyRegisterRegister
55 + 55 + AAAADetectorDetector
••
Good KeyGood Key
Bad KeyBad Key
1 0 11 0 1•• ••
••••
••
////33
33
WDCR . 2 - 0WDCR . 2 - 0
WDCR . 6WDCR . 6
WDPSWDPS
WDDISWDDIS
WDCNTR . 7 - 0WDCNTR . 7 - 0
WDCR . 5 - 3WDCR . 5 - 3 WDCHK 2-0WDCHK 2-0
Bad WDCR KeyBad WDCR Key
Power ManagerPower ManagerLow Power ModeLow Power Mode
Normal RunNormal Run
Idle 1Idle 1
Idle 2Idle 2
HaltHalt
CommentsComments
CPU offCPU off
All Peripherals offAll Peripherals off(except watchdog)(except watchdog)
Oscillator & Watchdog offOscillator & Watchdog off
PowerPower
~80 mA @ 20 MIPS~80 mA @ 20 MIPS
~ 50 mA~ 50 mA
~ 7 mA~ 7 mA
~ < 1 mA~ < 1 mA
Note: PLL is on all the time for ‘X241/2/3!Note: PLL is on all the time for ‘X241/2/3!
Interrupt Interrupt
NMINMI
‘‘C24xC24xCORECORE
2 non-maskable interrupts (RS, NMI)
6 maskable interrupts (INT1 - INT6)
INT1INT1
INT5INT5
INT2INT2
INT3INT3
INT4INT4
INT6INT6
RSRS
System ResetSystem Reset
Watchdog TimerWatchdog Timer
RS pin activeRS pin active
To RS pinTo RS pin
RSRS
‘‘C24x CoreC24x Core
Reset Reset
‘‘C24xC24x
RSRS
1010KK
VVcccc ExternalExternalDeviceDevice
resetreset••••
RSRS17 17 CPUCLK cyclesCPUCLK cycles
8 8 cycles min.cycles min.Reset VectorReset Vector
FetchedFetched
• RS pin must be held low a minimum of one CPUCLK RS pin must be held low a minimum of one CPUCLK cycle to ensure recognition of a resetcycle to ensure recognition of a reset
• Once a reset source is activated, RS pin is driven low Once a reset source is activated, RS pin is driven low for 8 CPUCLK cycles minimumfor 8 CPUCLK cycles minimum
Event ManagementEvent Management
EV and Non-EVEV and Non-EVPeripheralsPeripherals
XINT1XINT1
XINT2XINT2
PDPINTPDPINT
NMINMI
RSRS
EV and EV and Non-EVNon-EV
PeripheralPeripheralInterfaceInterface
Internal SourcesInternal Sources
External SourcesExternal SourcesNMINMI
‘‘C24x COREC24x CORE
INT1INT1
INT5INT5
INT2INT2
INT3INT3
INT4INT4
INT6INT6
RSRS
Event ManagementEvent Management
INT1INT1
INT2INT2
INT3INT3
11
00
11
‘‘C24xC24xCoreCore
((INTM)INTM)““Global Switch”Global Switch”
((IMR)IMR)““Switch”Switch”
((IFR)IFR)““Latch”Latch”
CoreCoreInterruptInterrupt
Event ManagementEvent Management
ArbitratorArbitrator
FlagFlag EnableEnable
XINT1XINT1
FlagFlag
XINT2XINT2
FlagFlag
ADCINTADCINT
To CoreTo CoreInterruptInterrupt
INT1INT1
EnableEnable
EnableEnable
PolarityPolarity
PolarityPolarity
Event ManagementEvent Management
INT1INT1
INT2INT2
INT3INT3
INT4INT4
INT5INT5
INT6INT6
Capture 1,2,3Capture 1,2,3Capture 1,2,3Capture 1,2,3
Timer 2Timer 2Timer 2Timer 2
Compare 1,2,3Compare 1,2,3Timer 1Timer 1
Compare 1,2,3Compare 1,2,3Timer 1Timer 1
EVEV
ADC (low priority)ADC (low priority)XINT1,2 (low priority)XINT1,2 (low priority)
ADC (low priority)ADC (low priority)XINT1,2 (low priority)XINT1,2 (low priority)
SPI, SCI, CAN (low priority)SPI, SCI, CAN (low priority)SPI, SCI, CAN (low priority)SPI, SCI, CAN (low priority)
XINT1,2 (high priority)XINT1,2 (high priority)SPI, SCI, CAN (high priority)SPI, SCI, CAN (high priority)
ADC (high priority)ADC (high priority)
XINT1,2 (high priority)XINT1,2 (high priority)SPI, SCI, CAN (high priority)SPI, SCI, CAN (high priority)
ADC (high priority)ADC (high priority) NonNonEVEV
CoreCore
PDPINTPDPINTPDPINTPDPINT
••
LatencyLatency
Latency delay between an interrupt request and the first interrupt
specific code fetch
TMS320C24x Latency Components Peripheral interface time (synchronization) CPU response time (core latency) ISR branching time (ISR latency)
Stack OperationStack Operation
ACCLACCL
PCPC
PUSHPUSH POPPOP
8-8-LEVELLEVEL
HARDWAREHARDWARE
STACKSTACK
POPDPOPD
PSHDPSHD
DATADATAMEMORYMEMORY
INTINTCALLCALL
RETRET
Hardware stack is expandable to data memory Hardware stack is expandable to data memory using PSHD/POPDusing PSHD/POPD
ProtectionProtection Interrupt latency may not protect hardware when Interrupt latency may not protect hardware when
responding to over current through ISR softwareresponding to over current through ISR software
PDPINT has a fast, clock independent logic path to high-PDPINT has a fast, clock independent logic path to high-impedance the PWM output pins (~ 45-55 ns) impedance the PWM output pins (~ 45-55 ns)
DSPDSPCORECOREDSPDSP
CORECORE
PPWWMM
OOUUTTPPUUTTSSPDPINT EnablePDPINT Enable
OverOverCurrentCurrentSensorSensor
OverOverCurrentCurrentSensorSensor
‘‘C24xC24x
PDPINTPDPINTflagflag
PDPINTPDPINTflagflag
clock synch.clock synch.clock synch.clock synch.
TimerTimer
GP TimerGP TimerGP TimerGP Timer
Stop/HoldStop/HoldStop/HoldStop/Hold Up CountingUp CountingUp CountingUp Counting Up/Down CountingUp/Down CountingUp/Down CountingUp/Down Counting
ContinuousContinuousContinuousContinuous ContinuousContinuousContinuousContinuous
DirectionalDirectionalDirectionalDirectional
Timer ArchitectureTimer Architecture
TxCNTTxCNTTimerTimer
CounterCounter
TxCNTTxCNTTimerTimer
CounterCounter
TxPRTxPRPeriod RegisterPeriod Register
TxPRTxPRPeriod RegisterPeriod Register
Period RegisterPeriod RegisterBufferBuffer
Period RegisterPeriod RegisterBufferBuffer
CompareCompareLogicLogic
CompareCompareLogicLogic16
16
PrescalePrescaleCountersCounters
PrescalePrescaleCountersCounters
clockingclockingsignalsignal
TMRDIRTMRDIRpinpin
auto-load on underflowauto-load on underflow
MUXMUX
TMRCLKTMRCLKpinpin
CPUCLKCPUCLK(internal DSP)(internal DSP)
UP TimerUP Timer
0011
2233
0011
2233
0011
22
CPUCLKCPUCLK
TxCNT Reg.TxCNT Reg.
TxCON[6]TxCON[6]
CPU writes a 2 to CPU writes a 2 to period reg. bufferperiod reg. buffer
anytime hereanytime here
TxPR=2 is auto-loaded TxPR=2 is auto-loaded on underflow hereon underflow here
This example:This example:TxPR = 3 (initially)TxPR = 3 (initially)Prescale = 1Prescale = 1
0011
22
U/D TimerU/D Timer
CPUCLKCPUCLK
TxCON[6]TxCON[6]
0011
2233
TxCNT Reg.TxCNT Reg.
2211
0011
2211
2211
0011
00
CPU writes a 2 to CPU writes a 2 to period reg. bufferperiod reg. buffer
anytime hereanytime hereTxPR=2 is auto-loaded TxPR=2 is auto-loaded on underflow hereon underflow here
This example:This example:TxPR = 3 (initially)TxPR = 3 (initially)Prescale = 1Prescale = 1
Seamless up/down repetition
Up/down count period is 2*TxPR
PWM ArchitecturePWM Architecture
PWM CircuitsPWM Circuits
PWM CircuitsPWM Circuits
PWM CircuitsPWM Circuits
Output LogicOutput Logic
Output LogicOutput Logic
Output LogicOutput Logic
GP Timer 1 CompareGP Timer 1 Compare
GP Timer 1GP Timer 1
GP Timer 2 CompareGP Timer 2 Compare
GP Timer 2GP Timer 2
Full Compare 1Full Compare 1
Full Compare 2Full Compare 2
Full Compare 3Full Compare 3
Capture UnitsCapture Units
MUXMUXQEPQEP
CircuitCircuit
WaveformWaveformGeneratorGenerator Output LogicOutput Logic
WaveformWaveformGeneratorGenerator Output LogicOutput Logic
EV Control Registers / LogicEV Control Registers / Logic
Reset INT2, 3, 4
TMRCLK / TMRDIR/2
ADC Start
Dat
a B
us
•
CLK
DIR
••
T1PWM/T1CMP
T2PWM/T2CMP
PWM1/CMP1PWM2/CMP2PWM3/CMP3PWM4/CMP4PWM5/CMP5PWM6/CMP6
CAP1/QEP1CAP2/QEP2CAP3
TIMERTIMER
CPUCLKCPUCLK
TxCNT Reg.TxCNT Reg.
TxCON[6]TxCON[6]
0011
2233
0011
2233
00 00 00 00 00
33 33
TMRDIRTMRDIR
Count holds at TxPR=3Count holds at TxPR=3since TMRDIR = hisince TMRDIR = hion rising clock edgeon rising clock edge
2 2 CPUCLK latencyCPUCLK latency2 2 CPUCLK latencyCPUCLK latency
This example:This example:TxPR = 3TxPR = 3Prescale = 1Prescale = 1CPUCLK as sourceCPUCLK as source
PWM ArchitecturePWM ArchitectureThis example:This example:TxCON.3-2 = 00 (reload TxCMP on underflow)TxCON.3-2 = 00 (reload TxCMP on underflow)TxPR = 3TxPR = 3TxCMP = 1 (initially)TxCMP = 1 (initially)Prescale = 1Prescale = 1
0011
2233
0011
2233
0011
22
CPUCLKCPUCLK
TxCNT Reg.TxCNT Reg.
33
00
CPU writes a 2 to CPU writes a 2 to compare reg. buffercompare reg. buffer
anytime hereanytime here TxCMP=2 is loaded hereTxCMP=2 is loaded here
TxPWM/TxCMPTxPWM/TxCMP(active high)(active high)
TxCINTTxCINT
PWM ArchitecturePWM Architecture
CPUCLKCPUCLK
0011
2233
TxCNT Reg.TxCNT Reg.
2211
0011
22
00
3322
11
TxPWM/TxCMPTxPWM/TxCMP(active high)(active high)
This example:This example:TxCON.3-2 = 01 (reload TxCMP when on underflow or period match)TxCON.3-2 = 01 (reload TxCMP when on underflow or period match)TxPR = 3TxPR = 3TxCMP = 1 (initially)TxCMP = 1 (initially)Prescale = 1Prescale = 1
TxCMP loadsTxCMP loadswith a 1with a 1
TxCMP loadsTxCMP loadswith a 2with a 2
TxCMP loadsTxCMP loadswith a 1with a 1
PWM ArchitecturePWM Architecture
CMPRxCMPRxcompare registercompare register
CMPRxCMPRxcompare registercompare register
CompareCompareReg. BufferReg. Buffer
CompareCompareReg. BufferReg. Buffer
CompareCompareLogicLogic
CompareCompareLogicLogic
16
sym.sym.asym.asym.
sym.sym.asym.asym.
OutputOutputLogicLogic
16
PWMy/PWMy/ CMPyCMPy
T1CNTT1CNT(GP Timer 1)(GP Timer 1)
auto-load on software selectable eventsauto-load on software selectable events
SVSVSVSV
DeadDeadBandBand
DeadDeadBandBandMUXMUXMUXMUX
Space VectorSpace Vector
Space VectorSpace Vector
VVaa VVbb VVcc
DTPH1DTPH1 DTPH2DTPH2 DTPH3DTPH3
DTPH1DTPH1 DTPH2DTPH2 DTPH3DTPH3
11
22
33 55
44 66
3-3-Phase Power ConverterPhase Power ConverterGNDGND
VVss
Only states of transistors 1, 3, & 5 need be determined since 2, 4, & 6 are their respective compliments
Switching State Notation: (Q5,Q3,Q1)Switching State Notation: (Q5,Q3,Q1) e.g. (0,0,1) means gate 1 is on, gates 3 & 5 are offe.g. (0,0,1) means gate 1 is on, gates 3 & 5 are off
Space VectorSpace Vector
Y-Connected Motor WindingsY-Connected Motor WindingsShowing Current FlowShowing Current Flow
((Q5,Q3,Q1) = (001) Q5,Q3,Q1) = (001) V Vaa=V=Vss , V , Vbb=V=Vcc= GND= GND
VVcc
60°60°
VVaa
VVbb
60°60°
ii
i/2i/2
i/2i/2
Voltage Drop VectorsVoltage Drop Vectors
yy
xx
22VVs s /3/3
VVs s /3/3
VVs s /3/3
VVs s /3/3
Space VectorSpace Vector
Basic Space Vectors w/ Switching PatternsBasic Space Vectors w/ Switching Patterns
UU180180 (110) (110)
UU300300 (101) (101)
UU00 (001) (001)
UU240240 (100) (100)
UU120120 (010) (010) UU6060 (011) (011)
O(000)O(000)O(111)O(111)
Space VectorSpace Vector Approximate desired voltage drop
vector as a linear combination of the basic space vectors
Coefficients are duration times
UU00 (001) (001)
UU6060 (011) (011)
UoutUout
TT11
TT22
Space VectorSpace Vector
DTPH1DTPH1
DTPH2DTPH2
DTPH3DTPH3
OO(111)(111)
UU00
(001)(001)UU6060
(011)(011)UU00
(001)(001)UU6060
(011)(011)
Full compare #1Full compare #1matchmatch
Full compare #2Full compare #2matchmatch
OO(111)(111)
GP Timer 1 valueGP Timer 1 value
TT11/2/2TT22/2/2
TTpp/2/2
T1PR matchT1PR match
PWM PWM
to motor phaseto motor phase
supply railsupply rail
Gate Signals areGate Signals areComplimentary PWMComplimentary PWM
Transistor gates turn on faster than they shut offTransistor gates turn on faster than they shut off Short circuit if both gates are on at same time!Short circuit if both gates are on at same time!
Asymmetric PWM ExampleAsymmetric PWM ExampleAsymmetric PWM ExampleAsymmetric PWM Example
PHxPHx
DTDT
dead timedead time
prescalerprescalerprescalerprescaler
CounterCounter8-bit8-bit
ENAENA
resetreset
CPUCLKCPUCLK(20 MHz)(20 MHz)
ComparatorComparatorComparatorComparator
4-4-bit periodbit period(DBTCON.11-8)(DBTCON.11-8)
4-4-bit periodbit period(DBTCON.11-8)(DBTCON.11-8)
DTPHDTPHxx
DTPHDTPHx_x_
PHPHxx
DTDT
edgeedgedetectdetect
edgeedgedetectdetect
ClockClock
DTPHDTPHxx
DTPHDTPHx_x_
A/D ConverterA/D ConverterC
h. 0
-7C
h. 0
-7
SampleSample& Hold& Hold
SampleSample& Hold& Hold
10 10 bit A/Dbit A/DConverterConverter
10 10 bit A/Dbit A/DConverterConverter
2-2-Level FIFOLevel FIFO
2-2-Level FIFOLevel FIFO
Inte
rnal
Dat
a B
us
Inte
rnal
Dat
a B
usVREFHIVREFHI
VREFLOVREFLO
ADCSOCADCSOC
ControlControl&&
ReferenceReferenceCircuitryCircuitry
8/18/1MUXMUX
VCCAVCCA
AGNDAGND5 5 voltsvolts
GNDGND
Event ManagerEvent ManagerSOC SignalSOC Signal
Q&A
Thanks