Copy of Mod 5 - Digital Techniques & Eis (Basic)

BASIC DIGITAL TECHNIQUES

Part 66 – C/028

AIRSERVICETRAINING(ENGINEERING)LIMITED

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AERONAUTICAL ENGINEERING TRAINING NOTES

These training notes have been issued to you on the understanding that they are intended for your guidance, to enable you to assimilate classroom and workshop lessons and for self-study. Although every care has been taken to ensure that the training notes are current at the time of issue, no amendments will be forwarded to you once your training course is completed. It must be emphasised that these training notes do not in any way constitute an authorised document for use in aircraft maintenance.

All Rights Reserved

The copyright in these technical training notes remain the physical and intellectual property of Air Service Training (Engineering) Ltd, (AST). Copying, storing in hard copy or electronic format, transmission to third parties and use for teaching by establishments other than AST is forbidden, except with the written permission of the AST General Manager.

M Haufe

Training Manager March 2006

© Air Service Training (Engineering) LimitedPart 66 – C/028 Basic Digital Techniques

CONTENTS PAGE

CHAPTER 1 : NUMBERING SYSTEMS

CHAPTER 2 : LOGIC CIRCUITS

SECTION 1 : 02.01.01

CHAPTER 2 : EXCLUSIVE OR, NANA & NORGATES

CHAPTER 3 : DATA CONVERSIONS

SECTION 1 : Basic Systems 03.01.01

SECTION 2 : Digital to Analogue Converter 03.02.01

SECTION 3 : Weighted Resistor DAC 03.03.01

SECTION 4 : R-2R Ladder DAC 03.04.01

SECTION 5 : Analogue to Digital Converter 03.05.01

SECTION 6 : Successive Approximation ADC 03.06.01

SECTION 7 : Fast Parallel ADC 03.07.01

CHAPTER 4 : DATA BUSES

CHAPTER 5 : COMPUTER ARCHITECTURE

SECTION 1 : THE BASIC SYSTEM 05.01.01

CHAPTER 6 : ELECTRONIC DISPLAYS

SECTION 1 : Advanced Screen Technology 06.01.01

SECTION 2 : Liquid Crystal Displays 06.02.01

SECTION 3 : Amorphous Transistors on Glass 06.03.01

SECTION 4 : The Electron Gun 06.04.01

SECTION 5 : The Light Emitting Diode (LED) 06.05.01

Issued April 2006 Contents 1

© Air Service Training (Engineering) LimitedBasic Digital Techniques Part 66 – C/028

CHAPTER 7 : FIBRE OPTICS

SECTION 1 : History 07.01.01

SECTION 2 : Optical Fibre Types 07.02.01

SECTION 3 : Optical Fibre Construction 07.03.01

SECTION 4 : Light Waves 07.04.01

SECTION 5 : Data Transmission 07.05.01

SECTION 6 : Advantages and Disadvantages

of Optical Fibres 07.06.01

SECTION 7 : Optical Fibre Terminations 07.07.01

CHAPTER 8 : ELECTROSTATIC SENSITIVE DEVICES

CHAPTER 9 : ELECTROMAGNETIC ENVIRONMENT

SECTION 1 : High Intensity Radiated Fields (HIRF) 09.01.01

SECTION 2 : Maintenance Procedures and HIRF Protection

09.02.01

SECTION 3 : Maintenance of Aircraft Structure Shielding 09.03.01

SECTION 4 : Equipment Maintenance 09.04.01

SECTION 5 : EMI (Electromagnetic Interference) 09.05.01

SECTION 6 : Electromagnetic Interferencefrom Portable Electronic Devices 09.06.01

CHAPTER 10 : SOFTWARE MANAGEMENT CONTROL

SECTION 1 : 10.01.01

CHAPTER 11 : ELECTRONIC INSTRUMENT SYSTEMS

SECTION 1 : EFIS 11.01.01

SECTION 2 : ECAM 11.02.01

SECTION 3 : EICAS 11.03.01

2 Contents Issued April 2006


CHAPTER 12 : TYPICAL ELECTRONIC/DIGITAL AIRCRAFT SYSTEMS

SECTION 1 : FMS 12.01.01

SECTION 2 : GPS 2.02.01

SECTION 3 : ACARS 12.03.01

SECTION 4 : Traffic Alert and Collision Avoidance System 12.04.01

SECTION 5 : Fly-by-Wire 12.05.01

SECTION 6 : Air Data Computer 12.06.01

Issued April 2006 Contents 3


4 Contents Issued April 2006


CHAPTER 1 : NUMBERING SYSTEMS

SECTION 1 : NUMBERS

INTRODUCTION

There are a wide variety of numbering formats used in electronics and computing.

The decimal, binary, octal, hexadecimal and binary coded decimals formats are covered in this section.

Conversions between these formats is also explained.

BASE

The number of digits used in any numbering system is known as it’s BASE or RADIX.

To identify the base of a number, a subscript of the base is used, however, when dealing purely in decimal or binary the base is often omitted.

610 base 10 decimal

1012 base 2 binary

2716 base 16 hexadecimal

6118 base 8 octal

Issued April 2006 Chapter 1 : Section 1 1


DECIMAL SYSTEM

The most common number system in everyday use is the DECIMAL or DENARY system, which uses 10 digits –

0 to 9

The value of each digit in a number depends on its position within the number.

Each digit in a decimal system represents a power of TEN.

Any number to the power of 0 is equal to 1.

Basepower 104 103 10 101 100 10-1 10-2

value 10000 1000 100 10 1 0.1 0.01

EXAMPLE:

‘six thousand, two hundred and fifty one’

BASEPOWER 103 102 101 100

VALUE 1000 100 10 1

NUMBER 6 2 5 1

This equates to

2 Chapter 1 : Section 1 Issued April 2006


BINARY SYSTEM

The binary number system is used extensively in electronics and computer systems and uses 2 digits –

0 and 1

The value of each digit (known as bits in binary), depends on its position within the number.

The right-most digit is called the Least Significant Bit (LSB).

The left-most digit is called the Most Significant Bit (MSB).

Each digit in a binary number system represents a power of TWO.

Basepower 24 23 22 21 20 2-1 2-2

decimal value 16 8 4 2 1 ½ ¼

Example:

101102

Basepower 24 23 22 21 20

decimal value 16 8 4 2 1

number 1 0 1 1 0

MSB LSB

If a ‘decimal’ point is not included in the number the LSB is always placed under 20 that has a value of 1.



Fig 1 shows the binary numbers under the appropriate column values with the corresponding decimal value.

23 22 21 20

8 4 2 1 Decimal Value

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

1 0 1 0 10

1 0 1 1 11

1 1 0 0 12

1 1 0 1 13

1 1 1 0 14

1 1 1 1 15

FIG 1



OCTAL SYSTEM

The octal system is used in electronics and some computer systems and uses 8 digits –

0 and 7

The value of each digit depends on its position within the number.

Each digit in an octal number system represents a power of EIGHT.

Basepower 83 82 81 80 8-1 8-2

Decimal value

512 64 8 1 1/81/64

Example: 1278

Basepower 82 81 80

decimal value 64 8 1

number 1 2 7

If a ‘decimal’ point is not included in the number the right most digit is always placed under 80 that has a value of 1.



Fig 2 shows the octal numbers under the appropriate column values with the corresponding decimal values.

82 81 80

64 8 1 Decimal value

0 0 0 0

0 0 1 1

0 0 2 2

0 0 3 3

0 0 4 4

0 0 5 5

0 0 6 6

0 0 7 7

0 1 0 8

0 1 1 9

0 1 2 10

0 1 3 11

0 1 4 12

0 1 5 13

0 1 6 14

0 1 7 15

0 2 0 16

: : : :

: : : :

0 7 7 63

1 0 0 64

1 0 1 65

FIG 2



HEXADECIMAL SYSTEM

The hexadecimal number system is extensively used in computer systems and uses 16 digits –

0 to 9

then the letters A to F are used to represent the numbers

10 to 15

The value of each digit depends on its position within the number.

Each digit in a hexadecimal number system represents a power of SIXTEEN.

basepower 162 161 160 16-1

decimal value 256 16 1 1/16

Example:

basepower 161 160

decimal 16 1

number 1 A

If a decimal point is not included in the number the right-most digit is always placed under 160 that has a value of 1.



Fig 3 shows the hexadecimal numbers under the appropriate column values with the corresponding decimal values.

162 161 160

256 16 1 Decimal value

0 0 0 0

0 0 1 1

0 0 2 2

0 0 3 3

0 0 4 4

0 0 5 5

0 0 6 6

0 0 7 7

0 0 8 8

0 0 9 9

0 0 A 10

0 0 B 11

0 0 C 12

0 0 D 13

0 0 E 14

0 0 F 15

0 1 0 16

0 1 1 17

0 1 2 18

: : : :

: : : :

0 F E 254

0 F F 255

1 0 0 256

1 0 1 257

1 8 2 258

FIG 3



SECTION 2 : NUMBER CONVERSIONS

INTRODUCTION

There are various methods to convert from one number format to another.

This section deals with conversions of decimal/binary/octal/hexadecimal formats.

DECIMAL TO BINARY CONVERSION

There are two methods described in this section and both produce the same result.

By Division

To convert a decimal number to binary requires the repeated division of the decimal number by 2, until the decimal number reduces to zero.

The remainders of each division is recorded and these remainders give the binary number when read upwards.

Example: 1910 to binary

2 19

2 9 remainder 1

2 4 remainder 1

2 2 remainder 0

2 1 remainder 0

0 remainder 1 Read upwards

1910 = 100112



By Subtraction

To convert the decimal number to binary requires the repeated subtraction of the decimal number, entering a 1 under the appropriate column value until the decimal number reaches zero.

Step 1 Write down the column value headings – up to but not exceeding the decimal number.

Step 2 Starting from the MSB, subtract the column value from the decimal number and enter a 1 under that column.

If subtracting a column value would produce a negative result, then enter a 0 under that column

Step 3 Continue until the decimal number reaches 0.

Example 9210 to binary

Step 1 64 32 16 8 4 2 1

1 0 1 1 1 0 0

Step 2

Step 3

92

-64

28

-16

12

-8

4

-4

64 was subtracted from 92 producing 28 – place a 1 under 64

32 could not be subtracted from 28 as this would produce a negative number – place a 0 under 32.

16 was subtracted from 28 producing 12 – place a 1 under 16.



2 subtracted would produce a negative – place a 0 under 2

1 subtraction would produce a negative – place a 0 under 1

The binary produced is in the correct order.

9210 = 10111002




Step 1 128 64 32 16 8 4 2 1

1 0 0 0 1 1 1 0

Step 2

Step 3

142

-128

14

-8

6

-4

2

-2

0

14210 = 100011102

Example 10010

Complete the following conversions

64 32 16 8 4 2 1

100

-64

36

1

10010 =



BINARY TO DECIMAL CONVERSION

Converting binary to decimal is the reverse of the subtraction method.

As in the decimal system where the number under each column was multiplied by the column value and added, the same applies to binary. However, as there are only zero or one, the process is simpler.

Step 1 Write down the column value headings corresponding to the amount of digits there is in the binary number.

Step 2 Enter the binary number under the headings with the LSB under value 1

Step 3 Add the column values that has a 1 under it

Example: 1101102 to decimal

Step 1 32 16 8 4 2 1

Step 2 1 1 0 1 1 0

Step 3 2

4

16

32

54

1101102 = 5410



Example: 111010112

Step 1 128 64 32 16 8 4 2 1

Step 2 1 1 1 0 1 0 1 1

Step 3 1

2

8

32

64

128

235

111010112

EXERCISE:

Complete the following conversion 10101102 to decimal

64 32 16 8 4 2 1

1 0 1 0 1 1 0

10101102



EXERCISE: 111101002 to decimal

128 64 32 16 8 4 2 1

111101002 =

EXERCISE 101002 to decimal

101002 =



BINARY TO OCTAL CONVERSION

To convert a binary number to an octal number, split the binary number into 3s and take each digit as the octal number.

Step 1 Split the binary number into 3s starting from the LSB.

Step 2 Convert each set of 3 binary bits into a decimal number which is the octal number.

Example 1110100102 to octal

4 2 1 4 2 1 4 2 1

1 1 1 0 1 0 0 1 0

7 2 2

111010010 = 7228

Example: 1101101010111 to octal

add 0’s to 001 101 101 010 111

make up to 3

1 5 5 2 7

11011010101112 = 155278

EXERCISE

Convert The following to octal

1011101101102

10102



BINARY TO HEXADECIMAL CONVERSION

To convert a binary number to a hexadecimal number, split the binary number into 4s and take each digit as the hexadecimal number.

Step 1 Split the binary number into 4s starting from the LSB

Step 2 Convert each set of 4 binary bits into a decimal number and then to the hexadecimal digit

Example: 1101001101002 to hexadecimal

Binary 8421 8421 8421

1101 0011 0100

‘Decimal’ 13 3 4

hexadecimal D 3 4

1101001101002 = D3416

Example 111111100

Add 0s

0001 1111 1100

1 15 12

1 F C

1111111002 = 1FC16

EXERCISE

Convert the following to hexadecimal:

1111000010102=

1011010102 =



OCTAL TO BINARY CONVERSION

To convert an octal number to a binary number requires each octal number to be SEPARATELY converted into a 3 bit binary number and the combination of binary bits makes the binary number.


4 1 3 2

100 001 011 010

41328 = 1000010110102

Example 318 to binary

Binary 011001

318 = 110012 (any 0 to the left can be ignored)

EXERCISE

Convert the following to binary

5278 =

1118 =

OCTAL TO HEX CONVERSION

Converting an octal number directly to hexadecimal and vice versa is extremely difficult and will not be covered in this section.



HEXADECIMAL TO BINARY CONVERSION

To convert a hexadecimal number to a binary number requires each hexadecimal number to be SEPARATELY converted into 4 bit binary numbers and the combination of binary bits mages the binary number.


Hex number 6 2 3

Value 8421 8421 8421

Binary number 0110 0010 0011

62316 = 110001000112

Example: 28B16 to binary

Hex number 2 8 B

Decimal number 2 8 11

Binary number 0010 1000 1011

28B16 = 10100010112

EXERCISE:

Convert the following to binary:

11116

AO916

ABC16



SECTION 3 : PRACTICAL SOLUTION TO CONVERSIONS

INTRODUCTION

Some of the conversions detailed can be complex, especially where large numbers are involved.

This section deals with a practical solution to converting between different formats.

By following simple procedures, the conversions are easily carried out regardless of the number size.

The bases of the procedure is to always convert a number format into binary then to the required number format.

Fig 1 shows the logic diagram for the conversions.

Decimal Binary Octal

Hexadecimal

The first procedure deals with decimal/binary/octal conversions.

The second procedure deals with decimal/binary/hex conversions.

The third procedure deals with octal/binary/hex conversions.

DECIMAL/BINARY/OCTAL CONVERSIONS

To demonstrate the conversion, the examples will convert from –

Decimal Binary Octal Binary Decimal

Example:

Convert 7210 to binary then octal and back to decimal.

Decimal to binary:

72

-64 8-80

64 32 16 8 4 2 1

1 0 0 1 0 0 0

7210 = 10010002

Binary to octal (split into 3s)



421 421 421

001 001 000

1 1 0

10010002 = 1108

Octal to Binary

1 1 0

421 421 421

001 001 000

1108 = 10010002

Binary to Decimal

64 32 16 8 4 2 1

1 0 0 1 0 0 0 =8

6472

10010002 = 7210



Example 2 30010

Decimal to binary

300

-256 44-3212-84-40

256 128 64 32 16 8 4 2 1

1 0 0 1 0 1 1 0 0

30010 = 1001011002

Binary to octal

421 421 421

100 101 100

4 5 4

1001011002 = 4548

Octal to Binary

4 5 4

421 421 421

100 101 100

4548 = 1001011002

Binary to Decimal

256 128 64 32 16 8 4 2 1

1 0 0 1 0 1 1 0 0 4

8

32

256300

1001011002 = 30010



DECIMAL/BINARY/HEXADECIMAL CONVERSIONS

The examples convert from:

Decimal Binary Hexadecimal Binary Decimal

The only difference is to split the binary into 4s where octal was into 3s.

Example:

Convert 31010 to binary then hexadecimal and back to decimal.

Decimal to Binary

310

-25654-3222-166-42-20

256 128 64 32 16 8 4 2 1

1 0 0 1 1 0 1 1 0

31010 = 1001101102

Binary to Hexadecimal (split into 4s)

8421 8421 8421

0001 0011 0110

1 3 6

1001101102 = 13616



Hexadecimal to Binary

1 3 6

8421 8421 8421

0001 0011 0110

13616 = 100110110

Binary to Decimal

256 128 64 32 16 8 4 2 1

1 0 0 1 1 0 1 1 0 2

2

16

32

256

310

1001101102 = 31010



OCTAL/BINARY/HEXADECIMAL CONVERSION

The conversion of octal and hexadecimal to and from binary have already been demonstrated and are shown here for completeness.

Example:

Convert 3678 binary then hexadecimal and back to octal.

OCTAL TO BINARY

3 6 7

421 421 421

011 110 111

3678 = 111101112

Binary to Hexadecimal

8421 8421

1111 0111

15 7

F 7

111101112 = F716

Hexadecimal to Binary

F 7

15 7

8421 8421

1111 0111

F716 = 111101112

BINARY TO OCTAL

011 110 111

421 421 421

3 6 7

111101112 = 3678



CHAPTER 2 : LOGIC CIRCUITSSECTION 1

INTRODUCTION

In the previous section we have learnt about the binary number system because this is the only system which a digital computer can use. In this section we are going to see how logic circuits are used to direct binary information, in the form of voltage levels and pulses, to various locations in the digital system as a whole.

It is not necessary to know the exact circuit configuration of any particular device, but only to understand the function of the device in terms of input and output.

BOOLEAN ALGEBRA

The circuit designer begins with a series of statements that the circuit is required to perform and implements these statements in a logic circuit system. His task is to develop a logic system which will perform the required function with the minimum of devices at the minimum cost. The user of the system has other concerns because for him the circuit is already designed and he must be able to interpret the circuit operation from the diagrams supplied. Therefore, he must be able to understand the function of the various logic devices to determine the scheme of operation. One can therefore see the importance for a technician to be familiar with the basic principles of Boolean algebra.

There are only three basic logic operations required in digital electronics. To produce these operations, even the most complex logic circuits can be broken down into basic building blocks or GATES. This will be the starting point. We will then go on to see how these gates can be used to perform logic functions.



GATES : GENERAL POINTS

Before proceeding into the development of logic gate symbols it should be noted that a variety of logic diagrams and symbols have been used in the past but now only two principle ones are widely used. These are:-

1. British Standard (BS) 3939 Section 21 (1969)

2. Military and American Standards (MS) 806B

Of these two types of symbol, the American one is more usually used in aircraft systems.

Gates may be constructed from a wide variety of electronic components including transistors which are especially designed for switching applications. Remember the whole operation of a digital computer relies upon the binary number system, ie. 1 or 0, which means ON or OFF; just like a switch.

LOGIC LEVEL REPRESENTATIVE

When performing logical operations using Boolean algebra, each variable can assume either a TRUE or FALSE value, and these values are represented by a 1 or 0 respectively. When electronic switches are used to perform a logic operation it becomes necessary to assign two discrete voltage levels that will correspond to the binary digits of 1 and 0. In a logic system where the dc supply voltage is, for example, +5 V then two choices for the voltage levels are available to represent the binary states of 1 or 0. These are shown in the diagrams below illustrating the two possible logic level representations.

FIG 1 LOGIC LEVEL REPRESENTATIONS



It can be seen that positive logic stipulates that the voltage level assigned to the active state 1 is more POSITIVE than the level assigned to the inactive state 0. Of course, it can be seen that negative logic is the opposite, for example, the voltage level assigned to the active state is more NEGATIVE than the level assigned to the inactive state 0.

The ‘positive logic’ representation is favoured by the majority of computer designers and manufacturers.

BASIC LOGIC GATES

The word gate suggests some kind of forceful control and logic gates are the basic elements which actively route the flow of digital information through the logic circuits. In a logic circuit, groups of gates working together are able to send particular bits of information to specified locations. As already stated, only three basic gates are required to perform all digital operations. These are the AND, OR and NOT gates, although two others, the NAND and NOR gates are often favoured now because they are easily fabricated in integrated circuit form and can perform all the basic gate functions. How the NAND and NOR gates are connected together to produce the basic gates we shall discover in due course. We shall now look at each gate in turn, how each one is represented symbolically, and the way they are written in Boolean algebra form. We are looking at what the output of the gate is in terms of various combinations of input signals, as Os and 1s, in tabular form in, what are called, TRUTH TABLES.

The AND Gate

An AND gate can, in theory, be said to consist of only two or more switches connected in series. Fig 2 shows the symbol that represents a two input AND gate which, as can be seen, can be produced by two switches A and B in series.

FIG 2 THE AND GATE



This gate will only adopt a 1 state at its output terminal when both the inputs A and B are also at the 1 state. As far as the circuit is concerned, this will be the case when both switches are CLOSED simultaneously. If we consider the output as f, then the AND gate Boolean expression is given by:-

It should be noted that the dot between the two inputs and is the way shown in Boolean algebra form that the inputs are being ANDed together. ALWAYS say and where you see it written as .

The Truth Table for the AND gate is shown in Table 1:-

0 0 0

0 1 0

1 0 0

1 1 1

TABLE 1. AND GATE TRUTH TABLE

As we proceed further the truth tables will, in some cases, become quite complex especially when more than two inputs are used. In all cases it is important that you write down all the possible combinations of the inputs to obtain all the possible outputs. You can work out how many outputs are possible by realising that it is given by , where x is the number of inputs, ie. in our case . If there are three outputs then the number of outputs is given by , ie. 8. It can immediately be seen that there is a relatively big jump in the number of outputs in this case. The easiest way to make sure all possible inputs are considered is to determine first the number of outputs. Then, starting at decimal 0, write down one line below the next in the table under the input columns, the binary equivalent numbers consecutively up to the number of outputs required. Let us consider a 3 input AND gate,



There are 8 possible outputs. Therefore, we must write down the binary equivalents of decimal 0 to 7 as shown in the truth table (Table 2).

DECIMAL

0 0 0 0 0

1 0 0 1 0

2 0 1 0 0

3 0 1 1 0

4 1 0 0 0

5 1 0 1 0

6 1 1 0 0

7 1 1 1 1

TABLE 2

Because this is an AND gate, the only state 1 output possible is when all inputs are at state 1.

The OR Gate

The figure below shows the symbol that represents a 2 input OR gate together with the electrical switching circuit by which the function f can be realised.

FIG 3 THE OR GATE

The gate will adopt a 1 state at its output terminal when either input or or both are at the state 1. In Boolean form the function is written as:-

As with the AND gate function, the + sign between and does not mean plus as in ordinary algebra but OR . This function can be realised by connecting two switches representing the inputs, in parallel. Because this gate also performs the AND function when both inputs are at 1 state, it is often referred to as an INCLUSIVE



OR gate. We shall need to have an OR gate which will not perform the AND function at all and that gate is called the EXCLUSIVE OR gate.

The truth table shown in Table 3 is that for a 2 input OR gate:-

0 0 0

0 1 1

1 0 1

1 1 1

TABLE 3 TRUTH TABLE FOR 2 INPUT OR GATE

The NOT Gate

Fig 4 shows the symbol for a NOT gate which is in fact the normal amplifier symbol with a small circle included at its output.

FIG 4 THE NOT GATE

It can be seen that the NOT gate has one input A and one output which is the inverse of the input. This function in Boolean algebra form is:-



Since there is only one input the number of outputs possible is and the NOT gate truth table is shown in Table 4:-

0 1

1 0

TABLE 4 TRUTH TABLE FOR NOT GATE

GATE COMBINATIONS

There are two ways in which we can learn these combinations. Firstly, we can start with the logic circuit and find the output. Secondly, we can draw the logic circuit for a given Boolean expression. In the former type of problem it is usual to write down the output of each gate in turn until the output is reached and then write down the truth table for the circuit. Here are a couple of examples:-

Example - Find the Boolean expression output for the following logic circuit and compile the truth table for the circuit.

FIG 5

Answer – Write down the output of NOT gate for input, ie. , then AND this to input to give . To obtain the truth table write the first 2 columns for possible values of and , then write in the next column and finally AND together the columns and . This gives:

0 0 1 0

0 1 1 1

1 0 0 0

1 1 0 0

Example – Find the Boolean expression output for the following circuit and compile the truth table for the circuit.



FIG 6

Answer – It can clearly be seen that the OR operation for inputs and must be performed first giving as output of the OR gate. This output is then combined with the other input as inputs to an AND gate. This gives the circuit output as

. The truth table is given below.

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 1 0

1 0 0 0 0

1 0 1 1 1

1 1 0 1 1

1 1 1 1 1

The second type of gate combination problem is where a logic circuit has to be drawn for a given logic expression. Here is an example:-

Example – Draw the logic circuit diagram which will perform the operation .

Answer – The first thing to note is that there are 2 inputs and . The second thing to note is that 4 gates are required, ie. 1 OR gate, 2 AND gates and 1 NOT gate. Now proceed as follows. Put the two inputs into an AND gate and the output into a NOT gate: this gives . Put the two inputs into an OR gate giving as its output. Combine this output with the output of the NOT gate to form the two inputs to an AND gate.

The circuit to perform the function is then shown below:-



FIG 7

It must be pointed out at this stage that there may be several combinations of logic gates which will perform a particular function. In this case it is often necessary to analyse the problem so that the least number of gates need to be used. Several methods have been developed to obtain the most simple Boolean expression for a given combination of inputs to perform a function.



NOTES:



SECTION 2 : EXCLUSIVE-OR, NAND & NOR GATES

INTRODUCTION

In this chapter we shall continue the discussion on combinational gates; in particular, NAND and NOR gates which are used extensively these days in logic circuit work, incorporating integrated circuits.

Before we go to the NAND and NOR gates let us look at the EXCLUSIVE-OR gate (EX-OR) which you will recall prevents ambiguity between AND and OR gates when all inputs are logic 1. Since the nature of the AND gate must be that the output can only be logic 1 when ALL inputs are logic 1 the EX-OR gate has got to be one in which the output is 0 when ALL inputs are logic 1. Although this might appear to be a simple operation, 5 basic gates are required to produce a logic circuit which gives the required truth table!

EXCLUSIVE-OR GATE

The truth table required for an EX-OR gate is shown below:-

Required output

0 0 0

0 1 1

1 0 1

1 1 0

The logic circuit which will produce this output is shown below in Fig 1:-

FIG 1 EX-OR GATE

Consider the output of this circuit. It is the function:-



We now draw up the full truth table for this function as shown below:-

1 2 3 4 5 6 7

0 0 1 1 0 0 0

0 1 1 0 1 0 1

1 0 0 1 0 1 1

1 1 0 0 0 0 0

It should be noted that each of the entries in columns 3 and 4 are NOT values of entries in columns 1 and 2. Entries in column 5 are obtained by ANDing together the entries in columns 1 and 4. The final column is obtained by ORing the entries in columns 5 and 6.

Since the column 7 entries compare with those of the required EX-OR gate truth table, the logic circuit does indeed represent an EX-OR gate.

In order to obviate drawing the 5 basic gates required to perform the EX-OR function, the symbol shown below is used. (Fig 2)

FIG 2

Since the output of the EX-OR gate is different to the basic OR gate we must use a different Boolean algebra expression which is shown below for a 2 input EX-OR gate:-



If you can remember that the function for the EX-OR gate is and knowing that and can only have the values of 1 or 0, the four outputs for the four possible inputs can be found directly without remembering the truth table. Suppose for instance then of course and putting the appropriate values into the expression for the EX-OR gate we get:-

(2 AND and 1 OR gates)

ie.

(OR gate)

Other results are different when inputs are , and , etc. You should find that the results do agree with the truth table.

NEGATED LOGIC ELEMENTS

In the modern field of electrical logic element construction, the semiconductor components have taken over exclusively as the principle form of design for such devices. Some logic elements are still assembled using discrete components, but most present-day devices are manufactured using integrated circuit (IC) techniques. All IC circuits make use of diodes and transistors to carry out the switching operations within the device (0 to 1 or 1 to 0) and are ideal for logic operations. It is obvious that diodes can be used to act as switches but they are not perfect and allowance has to be made for the voltage loss that occurs with each device. Because of this, the voltage levels representing the logic states (0 to 1) may eventually be lost unless some form of replacing the lost voltage is performed at each operation. Transistors, on the other hand, do not suffer from such losses and in addition they have the advantage that they provide power amplification to drive a number of similar elements. Therefore, transistors are preferred to diodes in logic switching circuits. However, when the transistor is used in this way, its amplified output is the inverse of the input and therefore represents the inverse of the logic operation. It behaves therefore as a NEGATING LOGIC ELEMENT. Far from being a disadvantage, it will be seen that such elements have a distinct advantage over non-inverting forms of logic elements.



The NAND gate

If the output of an AND gate is applied directly to a NOT gate the latter inverts all of the outputs of the AND gate, ie. it changes all output logic 1s to logic 0s and vice versa. The logic circuit shown below in Fig 3 will perform this function.

FIG 3

Since this is a combination of a NOT and AND gate it is called a NAND or negated AND gate. The combination is shown symbolically below in Fig 4.

FIG 4

In practice, the basic NAND gate consists of 2 transistors used as switches which are ON and OFF dependent upon the logic states of the inputs applied to each transistor. When both are ON the overall circuit output is logic 0 but for all other inputs the output is logic 1.

The Boolean expression for a NAND gate is:-



The truth table for a NAND gate is shown below and it can be seen that in each case the output for a given input combination is the inverse of the AND gate.

0 0 1

0 1 1

1 0 1

1 1 0

The NOR Gate

As you may have anticipated the NOR gate is a combination of the basic OR gate the output being connected directly to a basic NOT gate. Once again the NOT gate inverts all the outputs normally obtained from an OR gate. It is shown in logic circuit form in Fig 5.

FIG 5

Since this is a combination of a NOT and an OR gate it is called a NOR or negated OR gate. The combination is shown symbolically in Fig 6.

FIG 6



The truth table for a NOT gate is shown and it can be seen that in each case the output for given input combination is the inverse of the OR gate.

0 0 1

0 1 0

1 0 0

1 1 0

The Boolean expression for the NOR gate is:-

BRITISH STANDARD SYMBOLS

As for the basic gates, the British Standards symbols for EX-OR, NAND and NOR gates are of uniform shape, in Fig 7.

FIG 7



LOGIC ELEMENTS CONSISTING OF NAND GATES ONLY

NOT Gate

Consider taking a NAND gate and joining its two inputs together and applying one input to it, as shown in Fig 8.

FIG 8

The output will be given by since both inputs are and therefore have the same value 0 or 1. Since we know that then , thus the output is given by which is equivalent to a NOT gate.

AND Gate

Consider a logic circuit in which the two inputs are connected to a NAND gate and the output is applied to another NAND gate formed into a NOT gate, ie. its input terminals joined together. (Fig 9)

FIG 9

It can be seen that the two inputs have been ANDed together using 2 NAND gates.



OR Gate

The NOT and AND gates are fairly easily drawn in NAND gate form. The OR gate formation of NAND gates is rather more complicated. Fig 10 shows what it looks like.

FIG 10

By DE-MORGAN’S rules the output function becomes and since two NOT gates cancel each other, this becomes , ie. an OR gate.

LOGIC ELEMENTS CONSISTING OF NOR GATES ONLY

NOT Gate

This is identical to the modification made up to the NAND gate, ie. the 2 inputs are joined and the input A applied to it as shown in Fig 11.

FIG 11

The output is given by the function and since we know then must equal . This is of course the NOT of the input, ie. the NOR gate connected this way represents a basic NOT GATE.



OR Gate

Consider a logic circuit in which the two inputs are connected to a NOR gate and the output is applied to another NOR gate formed into a NOT gate as shown in Fig 11. Fig 12 shows this logic circuit together with the outputs of each gate.

FIG 12

It can be seen the double NOT function gives the output which is an OR gate.

AND Gate

As you might have guessed, this is the more difficult basic gate to represent by NOR gates only. However, it does follow the same pattern as the NAND gate representation of the OR gate. The logic circuit of an AND gate using NOR gates only is shown in Fig 13.

FIG 13

By using DE-MORGAN’S rules the output function becomes and this becomes after cancelling NOT – NOT gates, ie. the AND gate.


© Air Service Training (Engineering) LimitedBasic Turbine Engines Part 66 – C/028

CONVERSION OF AND-OR LOGIC FUNCTIONS TO NAND LOGIC

The EX-OR gate is a typical AND-OR logic function because its Boolean form is ie. AND gates ORed together. This form of function is easily

transformed into its equivalent NAND gate-only logic circuit. At first sight it might appear that extra gates are required in this conversion but as we shall see some gates become redundant and in fact only the same number of NAND gates is required.

FIG 14

FIG 15

Now we will replace all the OR, AND and NOT gates with their NAND equivalents and thus obtain the logic circuit shown in Fig 15.

It can be seen that NAND gates 1 and 2 form a NOT-NOT combination and they are redundant and can be omitted from the circuit without affecting the operation.



Exactly the same consideration applies to NAND gates 3 and 4 and therefore they can be omitted also.

It can be seen therefore, that 5 NAND gates wired up correctly will perform the function the basic circuit requires 2 NOT gates, 2 AND gates and 1 OR gate.

CONVERSION OF OR-AND LOGIC FUNCTIONS TO NOR LOGIC

A typical OR-AND function is which we shall now generate using NOR gates only. The function is first drawn using basic gates as shown in Fig 16.

FIG 16

Replacing OR 1, OR 2 and AND gates by their NOR equivalent gates gives the logic circuit shown in Fig 17.

FIG 17

After eliminating the redundant gates it can be seen that once again the same number of NAND gates is required to perform this function.



It should be noted that there are not always redundant gates after conversions have been made and this may result in having to use more NAND or NOR gates. However, this is preferred since, if all the gates are the same, fabrication is much easier in IC form.

Typical logic circuits found in aircraft:

FIG 18



FIG 19



FIG 20 SUMMARY OF BOOLEAN FUNCTIONS AND LOGIC GATES



SUMMARY

The following topics have been covered in this chapter:-

EXCLUSIVE-OR gate

NAND gate

NOR gate

British Standard EX-OR, NAND and NOR gates

Logic elements consisting of NAND gates only

Logic elements consisting of NOR gates only

Conversion of AND-OR functions to NAND gate logic

Conversion of OR-AND functions to NOR gate logic



NOTES:



CHAPTER 3 : DATA CONVERSIONSSECTION 1 : BASIC SYSTEMS

INTRODUCTION

Many systems in aircraft produce analogue signals for sensing and indicating such parameters as pitch, rolls, pressure, temperature etc. These analogue signals are often required to be processed by digital computing systems.

CONVERTER TYPES

Before a digital processor can accept information from the ‘outside world’, the information must be converted from its analogue state into a digital format.

A converter which accomplishes this task is called an ANALOGUE TO DIGITAL CONVERTER (ADC).

Once the information has been converted, it can be used by the digital processor.

It is often necessary to convert the digital data output of the digital processor into analogue form.

This is accomplished by using a DIGITAL TO ANALOGUE CONVERTER (DAC).

ADCs and DACs are essential to INTERFACE digital processors with analogue systems.

Fig 1 shows a basic system

FIG 1

It converts a pressure transducer analogue signal to digital which is processed in a digital processor.

The processor passes this data to a second processor which then output the digital information to an ADC.

The ADC converts the digital format into an analogue signal to indicate the pressure being measured.

Many analogue to digital converters use DACs as part of the conversion process.



NOTES:



SECTION 2 : DIGITAL TO ANALOGUE CONVERTER

INTRODUCTION

A digital to analogue conversion is the process of taking a value represented by a digital code and converting it to a voltage or current which is PROPORTIONAL to the digital value.

DAC PRINCIPLE

Fig 1 shows a 4 bit Digital to Analogue Converter

FIG 1

The digital inputs to A, B, C and D are usually derived from the output register of a digital processor.

4 bits produces 16 different binary numbers from 0000 to 1111 (0 to 15).

For each input number, the DAC produces a different analogue output voltage. The actual output voltage is proportional to the supply voltage, the binary number and any amplification applied to the output.

Each digital input is WEIGHTED according to its position in the binary number. Each bit value is double the previous bit value from the LSB.

4 BIT DAC PRINCIPLE

When all the input bits are at logic zero (0000), the output is zero volts.

With the Least Significant Bit (LSB) at a logic 1 (0001), the output is 0.25 volts.

This is known as the QUANTISATION INTERVAL and is the amount of voltage between each increment of the binary input.

Each increase of binary input increases the output voltage by 0.25 volts to a maximum of

15 0.25 = 3.75 volts



Fig 2 shows the output voltages for different binary inputs.

D C B A Output Voltage

0 0 0 0 0

0 0 0 1 0.25

0 0 1 0 0.50

0 0 1 1 0.75

0 1 0 0 1.00

0 1 0 1 1.25

0 1 1 0 1.50

0 1 1 1 1.75

1 0 0 0 2.00

1 0 0 1 2.25

1 0 1 0 2.50

1 0 1 1 2.75

1 1 0 0 3.00

1 1 0 1 3.25

1 1 1 0 3.50

1 1 1 1 3.75

FIG 2

It can be seen from Fig 2 that the weighting of the inputs are:

A = 0.25 volts

B = 0.50 volts

C = 1.00 volts

D = 2.00 volts

Any combination of binary is the addition of the weighted voltages.

or

the LSB value multiplied by the equivalent binary number.



Example

Binary = 1 1 0 1

Total Weighted Voltage = 2 + 1 + 0 + 0.25 = 3.25 volts

Example

Binary = 1 0 0 1

Total Weighted Voltage = 2 + 0 + 0 + 0.25 = 2.25 volts

Example

Binary = 1 1 0 1 = 13

Quantisation Interval (LSB) = 0.25

Output Voltage = 3.25 volts (13 0.25)

If the value of the LSB is changed to 0.1 volts, the output voltages would be as at Fig 3.

D C B A Output Voltage

0 0 0 0 0

0 0 0 1 0.1

0 0 1 0 0.2

0 0 1 1 0.3

0 1 0 0 0.4

0 1 0 1 0.5

0 1 1 0 0.6

0 1 1 1 0.7

1 0 0 0 0.8

1 0 0 1 0.9

1 0 1 0 1.0

1 0 1 1 1.1

1 1 0 0 1.2

1 1 0 1 1.3

1 1 1 0 1.4

1 1 1 1 1.5

FIG 3



The analogue voltage output of a DAC with more than 4 bits can be calculated as previously explained.

Example

8 bit DAC, LSB = 0.05 volts, input 10010010

Binary = 1 0 0 1 0 0 1 0

6.4 + 0 + 0 + 0.8 + 0 + 0 + 0.1 + 0 = 7.3 volts

or

Binary = 10010010 = 146

Output = 146 0.05 = 7.3 volts

QUANTISATION INTERVAL/LEVEL

The QUANTISATION INTERVAL is the maximum analogue voltage divided by the maximum digital binary input.

Example 4 bit DAC

Max output voltage = 4.5 volts

Max binary count = 15

Quantisation Interval = 4.5 15 = 0.3 volts

The quantisation interval is the value of the LSB.

Each analogue voltage level for different binary inputs is known as the QUANTISATION LEVEL.



Fig 4 shows an example of the quantisation levels for a 4 bit DAC

FIG 4

Two important factors of the converted voltages are accuracy and resolution.

ACCURACY

ACCURACY indicates how close the actual output value is to the predicted output value.

ExampleAn accuracy of 1%

Predicted Voltage = 10 volts

Actual voltage can be between 9.9 and 10.1 volts.

RESOLUTION

RESOLUTION is the smallest increment of voltage or current which can be obtained from a DAC. Its value depends on the LSB.

It may be expressed as a percentage of the full scale output of the DAC.

Resolution = step size 100full scale



Example

5 bit DAC = 31 max count

LSB = 0.5 volts

full scale = 15.5 volts

% resolution = 0.5 100 15.5

= 3.2%

SETTLING TIME

SETTLING TIME is the time taken for the output of a DAC to settle to a new value in response to a change of digital input.

The time is when the new value is within half the LSB value.



SECTION 3 : WEIGHTED RESISTOR DAC

INTRODUCTION

This device works on the principle of CURRENT division through input resistors. An Op Amp then converts the current totals to an output voltage proportional to the input current and the gain of the circuit.

CIRCUIT LAYOUT

Fig 1 shows a typical 4 bit weighted resistor DAC

FIG 1

Inputs to A, B, C and D will either be zero for logic 0 or 5 volts for logic 1.

The resistors DOUBLE in size from the MSB.

The Op Amp feedback resistor, in this example, is the same value as the MSB resistor.



WEIGHTED RESISTOR DAC ACTION

Fig 2 shows a 4 bit weighted resistor DAC with a binary counter providing the digital input.

FIG 2

With the counter reset, the digital input to the resistors is 0000, therefore no current flows in any of the resistors.

The DAC output = 0 volts

When the counter increases its count to 0001, 5 volts is applied to the 10K resistor.

The current produced is 5 = 0.5mA 10K

When the counter increases its count to 0010, 5 volts is applied to the 5K resistor.

The current produced is 5 = 1mA5K

When the counter increases its count to 0011, 5 volts is applied to the 10K and 5K resistors.

The current produced is 0.5mA + 1mA = 1.5mA

Each increase in count, increases the current by 0.5mA.

In Fig 2, the circuit feedback resistor is 1.25K. The current through the feedback resistor equalises with the input currents when the correct output level is reached.



so

Example

Using values from Fig 2 with the binary count at maximum (1111).

As long as the feedback resistor is the same as the MSB resistors values, the following calculation can be used.

Example

Binary = 0110 (6)

ADVANTAGE OF WEIGHTED RESISTOR DAC

The weighted resistor network provides the simplest and most DIRECT METHOD of DAC.



DISADVANTAGE OF WEIGHTED RESISTOR DAC

The main disadvantage of the weighted resistor DAC is the large range of resistors that are required.

If a 12 bit DAC was required the ratio of resistor values would be 2048:1, about 20M to 10K.

This means that the MSB resistor must be of close tolerance otherwise large errors would be induced into the circuit.

Fig 3 shows an 8 bit weighted resistor DAC with resistor values from R to 128R.

FIG 3

A common method to overcome the problems, associated with using a large range of resistor values, is to use an R-2R resistor network instead



SECTION 4 : R-2R RESISTOR DAC

INTRODUCTION

The R-2R Ladder DAC uses the super position theorem, where the equivalent resistor values are dependent upon whether 0 volts or 5 volts is applied to an input, to determine parallel and series resistor values.

The R-2R Ladder DAC works on the principle of VOLTAGE division through parallel and series paths.

CIRCUIT LAYOUT

Fig 1 shows a typical 4 Bit R-2R Ladder DAC as the input to a unity gain Op Amp.

FIG 1

The binary counter outputs either 0 volts for logic 0 or 5 volts for logic 1.

An open circuit cannot be used as an input as the resistors would be taken out of circuit.



R-2R LADDER DAC ACTION

Fig 2 shows an R-2R Ladder DAC with resistor values of 10K and 20K, and a unity gain Op Amp.

FIG 2

R = 10K

2R = 20K

gain of Op Amp = 1

With the binary counter reset, the digital input to the resistors is 0000, therefore no current flows in the circuit.

The DAC output = 0 volts

When the counter increases until it outputs 1000, 5 volts is applied to the circuit from D (MSB).

A, B and C are at zero volts.

Due to the resistor network values, the voltage produced at the Op Amp input is

⅓ of 5 volts = = 1.67 volts

If the counter now reads 0100, 5 volts is applied to the circuit from C.

A, B and D are at zero volts



Due to the resistor network values the voltage produced at the Op Amp input is

5 volts = 0.83 volts

If both C and D are at 5 volts and A and B at zero volts (1100) the voltage produced is the addition of the voltages at each NODE.

2.5 volts

5 volts at B is half that of C

5 volts at A is half that of B

D C B A

volts

Example

Binary count is 1111 (maximum 15)

The output voltage is calculated as

D C B A

+ + + = 31/8 = 3.125 volts

Example

Binary count is 0110 (6)

D C B A

0 + + + 0 = 11/4 = 1.25 volts

DAC INPUT DATA

Other devices such as switches, registers or digital processors can be used to provide the digital data into a DAC.

The examples shown used a binary counter as it can produce all the possible combinations of binary bits.

Using parallel or serial inputs to a DAC normally requires control of when the data is input to and when the output is to be ‘read’ from the DAC.

NOTES:



SECTION 5 : ANALOGUE TO DIGITAL CONVERTER

INTRODUCTION

An Analogue to Digital conversion is the process of sampling an analogue input voltage and producing a digital equivalent as an output.

ADC PRINCIPLES

Sample values of analogue signal are taken and related to a binary value over a period of time.

If the sample rate is too low, the analogue information may alter significantly between the sampling, losing information.

If the sample rate is too high, there is less time between samples to process the information.

The samples measured from the analogue signal are not always identical to the analogue level. If a large step size or quantisation interval is used, the analogue signal can vary significantly without any change of digital data.



NOTES:



SECTION 6 : SUCCESSIVE APPROXIMATION ADC

INTRODUCTION

It is often the case that an ADCs analogue input varies widely from one conversion to the next eg. the larger the analogue voltage the longer it takes to convert the voltage to digital. The successive approximation ADC ‘tests’ the input voltage at half the maximum voltage to determine if it is above or below the test value. It then halves this range to see if it is above or below the test value. Repeated halving produces the required output. The SAC has a FIXED CONVERSION PERIOD, dependent upon the amount of bits required.

CIRCUIT LAYOUT

Fig 1 shows the layout of a Successive Approximation ADC.

FIG 1

The binary counter produces a serial binary count to the encoder and logic unit.

The encoder and logic unit, and additional circuitry not shown, outputs a trial number.

The trial number register produces ones or zeros as the digital input to the DAC.

The DAC produces an analogue voltage proportional to the digital input.

The comparator compares the DAC input with the analogue input and produces either a logic 1 or logic 0.



SUCCESSIVE APPROXIMATION ADC PRINCIPLE

With the binary counter initially reset to zero, the MSB is being processed in the encoder and logic register.

The MSB is set to a logic 1, whilst the other 7 bits are at logic 0. The MSB is approximately half the maximum value.

The digital data is input to the DAC and converted to a proportional analogue voltage which is half the maximum range of the input voltage.

If the analogue input voltage is GREATER THAN the DAC analogue voltage, then the comparator outputs a logic 1 to SET the encoder and logic control bit 0 to a logic 1.

If the analogue input voltage is LESS THAN the DAC analogue voltage, then the comparator outputs a logic 0 to RESET the encoder and logic register bit 0 to a logic 0.

The binary counter increments to process bit 1 of the encoder and logic register.

The same action is repeated by comparing the input voltage with the DAC produced voltage to either set or reset the appropriate bits in the encoder and logic register.

After all the bits have been processed, in this example, 8 times, the DAC output should equal the input voltage. The digital output now represents the analogue input voltage.



SUCCESSIVE APPROXIMATION ADC ACTION

Example Analogue input voltage is ZERO VOLTS

Step size (LSB) into DAC is 10mV

Max output of DAC is 255 10 mV = 2.55V

Binary counter initially at 000.

Fig 2 shows the processing of the circuit.

Binary Counter

D C B A

Encoder and Logic Register

7 6 5 4 3 2 1 0

DAC O/P

Voltage (V)

Comparator Output

0 0 0 0 1 0 0 0 0 0 0 0 1.28 0 START

0 0 0 1 0 1 0 0 0 0 0 0 0.64 0

0 0 1 0 0 0 1 0 0 0 0 0 0.32 0

0 0 1 1 0 0 0 1 0 0 0 0 0.16 0

0 1 0 0 0 0 0 0 1 0 0 0 0.08 0

0 1 0 1 0 0 0 0 0 1 0 0 0.04 0

0 1 1 0 0 0 0 0 0 0 1 0 0.02 0

0 1 1 1 0 0 0 0 0 0 0 1 0.01 0

1 0 0 0 0 0 0 0 0 0 0 0 0.00 0 STOP

FIG 2

The digital output is 00000000 for 0 volts in.



Example analogue input voltage is maximum 2.55 volts


Binary Counter

D C B A


7 6 5 4 3 2 1 0

DAC O/P

Voltage (V)

Comparator Output

0 0 0 0 1 0 0 0 0 0 0 0 1 28 1 START

0 0 0 1 1 1 0 0 0 0 0 0 1.92 1

0 0 1 0 1 1 1 0 0 0 0 0 2.24 1

0 0 1 1 1 1 1 1 0 0 0 0 2.40 1

0 1 0 0 1 1 1 1 1 0 0 0 2.48 1

0 1 0 1 1 1 1 1 1 1 0 0 2.52 1

0 1 1 0 1 1 1 1 1 1 1 0 2.54 1

0 1 1 1 1 1 1 1 1 1 1 1 2.55 1

1 0 0 0 1 1 1 1 1 1 1 1 1.55 STOP

FIG 3

The digital output is 11111111 for 2.55 volts in.



Example Analogue input voltage is 2.34 volts.


Binary Counter

D C B A


7 6 5 4 3 2 1 0

DAC O/P

Voltage (V)

Comparator Output

0 0 0 0 1 0 0 0 0 0 0 0 1 28 1 START

0 0 0 1 1 1 0 0 0 0 0 0 1.92 1

0 0 1 0 1 1 1 0 0 0 0 0 2.24 1

0 0 1 1 1 1 1 1 0 0 0 0 2.40 0

0 1 0 0 1 1 1 0 1 0 0 0 2.32 1

0 1 0 1 1 1 1 0 1 1 0 0 2.36 0

0 1 1 0 1 1 1 0 1 0 1 0 2.34 1

0 1 1 1 1 1 1 0 1 0 1 1 2.35 0

1 0 0 0 1 1 1 0 1 0 1 0 2.34 STOP

FIG 4

The digital output is 11101010 for 2.34 volts in.

The advantage of the successive approximation DAC is that no matter what the analogue input voltage, it always takes the same amount of time to process the input.

If the DAC uses 12 bits, which has 8191 voltage levels, it takes 12 counts to process the input.

If the DAC uses 4 bits, which has 15 voltage levels, it takes 4 counts to process the input.



NOTES:



SECTION 7 : FAST PARALLEL ADC

INTRODUCTION

The Fast Parallel ADC, or Flash Converter, is the quickest ADC available.

It uses comparators with preset voltage references to determine what value the input analogue voltage is at. A priority encoder produces a digital output relative to the input analogue voltage.

CIRCUIT LAYOUT

Fig 1 shows the layout of a 3 bit fast parallel ADC.

FIG 1



FAST PARALLEL ADC PRINCIPLE

The resistor network produces reference voltages to the comparators of a step size equivalent to the LSB.

Depending on if the analogue input voltage is above or below the reference voltage, determines of a logic 0 and logic 1 is output from each of the comparators.

The outputs are inverted, and processed by the priority encoder circuit.

The digital output represents the input voltage.

FAST PARALLEL ADC ACTION

Fig 2 shows a 3 bit Fast Parallel ADC.

FIG 2

The resistor network produces reference voltages of 1 volt increments from 1 volt to 7 volts.



Example

The analogue input is at zero volts

All the non-inverting inputs of the comparators are greater than this value, giving logic 1s to the priority encoder.

The inputs are inverted, and 000 is produced as the output

Example

The analogue input is 7.5 volts.

All the non-inverting inputs of the comparators are less than this value, giving logic 0s to the priority encoder.

The inputs are inverted and 111 is produced as the output.

Fig 3 shows the digital outputs from the comparators, for different analogue inputs.

Analogue Voltages (Va) Comparator Outputs

C1 C2 C3 C4 C5 C6 C7

Va<1v 1 1 1 1 1 1 1

1v<Va>2v 0 1 1 1 1 1 1

2v<Va<3v 0 0 1 1 1 1 1

3v<Va<4v 0 0 0 1 1 1 1

4v<Va<5v 0 0 0 0 1 1 1

5v<Va<6v 0 0 0 0 0 1 1

6v<Va<7v 0 0 0 0 0 0 1

7v<Va 0 0 0 0 0 0 0

FIG 3



Fig 4 shows the comparator outputs inverted as inputs to the Priority Encoder.

AnalogueVoltages (Va)

Priority encoder Inputs

1 2 3 4 5 6 7Digital

Outputs

Va<1v 0 0 0 0 0 0 0 0 0 0

1v<Va>2v 1 0 0 0 0 0 0 0 0 1

2v<Va<3v 1 1 0 0 0 0 0 0 1 0

3v<Va<4v 1 1 1 0 0 0 0 0 1 1

4v<Va<5v 1 1 1 1 0 0 0 1 0 0

5v<Va<6v 1 1 1 1 1 0 0 1 0 1

6v<Va<7v 1 1 1 1 1 1 0 1 1 0

7v<Va 1 1 1 1 1 1 1 1 1 1

FIG 4

Advantage of a Fast Parallel ADC

The major advantage of the fast parallel ADC is its operating speed.

There is no clock as conversion takes place as soon as Va is applied and the only delay is the propagation delays of the comparators and encoder. This is typically around 50 m sec.

Disadvantage of a Fast Parallel ADC

The fast parallel ADC requires a lot of circuitry, one comparator circuit for each output data count except for zero.

The 3 bit requires 23 – 1 =8 – 1 = 7

An 8 bit requires 28 – 1 =256 – 1 255

An n bit requires 2n – 1

The high cost of these ADCs restrict their use to applications where high speed is a prime requirement.



CHAPTER 4 : DATA BUSES

DATA BUSES

Data buses are the systems used for transmission of data from one component to another. The data can be in the form of electrical or fibre optic signals, serial or parallel format.

Aeronautical Radio Incorporated (ARINC) has established many standards for aircraft electric and electronic installations. Among these specifications are the standards for data transmission buses and their format. Some of these will be discussed in this section.

The AMT needs to be familiar with the basic concepts, so that an understanding of the operation, functions and limitations can be known.

There are many specifications for aircraft electronics published by Aeronautical Radio Incorporated (ARINC). These specifications establish standards for many aspects of aircraft electronics and instruments. One of the standards covers digital data transmissions, which is specification 429.

ARINC 429

ARINC specification 429 covers the standards for transmission of data between components, transmission medium, data format of data between components, transmission medium, data format and others.

The transmission medium is a pair of twisted wires with shielding around them. This wiring is referred to as the ARINC 429 data bus.

ARINC 429 is a 32 bit serial data bus. Signals flow in only one direction on a bus. If two components required to transfer data between them, there would have to be two buses, one for sending information one way and the other for sending information back. Each bus would have its own transmitter and receiver.

The information transmitted is 32 bits long, sent one bit at a time. The digital signal uses -10 volts for a logic 0 and +10 volts for a logic 1.

ARINC 429 is designed to operate at a low speed of 12-14k bits per second and at a high speed of 100k bits per second, for transmission of information which must be updated rapidly. These two speeds cannot be mixed on a bus.

Issued April 2006 Chapter 4 1


FIG 1

2 Chapter 4 Issued April 2006


ARINC 429 DATA WORD

The ARINC 429 digital data word consists of 32 bits. The data word has five basic parts:

Label

Source/Destination Identifier (SDI)

Data Field

Sign Status Matrix (SSM)

Parity Bit

LABEL

Bits 1 to 8 comprise the label, this identifies the information contained in the data word (true air speed, total air temperature).

SOURCE/DESTINATION IDENTIFIER

Bits 9 and 10 comprise the Source/Destination Identifier (SDI), this is used when it is necessary to indicate the source of where the information is to be directed (1, 2, 3).

DATA FIELD

Bits 11 to 28 comprise the data field. This contains the specific data assigned to a label. This information fits certain parameters and can be in many different binary codes. If the data does not require all the available bits, binary 0 or pad bits are used to fill the field.

SIGN STATUS MATRIX

Bits 29 to 31 comprise the Sign Status Matrix (SSM). This identifies the characteristics of a word (+, -, North).

PARITY

Bit 32 is the parity bit; the bit value will give odd parity. Odd parity means that the sum of all logic 1s in the data word equals an odd number. This bit is used to check the transmission efficiency, since this is a one way bus.

SYCHRONISATION

To enable the receiver to identify the beginning of a transmission , the data word is synchronised by a minimum 4 bit time gap.



FIG 2



ARINC 429 – DIGITAL FORMAT

GENERAL

ARINC 429 uses the bipolar return to zero (RZ) modulation method. The information on an ARINC 429 bus can be in one of three states:

Hi

Null

Lo

The digital data word consists of a 32 bit word in bipolar form. Each bit is either in the logic 1 or logic 0 state. The null is used to separate the different bits and the different words.

The ARINC 429 bus operates at either of two speeds. The high speed ARINC 429 bus operates at 100 k bits/sec. The low speed bus operates at 12.0 kilo bits/sec. The speeds cannot be intermixed on the same bus.

The ARINC 429 bus is:

Self-clocking: the receiver senses the null between bits to generate its internal clocking.

Self-synchronising: the receiver senses the four bit null between words generate word synchronisation.

VOLTAGE LEVEL

The information on an ARINC 429 bus is transmitted in bit form. The first half of each bit represents the logic state of the bit. A high pulse (+10v) signifies a logic 1. A low pulse (-10v) signifies a logic 0. The +/- 10 volts is the differential voltage across the output terminals of the shielded part of twisted wires. The second half of each bit always returns to the NULL level (zero volts between terminals). The shield is grounded at both ends.

FIG 3 ELECTRICAL CHARACTERISTICS



FIG 4



ARINC 629

The ARINC 629 data bus is a high speed, two way, multiple terminal digital data bus. Up to 120 terminals can be connected to the bus, which is a twisted pair of wires that can be up to 100 metres long.

The bus operates at 2 megahertz which allows 100,000 20 bit words to be transmitted each second. Each terminal can send a message that contains up to 31 word strings and each word string can have 256 words.

BUS CABLE

The data bus cable is a pair of twisted wires that are not shielded. The bus allows any terminal to transmit and receive on a single cable. Each terminal is clamped onto the cable by a bus coupler that does not require cutting into the bus cable. There are bus terminators at each end of the cable.

BUS COUPLERS

The bus couplers are referred to as current mode couplers because they use the method of inductive coupling. This is similar to attaching a timing light to the spark plug wire when adjusting your car’s timing. Each LRU or LRM that requires to be connected to the bus uses a current mode coupler.

STUB CABLE

Each LRU or LRM is connected to its coupler by a stub cable. The stub cable contains two sets of shielded twisted pair of wires. One pair is used for transmitting and the other for receiving. The stub cables can be up to 40 meters long.



FIG 5



FIG 6



BUS CABLE INSTALLATION

Most ARINC 629 data bus cables are located within the electronics compartment of the aircraft. Also, most of the bus couplers are arranged in the panel with the bus cable running through each row and turned to run through the next row.

There are some bus cables that must run the length of the aircraft to connect units at the aft end of the aircraft to the electronics compartment. These cables may have production break splices done at the factory.

BUS COUPLER

The current mode couplers are used to connect each LRU or LRM to the data bus cable. Most are found in panels in the electronics compartment arranged in rows so that the bus cable can run through them. Up to 120 couplers can be connected to a bus cable.

The coupler is a two piece assembly. The coupler is attached to the cable by separating the halves, then separating the bus cable wires to fit over the coupler inductor, then the coupler assembly is closed. The upper half of the coupler assembly has the electronics for putting data on the bus and taking data off the bus and sending it to the LRU or LRM by the stub cable.

The stub cable is two sets of shielded twisted pair of wires. The stub cable is attached to the coupler and the LRU by connectors.



FIG 7



FIG 8



DATA STRUCTURE

ARINC 629 data transmitted in groups called messages. Messages are comprised of word strings. Up to 31 word strings can be in a message. Word strings have a label followed by up to 256 data words. Each label word and data word is 20 bits.

Only one terminal is allowed to transmit on the bus at a time. ARINC 629 uses a time procedure to allow only one terminal to transmit at a time and allows each terminal a chance to transmit. Basically, as each terminal powers up, it is put on the bus. There are three types of timers used, that allow this to happen.



FIG 9



ARINC 429-629

This chart compares the ARINC 429 data word to the ARINC 629 data word. ARINC 429 requires a different word for each type of information it sends. ARINC 629 uses a word string that has a label followed by information that can have up to 256 types of data. This permits faster transmitting or more information on the bus.

ARINC specification 629 deals with the standards for this bus. This bus is also referred to as the Digital Autonomous Terminal Access Communication (DATAC) bus.





CHAPTER 5 : COMPUTER ARCHITECTURESECTION 1 : THE BASIC SYSTEM

INTRODUCTION

A computer comprises of various elements – CPU, memory, and a range of Input/Output connections to devices such as displays switch control panels and external data buses. Almost all of a computer’s operations are concerned with the movement of data between these elements (eg reading a program from disc into memory, reading data, recalculating results and storing them back to memory). Some of these data transfers are purely internal to the computer, as in the case of air data updating. Other data transfers are to outside peripherals via cards plugged into expansion slots on the computer motherboard.

FIG 1

The diagram shows a simplified view of a computer system. The address bus and data bus link all the memory and input/output devices to the CPU and the main components are:

ADDRESS BUS Each memory location has a unique address number. The CPU has to be able to read or write data to any of these addresses. The CPU accesses a memory location by putting the wanted address number, in binary format, on to the Address Bus.

DATA BUS When the appropriate memory location is accessed, the CPU can either fetch data from it or write data into it; such data is transferred along the Data Bus.

CONTROL BUS All sections of the computer are controlled by these signals such as read, write and various chip select lines.



NOTES: Some of the memory will be in the form of ROM (Read Only Memory). This is a chip with the coding permanently burned into it. Its contents will not be lost if the machine power is switched off. Some, or all, of the system BIOS will be stored in ROM form.

Information never flows into the CPU from the Address Bus. The Address Bus is only used to allow the CPU to access various peripheral chips.

Since ROM cannot be written to, data only flows on to the data Bus from the ROM chip and never in the opposite direction.

Since RAM can either be read or written, there is a need to allow data to flow between memory and the CPU in either direction (only one direction at a time!)

The I/O expansion bus also has to be capable of both receiving and transmitting data on the Data bus (eg. a modem has to transfer data in both directions.



CPU

The CPU consists of three main parts:

The ALU – Carries out all the calculations and decision making tasks.

The Bus Interface Unit – Takes the data to and from the CPU (held inside its internal ‘registers’ – ie. small memory stores) along the external Data Bus to read/write memory and devices. The Data Bus is a two-way bus as it must carry information in both directions. The Bus Interface Unit also places the required location addresses on to the Address Bus, in order that the required devices can be accessed for reading or writing.

The Control Bus – Contains six control signals. Many CPUs have two major control lines, one that is brought to a low voltage level to indicate that a read is taking place and one that is brought to a low voltage level to indicate a write taking place. Naturally, only one of these lines will be brought low at any one time. The PC range of processors, the xxx86 range, treats memory and I/O devices differently and therefore has separate control lines for each. The PC’s main control lines are:

MEMR goes low to indicate a read memory

MEMW goes low to indicate a write to memory

IOR goes low to indicate a read of an I/O device

IOW goes low to indicate a write to an I/O device



The Address Bus and the Data Bus are simply the electrical paths between the CPU and the other chips. They exist as the copper tracks of the computer’s printed circuit board and the chips are soldered to these tracks. To allow other peripheral cards to attach to the buses, the buses connect to special sockets called ‘expansion slots’. The cards plug into these slots and pick up the bus connections, as well as power, from the edge connections.

All the bus connections are digital; they can only have two electrical states – either ON or OFF. This is due to the use of digital logic circuits. This means that every piece of information – from an address location number to an alphabetic letter – has to be represented in combinations of these ONs and OFFs.

MEMORY TYPES

A range of memory products exists, with differing characteristics. However, there are two basic types:

Those whose contents can only be read, during the running of a program. Some memory’s contents may be permanent while other memory chips may be removed from the computer and reprogrammed. Examples of this type are ROM, PROM, EPROM and EEPROM.

Those whose contents can be read and also written to. Examples are DRAM, SRAM, EDO and VRAM.

Apart from the above characteristics, memory can be graded in terms of capacity and speed of access. Take for example, a memory chip that is coded as:

41256-60

The first two digits indicate the product range, the rest of the numbers before the hyphen indicating the chip capacity (measured in thousands of bits). The numbers after the hyphen indicate the chip access time, where 60 means 60 nano-seconds, 70 means 70ns. Beware, however, that 10 means 100ns and 20 means 200ns, rather than the 10ns and 20ns that might be expected. So, the chip above is a 256 kilobyte, 60ns version.



ROM

These are ‘Read Only Memory’ chips and they are ‘non-volatile’; their contents will not be lost if the power is removed. These chips are used in a wide range of electronic control circuits, from industrial machine tools to domestic washing machines. They are also the ideal choice for computer control. A computer's control programmes require to be non-volatile. The computer’s basic functions are controlled by system software and there is a potential Catch-22 situation, in that

‘the computer needs a programme to be loaded, so that the computer can load a programme’.

By placing part of the operating system software into a ROM chip, the system BIOS, the basic machine control programmes are available to be run as soon as the computer is switched on. The programmes in the ROM provide the machine’s basic input and output functions, to allow application programmes to be loaded and run. Unfortunately, if the system is to be updated, the BIOS chip has to be replaced with a new Chip that contains the new programme routines. This requires opening the computer case and is a job for experienced support staff or technicians.

ROM chips are ‘mask programmed’ devices; the layers of the integrated circuit are manufactured using specifically designed masks. These produce chips that are only capable of performing the required predetermined programmes. Due to the cost of manufacturing ROMs, they are only used in large quantity runs. This, in turn, means that they are only made when the manufacturer is certain that the programmes they contain are debugged. These chips are also fitted in video, network and disc controller cards.



PROM

The initials stand for ‘Programmable Read Only Memory’. With ROM, the internal programme is dedicated at the production stage; the programme itself determined the physical construction of the ROM chip. A cheaper method for small and medium scale use is a ROM-type chip that is able to be programmed, after the construction stage. Such chips are mass produced by a chip manufacturer, who has no idea of the use to which they will be put. Once the chip is purchased by a computer manufacturer, the company’s programmes can be embedded in it. This is achieved by ‘blowing’ fusible links inside the chip, to form the binary codes representing the programme’s machine code instructions. Every intact link represents a binary 1, with a blown link representing a binary 0. Like the ROM, the PROM chip is also non-volatile.

EPROM

The initials stand for ‘Erasable Programmable Read Only Memory’ and it was introduced as a development tool. The problem with ROM and a programmed PROM was that, once produced, they were unalterable. This is perfectly fine for a computer manufacturer – once the programme contents are fully debugged. The EPROM is used to test the programme. Like PROM, its links are blown to the needs of the test programme. The EPROM can then be used on the test computer. If the programme is satisfactory it can be used to create mass ROM or PROM versions. If the programme needs alteration, the EPROM is subjected to ultra-violet light for a few minutes. This ‘heals’ the ruptured links, allowing the chip to be blown to the next programme. The blowing and wiping clean process can be repeated many times over, before the chip fabric starts to degenerate.

An EPROM chip is easily identified as it has a glass window on top of the chip to allow entry of the ultra-violet light. Due to its expensive construction, it is only a viable alternative to ROM and EPROM for small scale use.

Example:

EPROM chips would be the 2764-20 (64k – ie. 8k x 8 bits) and the 27512-20 (512k – ie. 64k x 8 bits). The equipment required to programme and erase EPROMs can be cheap enough for individual or hobbyist use. For continual development use, the EPROM is often replaced with a ‘ROM emulator’. This is a piece of equipment that plugs into the ROM socket and acts like an EPROM. It contains RAM to avoid the programme-erase cycles. Since it is self-powered, it appears to the main computer as a piece of ROM.



EEPROM

A variation on the EPROM is the EEPROM – the ‘Electrically Erasable and Programmable Read Only Memory’. Like EPROM, it holds its contents when the power is removed. However, its contents can be overwritten without resorting to prior cleaning with ultra-violet light. It is currently more expensive than other memory devices.

MAIN MEMORY

The variations on ROM memory outlined earlier are primarily concerned with the computer’s basic control functions, with application programmes being loaded from disc into main memory. This is not always the case. Many palmtop computers use ROM to store application programmes, to overcome the storage problems associated with such small machines. Due to their tiny physical dimensions, there is no space for a hard disc to store application software. So, the machine stores a word processor, spreadsheet, personal organiser, etc. in ROM.

In most computers, however, the application software is loaded into, and run from, main memory. In addition, there is a need for an area to store programme data and video data. These memory areas use RAM which stands for ‘Random Access Memory’. Unlike ROM technology, RAM chips are volatile which means that the data stored in the chips only remains there as long as the chips are powered. When the machine is switched off, the chips lose their contents. That is why users are always reminded to save all their data before switching off their machines. In fact, to ensure complete data integrity, the application should be exited, ie. getting back to the DOS prompt, before switching off. This ensures that any data held in the computer’s memory buffers are flushed away to disc. A database, for example, will not save each record as it is entered; it will save a number of records into a buffer area and then save the groups of records. Although they appear to the user as having been saved, they are still vulnerable to loss, if the power is switched off. The term ‘random access’ is used to distinguish it from serial access devices. With serial access devices, such as tapes, the data is read in with one item following the other. The last item takes longer to fetch than the first item. Random access means that any cell address in the entire memory area can be accessed with a uniform time overhead.

NOTE: Confusingly, ROM chips are also random access devices. The difference between ROM and RAM variants is not in their access methods, but in their volatility (or lack of it) and speed.



COMPUTER TECHNOLOGY IN AIRCRAFT

Honeywell’s sensor package enables the SPZ-5000 to provide smooth, precise control of the Citation Jet. The industry standard VG-14A Vertical gyro and C-14D directional gyro provide heading and attitude information. The AG-222 accelerometer outputs are used to provide smooth G-limited manoeuvres throughout the Citation Jet flight regime. The compact AZ-649 air data sensor outputs are used by the IC-500 for altitude and airspeed modes.

IC-500 DISPLAY GUIDANCE COMPUTER

The heart of the SPZ-5000 for the Citation Jet is the IC-500, a ½ ATR short unit containing an EFIS symbol generator, flight director computer and autopilot computer.

The autopilot function incorporates full three-axis, single-channel control implemented in a digital enhancement of the flight-proven SPZ-500 autopilot flying in thousands of Citations. The SPZ-5000 is a full fail-passive system which incorporates internal monitoring of the autopilot operation. This provides two benefits. First, autopilot monitoring allows the use of a wide range of torque to optimise control over the full altitude and airspeed regime. Citation Jet operators have it all – smooth high altitude cruise with precise handling in the demanding low altitude environment, even with gear and flaps down. Second, should a fault occur, the system prevents any significant attitude change of the aircraft.

FIG 2



IAC

The Integrated Avionics Computer at the heart of the PRIMUS 2000 combines the functions of an advanced digital flight control computer, a fault warning computer, dual EFIS display processors and an optional FMS computer into one lightweight package dramatically smaller than the total volume of older technology it replaces. The flight control function includes an integrated flight director, yaw damper and autopilot. The proven autopilot is all-digital and fully fail-passive, which allows it to be non-torque limited. This results in the ultimate control possible in all flight conditions, without jeopardising safety.

The IAC has at least 50% more processor capacity and 100% more memory than the functional LRUs it replaces

FIG 3



Honeywell’s advanced avionics for the Dornier 328 offer the operator exceptionally high reliability and simplified maintenance with a designed-in, Built-In Test routine that features a streamlined menu and user-friendly messages.

FIG 4



HONEYWELL SPZ-5000 SYSTEM

FIG 5



NOTES:



CHAPTER 6 : ELECTRONIC DISPLAYSSECTION 1 : CATHODE RAY TUBE (CRT)

Advanced display screen technologies are becoming cheaper and better all the time. The main applications for flat screen displays are ones for which a CRT would be quite unsuitable, and therefore for which the extra cost or reduced performance of a flat screen display is not a barrier.

Why can CRTs not be made thinner and lighter to compete with true flat displays? After all, they give better picture quality at a lower cost than flat-panel alternatives. CRTs have been slimmed down a good deal over the years, but there is a point at which the problems to be overcome increase so much that it is not economic to proceed.

For example, look at Fig 1, showing beam deflection.

FIG 1 SCANNING THE ELECTRON BEAM IN AN ANGULAR CATHODE RAY TUBE

The beam is deflected by means of a magnetic field. If the deflection is truly proportional to the current in the deflection coil – which may not be the case, since different trajectories cause the electron beam to spend a different amount of time in the field – then the deflection of the beam across the screen will be disproportional. This effect causes picture geometry errors which must be corrected with more circuitry. Fig 2 shows the form of an uncorrected picture known as pin cushion distortion. It stretches further at the corners, because that is where the path length of the electron beam is longest, as it must be when you consider the three dimensional properties of the deflection system.



FIG 2 PICTURE DISTORTION DUE TO DEFLECTION ON TO A FLAT SCREEN

Clearly, the thinner the CRT for a given screen size, the worse the error will be. Then there are three different colours to be corrected separately so that they all line up – and it becomes clear why there is a limit to how thin a CRT can be made.



SECTION 2 : THE ELECTRON BEAM

This is used to generate and focus the electron beam so that it reaches the screen in the best possible condition.

THE DEVIATION CONTROL

This can be divided into two categories:

Electrostatic Deviation – This is obtained by creating an electrical field between two sets of metal plates. The horizontal plates cause vertical deviation whilst the vertical plates cause horizontal deviation. This type of variation is found on relatively simple devices, such as oscilloscopes, which display forms rather than images.

Electromagnetic Deviation – This is obtained by an electromagnet field created by current flow in the deviation coils positioned vertically and horizontally around the neck of he CRT.

SHADOW MASK AND SCREEN

This is essentially the front of the CRT which is phosphor coated so that when the electron beam impacts with the screen light is emitted. The brilliance of this light is controlled by the number of electrons passing down the tube per second. The sharpness of the light is controlled by the magnitude of voltage applied to the electron lens element. The beam of electrons, and hence the spot of light on the screen, can be deflected by applying voltages across the ‘X’ and ‘Y’ deflectors.

FIG 1



COLOUR GENERATION

Both the analysis and synthesis are based on the fact any colour can be produced using three primary colours: RED, BLUE and GREEN, as shown below. This can be best explained by considering colour photography.

Any analyser, a camera for example, divides the colour of an object into its three basic components, Red, Green and Blue. When these colours arrive at the film, via a system of lens and mirrors, which is light and colour sensitive, they are used to reproduce the original colours. It is the intensity of the primary colours which determine the shading of the spectrum colours.

If the intensity of the primary colours could be measured and given an equivalent signal value, then this signal could be used to control the electron flow in a CRT. Such a signal is termed the ‘Chrominance Signal’.

FIG 2



Since three primary colours create three Chrominance signals, it stands to reason that in a CRT three corresponding guns are required. These are often referred to as the ‘Coplaner guns’. In older CRTs, these guns were mounted in a triangular configuration, this arrangement necessitated providing excessive correction. The preferred arrangement is now to have the guns mounted laterally as shown below.

FIG 3 COPLANER GUNS

The basic layout of the gun is shown in Fig 4. The component functions are:

FIG 4



A Filament (F) to heat a Cathode (K) to make it generate electrons.

A Grid (G1) or Wehnelt which controls the electron stream generated by the Cathode. This grid is permanently negatively biased.

A Grid (G2) which is a Bias grid.

A Grid (G3) which is a Focussing grid.

A Grid (G4) which is the Acceleration Anode.

The electron beam generated by a gun hits the luminescent material on the inner face of the screen, as at Fig 5. Each component of this material is called a luminophore. A trio of luminophores comprise the primary colours, red, blue and green. The scale of size is such that the distance between adjacent trio’s is slightly less than 1 millimetre.

For a correct reproduction of colours, the green gun generated electrons must hit the green luminophores only, red to red and blue to blue.

FIG 5



The deviation device converges the beams of each colour to a point which corresponds to one of the mask holes, so that each electron beam hits the luminophore corresponding to the colour of gun it comes from.

Fig 6 shows the principle of the shadow mask.

Assume that the beam is deflected horizontally from A to B.

At point ‘A’ the mask has no holes and the beam is blocked. If the mask had not been there, the beams converging on ‘A’ would hit any luminophore.

The blue beam would hit the green and vice versa. Colours would be changed.

FIG 6

The layout of the holes in the mask is such, that on passing through, the beams activate the luminophores corresponding to their colours, as shown at Fig 7.

FIG 7



Shown below, at Fig 8, is a block schematic of a typical CRT control circuit.

FIG 8

To understand how a figure is generated, let us take the example of a fixed figure ie the aircraft mock-up on the EADI.

The generation of this mock-up is independent of the aircraft parameters (altitude, airspeed, etc). In the microcompressor, there is a mock-up generating sub-programme which is called whenever the mock-up must appear on the EADI.

FIG 9



This sub-programme generates information which is transformed by the symbol generator. This generator is a sort of interface between the micro-processor and the CRT control circuits, since it generates, at every moment,

The position (X, Y) of the spot on the screen

And the colour information

For instance, the spot starts positioning at x0 y0, then it moves to x1 y1, x2 y2, x3 y3, etc.

As far as the colour information is concerned, the signal from the symbol generator is coded so that the mock-up colour is yellow.

Therefore, only the CRT red and green guns are activated (red + green = yellow).

FIG 10



SECTION 3 : LIQUID CRYSTAL DISPLAYS

Flat displays have been around for years. The first to go public in significant quantities were liquid crystal monochrome displays. In a liquid crystal display, the liquid crystal layer can either rotate or not rotate the polarisation of light passing through it.

With no voltage applied to the display, the liquid crystal molecules line up at the surfaces in a direction determined by the surface finish of the front and back electrodes. When a voltage is applied, the molecules line up (Fig 1).

At some stage in the development of matrixed twisted nematic displays, techniques for increasing the twist angle were devised, and they became known as Super Twist or STN displays. For a while they looked like going out of use, but improved versions have been developed.

FIG 1 ROTATION OF LIGHT POLARISATION BY A TWISTED NEMATIC LIQUID CRYSTAL CELL

Because liquid crystal displays are damaged by direct current, the drive voltage must be an alternating voltage, with front and rear electrodes driven in phase if the pixel is to be unenergised, or in antiphase if it is energised. This is the widely used twisted-nematic type of display.



To convert the change of polarisation to something visible to the human eye, an arrangement such as that shown in Fig 2 is used.

FIG 2 THE USE OF POLARISERS IN A LIQUID CRYSTAL CELL

Here, light cannot pass through the crossed polarisers unless its polarisation is rotated in the liquid crystal cell.



If you want to make a vga display panel, you need 640 pixels horizontally and 480 vertically. This, which would be considered a miserable resolution by current standards, needs 640 separately connected with vertical strips of electrode, and 480 horizontal strips, in order to address each individual pixel. The interconnection problem is costly to solve, but it can be done, for example, by using elastomeric connectors which press on to metallised contacts on the edge of the display glass (Fig 3).

FIG 3 MATRIXING OF A STN DISPLAY – CROSSTALK TO ADJACENT PIXELS IS POSSIBLE

The electronics to address this uses surface-mount ICs with multiple pins, or ball grid array connections. This is inherently costly to make.

Still, perhaps the major problem of displays like this is how to make the display visible, when each pixel is only addressed for a tiny proportion of the time. The molecules must line up with the voltage rapidly, but settle back to their un-energised position slowly. It is not surprising, therefore, that the response of this type of liquid crystal display to changes in picture content is a bit sluggish.



LIQUID CRYSTAL

LCD’s can also be used as alpha-numeric indicators, especially in systems where low power and long life is needed (microamperes compared with milliamperes). Liquid crystals are organic (carbon) compounds which exhibit both solid and liquid properties. Identified as cell-like in construction they consist of transparent metallic conductors called electrodes, on opposite faces, containing a liquid crystal. A voltage applied across the electrodes caused a molecular rearrangement within the crystal structure.

This arrangement displayed either numbers or letters and was always based on the seven segment display, however using up to date technology, flat screen displays as featured on the B777, are the ‘norm’ for the future. These displays are multicolour.

FIG 4



The most used type of LCD for flight deck indication uses a method known as the twisted nematic field effect. In simple terms the LC has its nematic molecules aligned homogeneously but with a 90 degree displacement between the top and bottom layers ie a 90 degree twist. If a signal voltage is now applied the molecules will untwist and line up with the applied field. So if the LC were placed in the path of polarised light, depending upon whether the input and output polarisers were parallel and displaced with each other, a display of light on dark or dark on light can be obtained.

Fig 5 shows the 7 segment layout for a LCD.

FIG 5



NOTES:



SECTION 4 : AMORPHOUS TRANSISTORS ON GLASS

Some years ago, three physicists shared the Nobel prize for work on amorphous materials. The first product seen by the public as a result of this fundamental research was the solar powered calculator. It was found to be possible to make semiconductors using amorphous materials rather than perfect crystals. The material had to have hydrogen added to all the unattached bonds which would otherwise trap charge carriers. Crystalline semiconductors gave superior performance, but where a transistor is used to improve the drive to each pixel. Referring to Fig 1, the circuit on the left here shows that a capacitor is charged to the voltage on the data line when the gate line is energised. The thin film field effect transistor is acting as a sampling switch, and the capacitor holds the sampled voltage until the next time it is addressed.

The performance of liquid crystal displays using this technology is greatly superior to normal STN displays. For a start, the liquid crystal material does not need to be optimised to retain the picture information between scans, so it can be made to respond more quickly. Portable LCD televisions using this type of screen have no visible problems with normal moving TV pictures. However, the delay can be detectable by the eye on some TFT computer screens, when the mouse cursor is moved very quickly. To detect it, though, you have to be looking for it. Picture streaking due to crosstalk between pixels in an STN display does not occur on tft displays. Also, because the liquid crystal material is not optimised for one obscure function (slow response) it can be made with a wider viewing angle. The angle is still limited, and it is still necessary to position the screen correctly relative to the viewer, but the problem is eased compared with the typical STN display.

The drawback with TFT displays is that there is a lot of electronics for each pixel. Even a single pixel which does not work can be visible, but it is very difficult to manufacture screens with 100% functional pixels. Therefore, quality standards are defined which limit the number of defects in the whole screen area, and further limit the number in the middle area. Even so, many displays do not meet the quality standard and have to be scrapped. This contributes to the relatively high cost of TFT displays, particularly large ones with more pixels. Typically, a 1024 x 768 pixel computer display can cost more than a complete machine with a 17 in crt monitor. As an aside, the means of using thin film transistors was first devised by a British engineer. It was not possible to get funding to develop this in Britain or elsewhere in the EU, so the technology was developed in Japan, whose industries have made a good return from it.



FIG 1 A TFT ACTIVE MATRIX LIQUID CRYSTAL DISPLAY



SECTION 5 : THE LIGHT EMITTING DIODE (LED)

Certain Transducers (diodes produce electrical signals from light. The opposite is done by a light emitting diode, shown below, with its symbol. The cathode lead is nearer the ‘flat’ at the base of the LED and some, but by no means all, manufacturers make it shorter than the anode lead.

FIG 1

OPERATION

An LED consists of a junction diode made from the semiconducting compound gallium arsenide phosphide. It emits light when forward biased, the colour depending on the composition and impurity content of the compound. At present red, yellow and green LED’s are available. When a p-n junction diode is forward biased, electrons move across the junction from the n-type side to the p-type side where they recombine with holes near the junction. The same occurs with holes going across the junction from the p-type side.

Every recombination results in the release of a certain amount of energy, causing, in most semiconductors, a temperature rise. In gallium arsenide phosphide some of the energy is emitted as light which gets out of the LED because the junction is formed very close to the surface of the material. An LED does not light when reverse biased and if the bias is 5v or more then it may be damaged.



EXTERNAL RESISTOR

Unless an LED is of the ‘Constant-current type’ (incorporating an integrated circuit regulator), it must have an external resistor connected in series to limit the forward current which, typically, may be 10mA (0.01A).

Taking the voltage drop (Vj) across a conducting LED to be about 1.7v, R can be calculated approximately from

R = (supply voltage – 1.7) v/0.01A

For example, on a 5v supply, R = 3.3/0.01 = 330 ohms

USES

LEDs are used as indicator lamps, particularly in digital electronic circuits to show whether the output is ‘high’ or ‘low’. One way of using an LED to test for a ‘high’ output (9v in this case) is shown below in (a) and for a ‘low’ output (Ov) in (b). In the first case the output acts as the ‘source’ of the LED current and in the second it has to be able to accept or ‘sink’ the current. If the output is unable to supply the current required by the LED, the circuit of (c) below can be employed. Here the output supplies the small base current to the transistor which then drives the LED.

FIG 2



DECIMAL DISPLAY

Many examples of decimal displays have seven segment red or green LED displays as alpha-numerical indicators (Fig a). Each segment is an LED and depending on which segments are energised, the display lights up the numbers 0 to 9 as shown in Fig (b).

Such displays are usually designed to work on a 5v supply.

(a) FIG 3 (b)

Each segment needs a separate current – limiting resistor and all the cathodes (or anodes) are joined together to form a common connection. The advantages of LED’s are small size, reliability, long life, small current requirement and high operating speed.

FIG 4



NOTES:



CHAPTER 7 : FIBRE OPTICSSECTION 1 : HISTORY

INTRODUCTION

Although optical fibres have been around for a long time, transmission of information through them is a relatively new technology.

Reflection of sunlight from a shiny surface was the first type of light beam communication. The first transmission of speech using a light beam was made February 19, 1880, by Alexander Graham Bell.

Because of serious limitations of the technology, this means of communication was ignored until the 1960s when the development of the laser (light amplification by stimulated emission of radiation) focused attention on the possibility of introducing a light beam into a ‘glass pipe,’ or optical fibre.

LASER

The electromagnetic radiation output (light) from a laser is monochromatic, and the rays are parallel and in phase. In 1962, the gallium arsenide light-emitting diode (LED) was developed, which produces a light near the infra red end of the visible spectrum. The semi-conductor laser was also developed in 1962.

For light beams to enter and travel down an optical fibre, the incident light should be coherent.

Coherent light has parallel light rays that are in phase and monochromatic.

Light not displaying these characteristics is termed noncoherent.

OPTICAL FIBRES

Optical fibres became of interest as a closed system conductor of light from a transmitter to a receiver. Low loss silica fibres were developed in 1966; however, these still had losses rated in thousands of decibels per kilometre.

Corning developed optical fibres in 1970 characterised by a loss rating of 20 db/km.

In 1979, the Japanese developed super-pure silica fibres with a 0.2-dB/km loss.

Advances in outer space manufacturing technology have led to the possibility of ultra-pure silica, which could be used to produce an optical fibre transmission line with nearly zero loss. Since the fibres are manufactured in zero gravity, air bubbles and impurities which cause loses from internal reflection of light are eliminated.



NOTES:



SECTION 2 : OPTICAL FIBRE TYPES

INTRODUCTION

Optical Fibres are generally available in 2 types of material, glass and plastic.

The choice of fibre type depends on the useage of the cable.

Fig 1 shows the ends of a fibre optic cable bundle.

FIG 1

GLASS FIBRE-OPTICS

Glass fibre-optics are made up of a bundle of very small glass fibre strands, typically 50 microns in diameter. A typical glass fibre-optic consists of several thousand cladded glass fibres protected by a sheathing material. The fibre-optic is terminated in an end tip that is partially filled with a rigid clear epoxy. The sensing face is optically polished so that the end of the fibre is perfectly flat. The quality of this polishing dramatically affects the optical coupling efficiency of the fibre.

The fibre-optic ‘bundle’ may even be shaped at the sensing end to match the profile of the object to be sensed.

Most glass fibre-optic assemblies are rugged and perform reliably in extreme temperature conditions. The most common problem experienced is breakage of the individual glass strands as a result of sharp binding or continual flexing when installed on reciprocating mechanisms.



PLASTIC FIBRE-OPTICS

Plastic fibre-optics are single strands of fibre-optic material, typically 0.25 to 1.5 mm in diameter. Most plastic fibre-optics are terminated at the sensing end with a bendable probe or threaded tip. The other end is not terminated, therefore it can be cut to length on site with the special cutter supplied.

Unlike glass fibre-optics, plastic fibres will tolerate repeated flexing. In fact, pre-coiled plastic fibre-optics are available for sensing applications on reciprocating mechanisms. Plastic fibre-optics require a visible light source for effective sensing as they absorb most infra red wavelengths. They are also less tolerant of temperature extremes and are sensitive to many chemicals and solvents.



SECTION 3 : OPTICAL FIBRE CONSTRUCTION

INTRODUCTION

Optical fibres are made up of different layers of material which are carefully chosen to minimise losses in the fibre and still be strong enough to survive handling.

CONSTRUCTION

The optical fibre has 2 concentric layers and a protective layer.

The CORE which carries the light

The CLADDING which provides the difference in refractive index that allows total internal reflection of light through the core

the COATING which is usually one or more layers of polymer to protect the core and cladding from shocks, vibration and contamination.

The core has a different refractive index than the cladding to allow the transmission of light.

The cladding often has a lower refractive index than the core.

Fig 1 shows the layers and how light reflects along the optical fibre.

FIG 1

The fibres sizes are usually expressed by giving the core size, followed by the cladding size, in m.

A 50/125 fibre cable has a core size of 50m and a cladding size of 125 m. (A human hair is approximately 100m).



NOTES:



SECTION 4 : LIGHT WAVES

INTRODUCTION

Light is electromagnetic radiation and is similar to electricity in many respects. Visible light is only a small part of the light spectrum.

LIGHT WAVE PARAMETERS

The speed of light is 300 106 m/sec.

Light waves are very small and is expressed in terms of the wavelength.

Ultraviolet light is 10 nm to 390 nm

Visible light is 391 nm to 770 nm

Infrared light is 771 nm to 1m

A gallium arsenide laser emits a light of 904 nm which is 3.3 1014 Hz.

Very small wavelengths translate into very high frequencies, which opens up a part of the electromagnetic spectrum previously not used for communications purposes. High frequencies permit the use of very broad bandwidths which are required for data communications.

LIGHT WAVE PROPERTIES

If two light waves reach peak values together, they are in phase and the effect is additive. This relationship is called constructive interference.

If two light waves are 180 out of phase, they cancel each other. This effect is termed destructive interference.

Parallel light rays follow the axis of direction of the optical fibre without reflecting from the fibre’s interior walls, reducing destructive interference and loss.

Fig 1 shows coherent light wave properties.

FIG 1



Fig 2 shows non parallel light waves

FIG 2

Fig 3 shows phase different light waves.

FIG 3

Fig 4 shows 2 light waves of different wavelengths (different colours).

FIG 4

Light emitted from a laser is characteristically coherent and thus desirable for light beam communications through optical fibres.



SECTION 5 : DATA TRANSMISSION

INTRODUCTION

Depending on the application, the transmitter and receiver can be very simple or complex.

Fig 1 shows a simple transmitter and receiver.

FIG 1

The electronic signal is input to a driver which provides the drive for the source. The source may be an LED or laser diode.

The output from the source is transmitted into the optical fibre and reflects along the length of the cable.

The detector receives the information and sends it to the output circuit which outputs the electronic signal.

OPTICAL FIBRE LINK

Many modes of communication are possible between 2 stations ( a transmitter and receiver).

SIMPLEX transmission occurs between a single transmitter and a single receiver. It is a ONE-WAY communication link

HALF DUPLEX transmission occurs between 2 transceivers and either can transmit or receive but not at the same time. It is BI-DIRECTIONAL communication link.

FULL DUPLEX transmission involves simultaneous two way communication. It is a bi-directional communication link.

If a duplex network containing optical fibres involves more than one transmitter or receiver, the switching system is expensive compared to electrical or electronic switching since optical fibre links are mechanically connected and mechanical switches must be used.

OPTICAL FIBRE COUPLERS

A fibre optic link is a point to point system one transmitter linked to one receiver. In many applications it is desirable to divide light from one fibre into several fibres or couple several fibres into one fibre.

A COUPLER is a device that performs such distribution.



Couplers are used in networks and data buses and is a multi-port device of which there are many different types.

Fig 2 shows a TEE COUPLER which connects several terminals onto a common data bus.

FIG 2

Fig 3 shows a STAR COUPLER which combines or couples the cables.

FIG 3



Fig 4 shows a FUSED STAR COUPLER where the fibres are wrapped together at a central point and heater. The fibres fuse together producing a coupling.

FIG 4



NOTES:



SECTION 6 : ADVANTAGES AND DISADVANTAGES OF OPTICAL FIBRES

INTRODUCTION

Fibre optics have many advantages over conventional wire cables, such as

Wide bandwidth

Low loss

Electro magnetic immunity

Light weight

Small size

Safety

Security

BANDWIDTH

Bandwidth is an effective indication of the rate at which information can be sent. Optical fibres have an extremely large frequency range which allows the simultaneously transmission of voice, data and video.

LOW LOSS

Loss indicates how far the information can be sent.

ELECTROMAGNETIC IMMUNITY

Unlike copper cables, optical fibres do not RADIATE or PICK-UP electromagnetic radiation.

Copper conductors act like an aerial transmitting or receiving energy. Optical fibres do not radiate or receive electro magnetic energy so are immune to radiated interference.

LIGHTWEIGHT

An optical fibre weights considerably less than a copper conductor. To transmit the same amount of data, that an optical fibre can handle, requires many copper wires.

SMALL SIZE

A single optical fibre is smaller than its copper equivalent. A fibre optic cable greatly exceeds the data capacity of a coaxial cable even though it is 10 times smaller.



SAFETY

A fibre is a dielectric and does not carry electricity and therefore presents no fire hazard. It can be safely run through hazardous areas where wires might present a danger, such as fuel tanks. As it is a non conductor, lightning strikes will not damage optical fibres.

SECURITY

Fibre optics is a highly secure transmission medium as it does not radiate electromagnetic radiation and is extremely difficult to top into the cable.

DISADVANTAGES OF FIBRE OPTICS

Disadvantages of Fibre optic cables.

Fibre optics cannot carry electricity.

Manufacturing techniques are more complicated than for metal conductors.

As the Optical fibres are so small, they are difficult to handle, such as splicing, whereas a wire cable can be crimped or soldered together relatively easily.

The advantages of optical fibres far out-weight the disadvantages.



SECTION 7 : OPTICAL FIBRE TERMINATIONS

INTRODUCTION

There are many different terminations available to terminate or splice the optical fibre cables. Two examples are detailed below.

MICRO LENS

Fig 1 show the construction of a connector using a small glass bead or MICRO LENS to focus the light output of the LED into the optical fibre.

FIG 1

PIGTAIL

The PIGTAIL approach is to permanently attach the fibre to the source. A common way of achieving this is to cement the fibre into a V groove and align the fibre and source to obtain optimum coupling. This type is especially used with laser sources as the pigtail brings the fibre as close to the laser chip as possible to prevent any light spread before entering the fibre.



NOTES:



CHAPTER 8 : ELECTROSTATIC SENSITIVE DEVICESSECTION 1 : ELECTRO STATIC DISCHARGE SENSITIVE DEVICES

INTRODUCTION

Electro Static Discharge (ESD) is the term used to describe the sensitivity of electronic components to static electrical charges. Many of these components such as some types of Light Emitting Diode, computer chips, circuit boards etc. can be damaged beyond repair by an electrical discharge as low as 100 volts.

Recent studies have shown that 25% of all component failures are related to Electro Static Discharges and of all defective components that are received, 50% are damaged on arrival due to ESD.

Electro Static Discharge is regarded as one of the biggest problems facing the electronics industry.

ELECTRO STATIC DISCHARGE DEFINITION

Electro Static Discharge is the transfer of electro static charge between bodies at different potentials caused by direct contact or induced by an electro static field.

When two bodies are rubbed against each other, transfer of electrons takes place very rapidly. The body that loses electrons becomes positively charged while the one that receives electrons, it becomes negatively charged. Since a charge is transferred, electricity is generated. This generation of electricity, due to transfer of charges, is called a Triboelectric effect. Static electricity can also be generated when two objects in contact are suddenly separated from each other. Even activities such as walking across the floor or standing up from a chair can generate static electricity.

Fig 1 below shows a sample of materials that becomes positively or negatively charged.

FIG 1



The human body has a capacitance of around 100-250pfd and can be charged up storing the charge.

When another item, such as a computer chip, is touched, the body capacitor rapidly discharges.

It is possible to have 25,000 volts of static built up on a person dependent on humidity and the materials producing the charge.

VOLTAGE LEVELS

Electro static discharges become a more serious problem on low humidity days where the lack of moisture permits a more rapid static charge build up due to friction.

A technician walking across an aircraft carpet or removing a coat may accumulate a static charge of over 100 volts.

Most people cannot feel an electro static discharge below 3000 volts, however a discharge that produces a physical spark is typically over 12000 volts.

These levels are well above the tolerance levels of Electro Static Devices.

DAMAGE

An Integrated Circuit (IC) consists of several transistors fabricated on one chip where thousands of transistors are crowded together. By decreasing the thickness of the gate oxides and interconnecting lines the manufacturers hope to achieve much higher speeds at very low power consumption. But under these conditions if the Electrostatic Discharge passes through an IC and the current that results is not diverted or diminished by a suitable protective mechanism, the discharge may raise the temperature of the junction inside the component to melting point which will cause damage to the junction or interconnecting lines.

Since surface mount devices are smaller than conventional ICs they are even more susceptible to ESD damage. ESD causes two main types of failures:

Immediate failure where the effect can be readily seen by the equipment manufacturer.

Delayed failure where the device is damaged only up to the point where it may pass quality control tests, but wears out sooner than its rated time.

PROTECTION

It is very difficult to determine the point at which the damage due to electrostatic discharge occurs, since it can take place right from the manufacturing process, assembly, testing, packaging and shipping to the airline supply system and subsequent fitting by the user.

Some protection measures are required to prevent damage.

Work stations must have conductive mats provided.

Technicians handling devices must use an earthed wrist strap.

Specialist soldering irons and test equipment must be suitably earthed and checked regularly.



Anti static materials must be used to transport and handle devices.

Any component must have its connecting leads shorted together – by means of wires, shorting clips, metal foil or a conductive foam.

Printed Circuit Boards (PCB) connections must have their edge connectors shorted together to keep all the installed components at the same potential.

Touching of component leads and PCB connectors must be avoided.



PREVENTION

A wrist strap, as shown in Fig 2 below, must be connected to earth through a 1M resistor. This will discharge any charge that may be built up and also prevent any further build up of a static charge.

FIG 2

The resistor is provided as a safety feature. All power must be switched off in the area that a technician, using an earthed wrist strap, is working. If the technician should inadvertently come into contact with a voltage supply, the M1 resistor will share the supply voltage, reducing the amount of damage to the body.

Any tools that may come into contact with an Electro Sensitive Device must be earthed. Tool such as screwdrivers or pliers, generally have insulating handles so are not discharged through the wrist strap.

Discharging can be achieved by momentarily touching the metal surface of the tool to earth.



SYMBOLS

There are 3 symbols in common use to identify Electro Static Discharge Sensitive (ESDS) parts.

Fig 3 shows the symbol for an item that must only be removed from the packaging at a static free work station.

FIG 3

Fig 4 shows the symbol for an item that must be handled only at a static free work station.

FIG 4

Fig 5 is the symbol most commonly used to indicate that an equipment or container has ESDS parts and care must be taken.

FIG 5



TRANSPORTATION

If an ESDS component/PCB is to be removed from an aircraft, it must be placed in a special container to protect it from any static electricity until it is received for maintenance.

These special containers are made from a semi-conductive plastic material.

They may be specialist containers with a fastener to secure the item such as shown in Fig 6 below.

FIG 6

A common container is a semi-conductive plastic bag with the label, identified at Fig 5, securing the open end.

CONCLUSION

The elimination of electro static discharge can make a big difference to the safe operation of aircraft.

Electrostatic discharges

Often cannot be seen, heard or felt.

May stress, degrade or damage devices, even without physical contact.

May produce large voltages capable of causing damage.

May occur at any time.

It is the responsibility of everyone to ensure Electro Static Discharge Sensitive devices are handled correctly.



CHAPTER 9 : ELECTROMAGNETIC ENVIRONMENTSECTION 1 : HIGH INTENSITY RADIATED FIELDS (HIRF)

INTRODUCTION

Today’s digital aircraft systems communicate through the movement of thousands of bits of digital data. These data streams operate at extremely low power levels and can easily be overridden by a more powerful signal. This is the underlying concept that makes radiated energy from electromagnetic fields so troublesome. High-intensity radiated electromagnetic fields (HIRF) are emitted by virtually every radio broadcast tower in the world. Every FM transmitter, every TV station antenna, and every radar station emits electromagnetic energy. This radiated energy can and will induce a current into a nearby conductor. If the conductor happens to be a data bus and if the induced current is strong enough, the possibility exists that the data on the bus can be lost. For an aircraft, this loss of data can be catastrophic.

Recent FAA standards require all new equipment to undergo HIRF testing. These tests are used to ensure that the electronic components used on modern digital systems will not fail when subjected to high-intensity electromagnetic fields. An aircraft might be subjected to such high-intensity fields if it flies too close to a powerful radio transmitter or perhaps if it is struck by lightning.

Composite structures, which block less magnetic energy than conventional aluminium aircraft, also complicate the issue. Today’s standards for HIRF testing may be adequate or may be increased; but if aircraft continue to rely on low-energy digital circuits, the threat of HIRF will remain.

ENVIRONMENTAL HAZARDS

Lightning and HIRF can interfere with the operation of the aircraft electrical and electronic systems by coupling electromagnetic energy to the system wiring and components.

This electromagnetic energy can potentially upset system functions or even cause physical damage to aircraft systems. Lightning appears as a time limited high energy electromagnetic pulse thus having wide frequency spectrum while HIRF sources operate in specific frequency ranges.

Exposure to lightning and HIRF environment can result in numerous problems related to control and safety of aircraft. A fast changing RF environment can couple voltage and current transients into the electrical/electronic equipment or components. Use of composite materials and the presence of dielectric apertures has facilitated the penetration of external RF fields into the aircraft interior. The electrical and electronic systems may be susceptible to disruption to both command/response signals and operations mode logic as a result of electromagnetic interference. The trend towards increased reliance on electrical/electronic systems for flight and engine control functions, navigation, and instrumentation requires that the lightning and/or HIRF protection measures continue to be effective.



Typical protection afforded for lightning/HIRF is via the aircraft skin; voltage, and current protection at equipment; and wiring protection through use of shielding.

Fig 1 shows the static discharge systems fitted to Aircraft.



FIG 1

The static dischargers are also known as static wicks.

Environmental factors play a major role in accelerating electromagnetic protection degradation. Some of these are related to the environmental aspects of aircraft operation such as corrosion, mechanical vibration, and thermal cycling.

Other aspects include damage, subsequent repair and modifications. Therefore, age and operational, environment related, electromagnetic protection degradation, needs to be monitored. Frequency and quality of inspection methodologies need to be assessed against electromagnetic protection degradation due to repair, replacement, and use of dissimilar materials needs to be monitored.



ELECTROMAGNETIC PROTECTION AIRWORTHINESS AND SAFETY ASSURANCE

The following activities are elements of an adequate maintenance and monitoring programme used to assure continued protection of in-service aircraft electrical/ electronic systems against the effects of lightning and/or HIRF exposure, and those due to environmental factors.

AIRCRAFT MANUFACTURER (AM) and Original Equipment Manufacturer (OEM) electromagnetic protection plan, is a plan that has been developed by the AM/OEM to ensure that the aircraft will remain airworthy following exposure to an electromagnetic environment. This plan also accounts for electromagnetic protection degradation due to environmental factors such as corrosion, mechanical vibration, thermal cycling, damage, subsequent repair, and modifications.

An integral part of this plan is a developed sequence of measures that are required in the event of exposure to lightning and/or HIRF environment, as well as, maintenance/inspection due to ageing and environmental degradation of aircraft. The programme should address protection features such as: structural shielding, insulation degradation, electrical bonding integrity, etc.



SECTION 2 : MAINTENANCE PROCEDURES AND HIRF PROTECTION

INTRODUCTION

The initial aircraft maintenance programme is defined by the aircraft manufacturer as a normal part of the aircraft design and certification process. The maintenance programme is typically developed by the manufacturer together with regulatory authorities and aircraft operators.

Visual inspection is the first and generally most important step in HIRF maintenance. HIRF hardness degradation can be unintentionally introduced during normal maintenance and repair activities (eg paint overspray, errors in re-assembly of connectors). It is critical that the procedures contained in assembly and repair manuals be reviewed to ensure that established quality control inspection procedures can be relied upon to detect any incorrect installation which could impact the HIRF protection features.

Scheduled maintenance tasks should not be defined in order to protect against incorrect assembly and repair.

RELATIONSHIP BETWEEN DESIGN AND MAINTENANCE

Maintenance requirements for aircraft HIRF protection should be defined as an integral part of the initial aircraft maintenance programme, and adjusted as the programme is developed in accordance with service experience. The procedures can only be defined with a detailed knowledge of the design. The primary design features used to ensure aircraft systems operate satisfactorily when exposed to a HIRF environment involves three complementary hardening features:

Aircraft structure – (aircraft skin and frame)

Electrical wiring installation protection – (solid or braided shielding/connectors)

Equipment protection – (LRU case, electronics I/O protection)



The maintenance programme will depend on the specific aircraft system architecture, aircraft structure design, system design, and HIRF protection allocation.

Increased time between maintenance checks may be achieved by redundant protection. System architecture which results in system redundancy contributes to overall HIRF protection and can reduce the impact of protection degradation. If sufficient redundancy can be shown to exist then scheduled maintenance of HIRF protective features may not be required. However, degradation common to multiple levels of redundant protection, such as corrosion, must be considered.



SECTION 3 : MAINTENANCE OF AIRCRAFT STRUCTURE SHIELDING

INTRODUCTION

Since aircraft structure contributes to HIRF protection, this aspect should be considered when the aircraft maintenance requirements are developed and should be adequately addressed in the aircraft maintenance and structural repair manuals.

The following are examples of items which will typically need to be considered for inclusion in the maintenance programme to ensure acceptable protection retention:

Primary Structure:

Electrical continuity between main parts, eg wing/fuselage, pylon/wing, fin/fuselage, tailplane/fuselage, etc.

Secondary structure:

Electrical continuity between secondary structure, if used as a shielding feature and the

DEGRADATION

Degradation or failure modes of structure, both metallic and non-metallic, are assessed as a normal part of maintenance programme development. The most significant degradation effect that structure can have on HIRF protection arises from a decrease or loss of electrical continuity. This can be caused by corrosion, accidental damage, etc. Existing structural maintenance techniques (based primarily on visual inspections, supplemented as necessary by electrical bonding checks) have proven to be effective at detecting such degradation.

The items in Fig 1 may need to be addressed during visual inspection.

Where equipment racks, shelves and doorways are designed to contribute to the protection standard of installed equipment or systems there should be appropriate inspection procedures applied.



ITEM INSPECTION

Bonding Straps Check and/or inspect as necessary for:

Damage

Chafing

Deformation

Security of attachment

Corrosion

Degradation due to electrical discharge

Conductive Gaskets Check and/or inspect as necessary for:

Damage

Corrosion

Wear

Water

Brittleness

Hardening

Fluid contamination

Evidence of continuous contact between gasket and associated panel/enclosure

Flame Sprayed Surfaces Check and/or inspect as necessary for:

Damage

Erosion

Corrosion

Retaining screws in contact with surface

Raceways Check and/or inspect as necessary for:

Damage

Security of attachment and corrosion

FIG 1



MAINTENANCE OF ELECTRICAL WIRING INSTALLATION PROTECTION

The design HIRF analysis or test will have clearly identified the relative contribution of each of the main items which contribute to the overall wiring protection. Since the aircraft wiring installation features contribute to the HIRF protection this aspect should be considered when the aircraft maintenance requirements are developed and should be adequately addressed in the aircraft maintenance manual.

Electrical wiring protection is achieved mainly by shielding; shielding of bundles, or individual cable shielding. An integral part of wiring shielding is termination of the shielding. Note that this chapter addresses maintenance for wiring shields which contribute to HIRF protection.



The examples in Fig 2 are typical of items which may need to be addressed during visual inspection.

ITEM INSPECTION

Cable Shielding Check and/or inspect as necessary for:

Damage Chafing Birdcaging Wear Corrosion Fluid contamination

Bonding Straps Check and/or inspect as necessary for:

Damage Chafing Deformation Security of attachment Corrosion Fluid contamination Degradation due to electrical discharge

Connector Backshells Check and/or inspect as necessary for:

Damage Security of attachment Corrosion Fluid contamination

Cable Shield Pigtails Check and/or inspect as necessary for:

Damage Chafing Deformation Corrosion Wear Security of attachment

Twisted Wiring Check and/or inspect as necessary for:

Damage Chafing Deformation Wear

FIG 2



SECTION 4 : EQUIPMENT MAINTENANCE

INTRODUCTION

HIRF protective features may be designed into equipment in such a way to preclude meaningful in situ testing of the protective features. In a large percentage of these cases, the failure of a protective feature in the equipment will result in a loss of function. In that case, the protection feature will be restored to normal by the resulting maintenance action. However, in some cases, the protective feature’s failure is latent, and is not easily detected. In those cases, the reliability of those features should be orders of magnitude greater than the reliability of the equipment itself, which would result in a reasonable assurance that the protective features include design architecture, such as differential circuits. In those cases, no maintenance activity is required to verify the operation.

Normally, maintenance of HIRF protective features in equipment can be accomplished within the existing scope of maintenance activities for the equipment, without specific protective device testing. However, the equipment manufacturer may require a specific test of a HIRF protective feature, during equipment repair or maintenance, if he finds that test necessary to preclude a loss of HIRF protection. This is most appropriate for equipment which supports highly critical functions, such as equipment in a Level A system, where the HIRF protection failure is latent, or where the reliability of the HIRF protection feature is not significantly more reliable than the equipment as a whole.

AIRCRAFT MODIFICATION AND HIRF PROTECTION

During the design phase of a modification, an assessment should be made of the impact on the overall HIRF protection of the aircraft, to ensure that the overall electromagnetic hardness will not be compromised.

Changes in wiring type, connectors, bonding, shielding, and LRU modifications should be evaluated to ensure that they do not compromise the protection of Level A, B or C systems.

Where equipment performs a function which has a high level of criticality, the routing of the wiring should not be modified without re-assessing the impact on the protection that is already provided. The methods used for assessing the protection levels should be the same or similar to the methods used by the aircraft manufacturer or OEM for the design certification of the aircraft or equipment.

For systems which perform a function which has a low level of criticality, it should be verified that the overall EMC of the aircraft systems is not adversely affected by the modification.



NOTES:



SECTION 5 : EMI (ELECTROMAGNETIC INTERFERENCE)

Any output which should not be present is called interference. Interference has two possible sources – internal and external.

EXTERNAL INTERFERENCE

This normally exists in one of two forms:

Conducted interference

Radiated interference

CONDUCTED INTERFERENCE

In this form the equipment is subjected to interference via the cables in the aircraft. It may be interference on power supply lines or control lines or indeed on RF lines themselves. Equipments which are affected by this type of interference include ADF and HF. See later note.

RADIATED INTERFERENCE

This is created by interruptions of current in the aircraft, leading to the radiation of high frequency components. This high frequency radiation may be picked up by the aerials, which may be located in the radiated interference field. Equipments which may be affected include ADF and HF. See later note.

SOURCES OF EXTERNAL INTERFERENCE

ELECTRICAL SYSTEMS: these include brush gears, commutators, actuators, switches, relays, alternators, etc.

ENGINE SYSTEMS: this results from ignition systems principally eg faulty HT lead screening. It is very prevalent in light aircraft installations ie ADF.

INADEQUATE BONDING: this leads to a build up of static interference affecting low frequency equipments.

POOR QUALITY AIRCRAFT INSTRUMENTS: found in older light aircraft, eg turn and slip, affecting ADF.

INADEQUATE STATIC WICKS: results in interference to equipment from lightning and other forms of static.

FAULTY CONNECTIONS: all poor or faulty connections increase radiated interference and include plugs, AE and earth connections.

POWER SUPPLY INTERFERENCE: caused mainly by failure of components in power supply systems which introduce noise when they occur. Smoothing circuit breakdown is a frequent cause.



NOTE: The level of interference of external noise depends on the frequency content of the interference, ie the level of interference decreases as its frequency rises.

ELIMINATION OF EXTERNAL INTERFERENCE

The effects of interference can be minimised by the use of well sited aerials. (One of the factors giving rise to approved aerial positions.) However, generally the introduction of filters will give the greatest reduction in interference. These normally consist of suitable values of L and C being inserted in different configurations. Conducted interference can also be reduced by the inclusion of filters in the appropriate lines.

Radiated interference can be reduced by introducing the filters at the source of the interference, or as close as possible. This is frequently in the form of a capacitive static filter across the source of noise.

PASSIVE FILTERS – employing capacitors, inductors and resistors only –which are passive components.

ACTIVE FILTERS – An active filter can include passive components together with zener diodes, transistors etc. which are active devices.



SECTION 6 : ELECTROMAGNETIC INTERFERENCE FROM PORTABLE ELECTRONIC DEVICES

INTRODUCTION

Although the number of events that have been reported to be EMI related are extremely low compared to other reportable operational occurrences, the potential consequences of EMI are of concern.

EQUIPMENTS

Studies indicated that emissions from the early type of hand-held recording units, radios and hearing aids were believed not to be a threat to the onboard navigational equipment. Software changes were made, nonetheless and the number of reported EMI events decreased. By 1990, however, the number of people boarding aircraft with electronic devices had grown significantly and the low-voltage operation of modern aircraft digital electronics were potentially more susceptible to EMI. A look at the data recorded indicates that the most likely time to experience EMI emissions is during cruise flight.

IDENTIFICATION OF PERSONAL EQUIPMENT DEVICES (PEDS)

When EMI is suspected or known it is important to identify the specific type of equipment which is causing the interference. In the United States cellular phones are licensed by the Federal Communications Commission for land-mobile operation only. If used in flight, a mobile phone can disrupt aircraft equipment and could disrupt ground users over a large area. Of particular note: the number of events relating to computers, compact disc players, and phones has dramatically increased and these devices have been found to more likely cause interference with systems which control the flight of the aircraft.

Recognising an apparent instrument or autopilot malfunction to be EMI related may be difficult or impossible in many situations. In some reported events the aircraft was off course but indications in the cockpit displayed on course. Air traffic controllers had to bring the course deviations to the attention of the crews. It is believed that there are EMI events happening, that are not recognised as related to EMI and therefore not reported.

RADIATED INTERFERENCE

The culprit is electromagnetic emissions from the PEDs, which interfere with avionics systems, most commonly radio navigation and communications. Co-conspirators are the aluminium air-frame, which can act as a shield, a resonant cavity, or a phased array, and the sensitivities of the avionics. The radiation from the devices can couple to the avionics through the antennas, the wiring, or directly into the receiver. Systems should be designed to better withstand interference from PEDs.

In general manufacturers of affected devices have a responsibility to design immunity into their products.



OPERATING FREQUENCIES

The PEDs operate at frequencies from a few tens of kilohertz for AN radios to 133 MHz for laptop computers. The frequency and intensity of the radiation also depend on what mode the device is being operated in.

The frequency bands that avionics systems use cover the electromagnetic spectrum from a few kilohertz to several gigahertz.

From 108-118 MHz is the VHF omnidirectional range finder (VOR), a radio beacon that is used to navigate from point to point.

At 328-335 MHz is the glideslope system used during landings.

And above 1 GHz is the distance-measuring equipment (DME), which gauges the distance between the aircraft and a ground-based transponder and which is used throughout flight, from take-off to landing.

Also in the spectrum above 1 GHz are collision avoidance, global positioning, and cockpit weather radar systems.

Most at risk among these systems are those that have antennas located at various points outside the skin of the aircraft to pick up the navigation and communication signals. Those are the instruments that we cannot harden because they are built to receive very small signals. We rely on those sensitive receivers to pick up small signals in space, and that is the primary concern we have with carry-on electronic devices.

AERIAL PICKUP

Once the antennas have picked up the signals, they run through coaxial cables to communications or navigation receivers generally located below the floor of the cockpit. The output of those receiver boxes then goes to cockpit indicators or to other computers in the aircraft, or both.

The wires that connect the receivers to the indicators or computers are twisted, shielded pairs, or twisted, shielded triples, depending on whether the signal is digital or analogue.

Often the wires from the antennas to the receivers run along the fuselage inside the aircraft skin, passing less than a metre from a PED wielding passenger. The thin sheet non-conducting material that forms the inside of the passenger compartment, typically fibreglass, offers no shielding whatsoever between the PED and the wiring.

SHIELDING

Shielding could be damaged during servicing or could degrade over time. The effectiveness of shielding also depends upon good grounding. This is difficult to maintain over time because of the nature of aluminium’s surface chemistry; aluminium oxidises rapidly in air, thereby increasing the resistance of the electrical connection to ground. In that case, the wires could pick up interfering signals directly.

Even with shielding in mint condition, electromagnetic interference can still couple to the aircraft’s navigation or communication systems. Although the aluminium skin of the aircraft forms an excellent electromagnetic shield, it has holes through which the radiation can escape. In airliners, the biggest holes are the windows.



To further compound the problem, the aircraft’s aluminium skin is essentially a resonant cavity.

The result is a signal intensity that is even larger than it would be in free space.

CONCLUSION

This type of interference will continue until all PEDs hazardous to the aircraft systems is identified and restricted from use whilst in flight.

Care must be taken during maintenance, to ensure that shielding is not damaged or compromised even inside the cabin.



NOTES:



CHAPTER 10 : SOFTWARE MANAGEMENT CONTROL

SECTION 1 :

INTRODUCTION

For a number of years, aeroplane systems were evaluated to specific requirements, to the ‘single fault’ criterion, or to the fail-safe design concept.

As later generation aeroplanes developed, more safety critical functions were required to be performed, which generally resulted in an increase in the complexity of the systems designed to perform these functions. The potential hazards to the aeroplane and its occupants which could arise in the event of loss of one or more functions provided by a system or that system’s malfunction had to be considered, as also did the interaction between systems performing different functions.

This has led to the general principle that an inverse relationship should exist between the probability of loss of function(s) or malfunction(s) (leading to a serious Failure Condition) and the degree of hazard to the aeroplane and its occupants arising thereform. In assessing the acceptability of a design it was recognised that rational probability values would have to be established. This was worked out on the following basis:

Historical evidence indicates that the risk of a serious accident due to operational and airframe related causes is approximately 1 per million hours of flight. Furthermore, about 10 percent of the total can be attributed to Failure Conditions caused by the aeroplane’s systems problems. It seems reasonable that serious accidents caused by systems should not be allowed a higher probability than this in new aeroplane designs. It is thereby possible to require for new designs that the probability of a serious accident from all such Failure Conditions be not greater than 1 per ten million flight hours 1 10-7 per flight hour.

The difficulty with this is that it is not possible to say whether the target has been met until all the systems on the aeroplane are collectively analysed numerically.

AIRWORTHINESS NOTICE

Airworthiness Notice No. 45 was issued to give CAA recognition to RTCA/EUROCAE documents.

DO-178/ED-12

Software considerations in Airborne Systems and Equipment Certification.

The RTCA/EUROCAE documents have been updated to reflect industry’s experience.

The rigid correlation required between software verification effort and function criticality category has been relaxed.

A more flexible approach, in which design techniques are permitted to influence the software verification effort for a given function criticality is described in RTCA/EUROCAE documents.



The purpose of the Airworthy Notice No 45 is to extend CAA recognition to the RTCA/EUROCAE documents and to restate the applicable requirements with appropriate guidance material.

CRITICALITY

In addition to the normal assessment of system and/or function criticality, the responsible Design Organisation shall assign, to each software-based system or equipment, associated software levels which relate to the SEVERITY of the effect of possible SOFTWARE ERRORS within the system or equipment.

The software levels shall be agreed by the CAA.

FAILURE CONDITIONS

Failure Condition

The effect on the aeroplane and its occupants, both direct and consequential, caused or contributed to by one or more failures, considering relevant adverse operational or environmental conditions. Failure Conditions may be classified according to their severities as follows:

MINOR Failure conditions which would not significantly reduce aeroplane safety, and which involve crew actions that are well within their capabilities. Minor failure conditions may include, for example, a slight reduction in safety margins or functional capabilities, a slight increase in crew workload, such as routine flight plan changes, or some inconvenience to occupants.

MAJOR Failure Conditions which would reduce the capability of the aeroplane or the ability of the crew to cope with adverse operating conditions to the extent that there would be, for example, a significant reduction in safety margins or functional capabilities, a significant increase in crew workload or in conditions impairing crew efficiency, or discomfort to occupants, POSSIBLY INCLUDING INJURIES.

HAZARDOUS Failure Conditions which would reduce the capability of the aeroplane or the ability of the crew to cope with adverse operating conditions to the extent that there would be:

A large reduction in safety margins or functional capabilities

Physical distress or higher workload such that the flight crew cannot be relied upon to perform their tasks accurately or completely; or

Serious or fatal injury to a relatively small number of the occupants

CATASTROPHIC Failure Conditions which would prevent Continued Safe Flight and Landing.

The classification of Failure Conditions does not depend on whether or not a system or function is the subject of a specific requirement. Some ‘required’ systems, such as transponders, position lights and public address systems, may have the potential for only Minor Failure Conditions. Conversely, other systems which are not ‘required’ , such as flight management systems, may have the potential for Major, Hazardous or Catastrophic Failure Conditions.



SOFTWARE LEVELS

Fig 2 shows the relationship between the function criticality and the assigned software level.

AMJ 25

Criticality Category

FAA


RTCA/EUROCAE

Software Level

Effect on Aircraft and Occupants of Failure or Design Error

Minor Effect Non-Essential

Level D 1 Slight reduction of safety margin

2 Slight increase in workload (routine changes in flight plan)

3 Physical effects but no injury to occupants

Major Effect Essential Level C 1 Significant reduction in safety margins

2 Reduction in the ability of the flight crew to cope with adverse operating conditions impairing their efficiency

3 Injury to occupants

Hazardous /severe-Major Effect

Essential Level B 1 Large reduction in safety margins

2 Physical distress or workload such that the flight crew cannot be relied upon to perform their tasks accurately or completely

3 Serious injury to or death of a relatively small proportion of the occupants

Catastrophic Effect

Critical Level A 1 Loss of Aircraft

2 Fatalities

FIG 1



NOTES:



CHAPTER 11 : ELECTRONIC INSTRUMENT SYSTEMS

SECTION 1 : ELECTRONIC FLIGHT INSTRUMENT SYSTEM (EFIS)

INTRODUCTION

The electronic flight instrument system EFIS is a highly sophisticated flight director system (FDS) which uses cathode ray tube (CRT) technology to provide the pilot with attitude and navigation information.

The basic aircraft EFIS system as shown at Fig 1 consists of:

Two attitude director indicators (ADI)

Two horizontal situation indicators (HSI)

Three symbol generators (SG)

Two control panels

Light sensor

In some systems the attitude director indicator is known as the pilots flight display (PFD) and the horizontal situation indicator is known as the navigation display (ND).

FIG 1

ATTITUDE DIRECTOR INDICATOR (ADI)

The ADI is the upper a pair of cathode ray tubes fitted to both pilots front instrument panels. It presents, on an approximately 16 cm square colour screen, attitude (pitch



and roll), flight director commands, localiser and glideslope deviation as shown at Fig 2.

FIG 2

In addition the ADI displays autoflight system annunciations, groundspeed, airspeed, angle of attack, radio altitude and decision height. Attitude is the primary part of the ADI display and is derived from the inertial reference system when aligned and in the navigation mode, or when selected to attitude.

Flight director commands are presented to the pilot by the conventional method of command bars. A flight director with a failure in either axis causes the respective command bar to disappear. If both axis are unreliable both bars disappear and the FD flag appears, IRS alignment must be completed before flight director commands can be displayed. Auto-flight modes are usually presented in selected mode (white) and acquisition mode (green).

RADIO ALTITUDE

During approach, when between 2500 and 1000 ft, digital radio altitude is displayed on the ADI. Below 1000 ft radio altitude, the digital presentation is replaced by an analogue ring scale presentation and digital readout. Above 2500 ft radio altitude is blank.



DECISION HEIGHT (DH)

At DH plus 50 feet, a chime sounds at an increasing rate until DH is reached. The scale then changes from magenta to flashing amber for a couple of seconds. To cancel the flashing, a reset button is provided on the control panel.

HORIZONTAL SITUATION INDICATOR (HSI)

The HSI, at Fig 3 is a cathode ray tube may be fitted beneath or to the side of the ADI and presents plan view navigational information to the pilot.

FIG 3

NOTE: Active waypoints are coloured MAGENTA

Inactive waypoints are coloured WHITE

Wind direction is displayed with respect to map display orientation and compass reference.



HSI MODES

There are four modes which can be selected and presented on the HSI:

MAP

PLAN

VOR

ILS

MAP MODE

The map mode, at Fig 4, used in most phases of flight, in conjunction with a flight plan chosen by the pilot from the flight management computer; the HSI presents the information on a moving map display.

FIG 4

The symbol representing the aircraft is at the lower end of the screen and part of a compass is at the upper end. The pilot has also a facility to present high level and low level navigational aids, when in the map mode.

Weather information can be superimposed by independent selection on either the pilot’s or co-pilot’s HSI when in the MAP, VOR and ILS mode. The greatest intensity being displayed as red, reducing through amber to green. Wind speed and direction, an extremely desirable facility, is displayed in the bottom left hand corner of the HSI.



PLAN MODE

The plan mode, at Fig 5, is basically a facility that the pilot can use to check his selected route. In this mode the map is static and oriented to true north. The pilot can select through the route from the FMC. Weather radar information cannot be displayed in this mode.

FIG 5

NOTE: The centre waypoint on the screen is the first waypoint on the flight plan page currently displayed on the FMS. Moving through the flight plan changes the display, for example shown here the aircraft symbol is off screen.



VOR AND ILS

The VOR and ILS modes, at Fig 6 can be displayed in arc mode with range selection, or as a compass rose with conventional split bar guidance commands presented.

FIG 6

NOTE: When weather radar is displayed in expanded VOR or ILS mode, the scale shown applies only to the weather radar display.



HEADING INFORMATION

The HSI compass rose is automatically referenced to magnetic north when between 73N and 60S latitude with a NORM/TRUE switch in NORM and to true north when above those latitudes. On switching to TRUE the compass references true north regardless of latitude.

TEMPERATURE SENSING

Temperature sensing units are fitted to the ADI and HSI. They are set to LOW and HIGH value approximately 20C apart. If the LOW value is exceeded the sky and ground shading is switched off on the ADI alerting the pilot. The display is automatically restored when the temperature drops. However, if the temperature exceeds the high value the whole display switches off. The system will again automatically reset itself when it cools down.

LIGHT SENSORS

in order to ensure that the light intensity on the displays selected by the pilot is compatible with the ambient light on the flight deck, light sensors are fitted in close proximity to the displays.



SYMBOL GENERATOR

The ADI and HSI must have the information from the various aircraft sensors and equipment converted into suitable data for presentation. This is achieved by a symbol generator (SG). When the SG is powered displays are provided on both ADI and HSI. When not powered the displays are blank.

Various failure conditions may be displayed, as at Fig 7.

FIG 7

A blank screen results from power failure or over-temperature, or failure of relevant signal generator.

Partial loss of colour can result from over-temperature.

When information is not reliable or radio signals are not received, the display is removed.

If aircraft equipment fails a failure flag is displayed.

If a cross cockpit (comparator) disagreement exists in attitude, heading, or track the appropriate master warning and EICAS message appears.

CONTROL PANELS

The ADI and HSI control panels at Fig 8, provide control of symbology options, modes ranges and brightness for respective ADI and HSI displays and selection of radio altimeter decision heights.



FIG 8

COMPRESSION MODE

On most EFIS systems, if either the ADI or HSI cathode ray tube fails, the system will transfer to a compression facility, either automatically or selected by the pilot. In this mode, modified information from the failed CRT can be presented on the serviceable CRT.



COLOUR CODING

With the current EFIS, using 16 colour cathode ray tubes, the colour presentation on EHSIs is generally:

Red indicating warning

Amber indicating cautionary information, faults, flags



SECTION 2 : ELECTRONIC CENTRALISED AIRCRAFT MONITORING

INTRODUCTION

The Electronic Centralised Aircraft Monitoring (ECAM) system is part of the electronic instrument system (EIS) consisting of six screens providing the flight crew with assistance in system management in both normal and abnormal conditions. This operational assistance is given by the EFIS system plus two centre mounted CRT’s identified as:

The Engine/Warning Display (E/W)

The System/Status Display (S/S)

The physical layout of both CRT displays is dependent upon the flight deck layout; for example, they are shown one above the other (320 Airbus) however in the MD11 they are side by side, as shown at Fig 1.

FIG 1

PFD - Primary Flight Display (ADI)

ND - Navigation ( or Nav) Display (HSI)



ECAM SYSTEM ORGANISATION

The information fed to the CRT’s is derived from the various aircraft systems, and is processed via the following units as shown at Fig 2.

FIG 2

FLIGHT WARNING COMPUTERS (FWCS)

The FWCs alert messages, aural alerts, and vocal messages (Radio Height) are derived:

Directly from aircraft sensors or systems to generate RED WARNINGS

Through the system data acquisition concentrators (SDACs) for AMBER CAUTIONS.

The FWC’s also generate all messages which are displayed on the ECAM display units.

DISPLAY MANAGEMENT COMPUTERS (DMCS)

These units are common to EFIS/ECAM and generate the images displayed on the PFD, ND, E/W and S/S display units. They provide a similar function to the symbol generators of EFIS.

SYSTEM DATA ACQUISITION CONCENTRATORS (SDACS)

These units acquire data, process and distribute it to the:



DMCs for the display of engine parameters and system page data.

FWCs for generation of alert and procedure messages.

DISPLAYS

In normal operation, with no system failures, the ECAM system eases crew workload, by eliminating the need for frequent scanning of numerous system panels.

The ECAM provides warnings and cautions in plain English, when:

the aircraft flies out of its flight envelope.

failures are detected that affect the aircraft’s integrity.

ENGINE/WARNING CRT DISPLAY

The E/W display shows:

Engine parameters

Fuel on board

Slats and flap positions

Warning and caution messages, displaying a failure title and associated procedures, including any system affected by the failure.

Memo information, where no fault exists such as seat belt signs are on or checklists.

A status cue STS indicates that failures have been removed from the display, but may be called up if necessary.

SYSTEM/STATUS CRT DISPLAY

The S/S display shows:

System synoptic diagrams.

During routine system monitoring, synoptic diagrams may be automatically or manually selected to show the current flight phase information.

In the event of a system failure, the relevant synoptic diagram is automatically presented, whilst information relative to the failure is shown on the E/W display.

Any problems caused due to the failure, result in the relevant synoptic diagrams being presented in sequence in response to crew action.

Once all the information relative to the failure has been viewed, the display reverts to its normal display.

Status messages relative to the page selected are displayed.

ECAM CONTROL PANEL (ECP)

The ECP allows selection of the system pages or the status page on the S/S Display. Clear and recall allow actions associated with the warning messages displayed on the E/W Display. The ECP is shown at Fig 3.



FIG 3

OFF/BRT Knobs:

Control on/off and brightness for each ECAM display unit.

Plus automatic adjustment of the display light intensity with changing light conditions on flight deck; provided additional brightness control.

NOTE: When the upper display knob is turned to off, the E/W image is switched to the other ECAM display.

Each System Page Push Switch:

When depressed, the S/S display changes to the corresponding system page.

Illuminates after manual selection or when an advisory is detected.

RCL Push Switch

When depressed the warning/caution messages which have been suppressed by the CLR push switch, or by the flight phase inhibit, are recalled. If there is no warning/caution present, the indication NORMAL is displayed on the CRT for 5 seconds.

STS Push Switch

When depressed the status page is displayed on the S/S display. If there is no status message present, the indication NORMAL is displayed on the CRT for 5 seconds.

CLR Push Switch

Illuminates as long as a warning/caution message requiring action or acknowledgement is present on the ECAM display unit. As long as the CLR push is illuminated, pressing it, will change the ECAM display until the actions required by the ECAM have been followed.

ALL Push Switch

When pressed, all the system pages are displayed successively at 1 second time intervals. In case of ECAM control failure, the ALL push switch allows successive presentation of all system pages, with the facility to stop at the desired page for display.



EMERG CANC Push Switch

When depressed:

Any PRESENT AURAL warning is cancelled.

Any present caution is cancelled for the rest of the flight. The status page is automatically called and the following message presented: CANCELLED CAUTION and the title of the failure which was inhibited.

TO CONFIG Push Switch

When depressed a TO power application is simulated. This test will trigger a warning if the aircraft is not correctly configured for take off.

ATTENTION GETTERS

The purpose of the attention getters are:

MASTER WARNING LIGHT (RED). Indication of system faults which require immediate crew awareness and immediate corrective action.

MASTER CAUTION LIGHT (AMBER). Indication of system faults which require immediate crew awareness but not immediate corrective action.



ECAM SYSTEM FAILURES

In the event of an ECAM system failure, display functions can be manually switched between units to maintain full operational capability as shown at Fig 4.

FIG 4

COLOUR CODING OF DISPLAY

RED Warnings

AMBER Cautions

GREEN Normal long term operation

WHITE For function not in normal operation (switch in off position

BLUE For action to be carried out

TYPES OF FAILURE

INDEPENDENT FAILURE. This type of failure affects an isolated item of equipment, or system, without repercussions on any other systems in the aircraft.

PRIMARY FAILURES. This type of failure, in affecting an item of equipment or a system, causes loss of other systems in the aircraft.

SECONDARY FAILURES. This is the loss of an item, or system, due to a primary failure.



ECAM SEQUENCE

In case of failure detected by the ECAM the following may occur:

The E/W Display presents the warning and caution messages.

The master warning, or master caution lights illuminate.

The audio is triggered.

The S/S Display presents the affected system page.

The CLR push illuminates on the ECP.

After completion of the required corrective actions the crew must depress the CLR push button until the normal configuration returns and the clear push button extinguishes. An example of a typical fault sequence is shown in the following diagrams (Fig.5).



Example : No failure detected by the ECAM.

FIG 5



Example : Hydraulic Reservoir Overheat Failure

Cockpit Indications:

Single chime sounds

Master caution lights illuminate steady

Fault light illuminates on overhead panel

CLR PB illuminates on ECP

FIG 6

The upper display indicates that the blue electrical pump must be switched off. The lower shows the synoptic display for the hydraulic system.



The crew applies the ECAM required actions by switching off the Blue eng 2 pump, the blue hydraulic circuit is depressurised.

Cockpit indications:

Single chime sounds

Master caution lights illuminate steady

Fault/Off lights illuminates on overhead panel

CLR PB illuminates on ECP.

FIG 8

The crew depresses the CLR PB.

Cockpit indications:



CLR PB illuminates on ECP

Fault/Off lights remain on

FIG 9

The crew depresses the CLR PB a second time

Cockpit indications



CLR and STS PBS illuminates on ECP

FIG 10



The crew depresses the CLR PB a third time

FIG 11



NOTES:



SECTION 3 : ENGINE INDICATING AND CREW ALERTING SYSTEM

INTRODUCTION

Historically the engine parameters that require monitoring by the flight crew have been displayed on the flight deck utilising electro/mechanical instruments. In addition many different audio and visual warning systems have been used to alert crews to system malfunctions, dangerous conditions etc.

The Engine Indicating and Crew Alerting System (EICAS) consolidates engine indications, systems monitoring and crew alerting functions on two Cathode Ray Tubes (CRTs) mounted in the centre instrument panel. As a backup, discrete warning lights and a Stand-by Engine Indicator panel are provided. An over-view of the system is shown at Fig. 1

FIG 1



SYSTEMS FUNCTION

The EICAS includes two CRT display units, two computers and two control panels which provide the crew with:

Primary engine parameters – full time

Secondary engine parameters and warning, cautionary, advisory messages as required.

Normally only the primary engine parameters are displayed and the lower screen is blank, but secondary engine parameters or system status can be selected at any time via the Pilots Display Select Panel. The maintenance panel can be used to select maintenance displays, as required, on the ground.

The EICAS computers monitor over 400 inputs and through a comprehensive warning and caution system, provide a quick and unambiguous identification of problems as they arise. The alerting system is designed to communicate both the failure and the degree of urgency so that crew reaction is appropriate to the malfunction. When a parameter goes out of tolerance an Alert, Status or maintenance message is generated, depending on the urgency of the malfunction.

ALERTS

There are three levels of alert messages:

Warning messages reflect an operational or aircraft system condition which requires immediate crew awareness and immediate corrective or compensatory action.

Caution messages reflect a condition which requires immediate crew awareness and future compensatory action

Advisory messages are generated for conditions which require only crew awareness.

INHIBITS

Parts of the crew alerting system are inhibited or deactivated to prevent distractions during certain phases of flight. Multiple display messages of a similar nature are sometimes replaced by a single, more general, display message. For example, if only the forward or aft entry door is on the left side, a L FWD ENT DOOR or L AFT ENT DOOR ,message appears. If both doors are open, only a L ENTRY DOORS message appears.

Some display messages are also inhibited for a brief time period even though system lights are illuminated. This inhibit prevents normal in transit indications from appearing on the display. For example, the GEAR light illuminates as soon as landing gear retraction begins. However, the associated GEAR DISAGREE display message is inhibited for 25 seconds, allowing sufficient time for normal landing gear retraction to occur.



STATUS MESSAGES

Fig 2 shows status information displayed.

FIG 2

Status information is required to determine the readiness of the aircraft for dispatch, and is closely associated with the Minimum Equipment List (MEL). This is normally done before pre-flight check for allowable dispatch items, or prior to engine shut down to aid post flight technical log book entries. Use of the status mode is not required in flight, but can be useful in anticipating any necessary ground maintenance action. A status cue appears in the top left hand corner of the lower CRT whenever a change in status occurs with the status page not displayed. Display of status messages is obtained by pressing the status button on the Display Select Panel. The messages will appear on the right hand side of the lower CRT.

MAINTENANCE MESSAGES

These messages are designed to provide flight deck display of maintenance information for the use of flight deck crew post flight log book entries and ground crew. For convenience all status messages are repeated on the Maintenance Page, additionally all other significant information not covered by alert messages. Maintenance messages are obtained on the right hand side of the lower CRT by pressing the ECS/MSG button on the EICAS maintenance panel when the aircraft is on the ground.



DISPLAY FORMATS

During normal operations primary engine parameters only are displayed on the upper CRT the lower CRT is blank. The primary engine parameters allow the setting and control of thrust and comprise:

Engine Pressure Ratio EPR

N1

EGT

Secondary engine parameters are displayed on the lower CRT and can be called up at any time by pressing the ENGINE button on the pilot’s display control panel, if the ENGINE button is pressed a second time the display is cleared ie. returns to normal display. If during normal operation a secondary engine parameter becomes out of tolerance that parameter is automatically displayed, for both engines, with the out of tolerance parameter displayed in the appropriate alert colour (red or amber).

Fig 3 shows a typical display.

FIG 3



ALERT MESSAGES

Alert messages are displayed on the upper CRT in the top left hand corner.

Fig 4 shows the display.

FIG 4

Warning messages are colour coded red and can be removed from view only by correcting the malfunction.

Audio – Bell for fires – two tone siren for other conditions.

Caution messages are colour coded amber and appear below any warning.

Audio – single tone siren.

Advisory messages are also amber but are indented one space to the right, below any cautions, so as not to be confused with cautions.

Audio – none.

Up to 11 messages can be displayed. If more than 11 messages are generated the last message is removed and replaced by a page number, page 2 can then be displayed by pressing the CANCEL switch, page 1 can be recalled by pressing the RECALL (RCL) switch. In the event of an upper or lower CRT failure all engine indications are automatically transferred to the other CRT. This display is known as



the compacted mode. The compacted mode as shown at Fig 5 displays all the available information on one screen.

FIG 5

Thus the crew still retains full capability in the event of a CRT failure or if the lower CRT is being used for status displays (or maintenance displays on the ground)

In the compacted mode, the primary engine indications are shown in their normal form, secondary information and oil system indications are shown in digital form.



CHAPTER 12 : TYPICAL ELECTRONIC/DIGITAL AIRCRAFT SYSTEMS

SECTION 1 : FLIGHT MANAGEMENT SYSTEM

INTRODUCTION

The Flight Management System (FMS) is the heart of a modern aircraft’s electronic system. It gathers information from the aircraft sub-systems at a single point from which the pilot can, through a keyboard, manage the aircrafts lateral and vertical flight path (commonly called L-NAV and V-NAV). It reduces the need for the pilot to make calculations, refer to maps, and read manuals.

The primary function of the FMS is to provide performance management, navigation guidance and automatic flight control. A secondary function of the FMS is to provide inputs to flight deck displays to assist the pilot with manual flight; functions supported include the HSI map display and the positioning of bugs on the airspeed and EPR (N1) indicators.

SYSTEM CONFIGURATION

A typical FMS is configured as shown in Fig 1 and consists of two control and display units (CDUs) and two flight management computers (FMCs). The CDU incorporates a keyboard by which enables the pilot to communicate with the FMC.

FIG 1



Normally, each CDU and HSI map displays data from the related computer. Positioning of a FMC switch to the ALTN position connects the related HSI and CDU displays to the offsides computer. This level of interconnection makes all flight management functions available as long as one CDU and FMC is operating.

DATABASE

Each FMC holds a database which is divided into two major sections:

PERFORMANCE This section of database stores information on aircraft drag and engine characteristics, along with maximum and minimum altitudes and speeds. From this, and system fed information, the FMC calculates the pitch and thrust commands for the selected flight profile. Any changes in the performance database means changing the part number of the FMC.

NAVIGATION This section of the database contains full information on airways, VHF nav aids and waypoints within a specific area defined by the airline, and airfield information, including runways, SIDs, STARs, approaches and gate positions, is stored for the most frequently used airports.

The information in the database is updated every 28 days and covers a 56 day cycle.



CDU KEYS

It is through the CDU keypad, as at Fig 2, that the pilot communicates and gains information to the FMC.

FIG 2



A brief explanation of the uses of these keys follow.

LINE SELECT KEY (LSK) This key allows the transfer of data between the scratch pad and the line adjacent to that line select key. It is the main method of entering route details into the FMC.

INITIALISING/REFERENCE KEY (INIT REF) This key accesses the pages for initialising the navigation data prior to departure.

ROUTE KEY (RTE) This key selects the route page for entering or changing origin, destination, route or offset.

FIX KEY (FIX) This key selects the fix page for the creation of waypoints using intersections between the active route track and the bearing from an off-route fix.

DIRECT/INTERCEPT KEY (DIR INTC) This key selects the page with box prompts required for entering route from present position direct to waypoint, or to intercept designated course to waypoint.

CLIMB KEY (CLB) This key selects the climb page for evaluating and changing the climb schedule.

CRUISE KEY (CRZ) This key selects the cruise page for evaluating and changing the cruise schedule.

DESCENT KEY (DES) This key selects the descent page for evaluating and changing the descent schedule.

EXECUTE KEY (EXEC) A light illuminates on this key indicating a modification to the active route or vertical profile is armed. Selecting the key activates the modification and extinguishes the light in the key.

PROGRESS KEY (PROG) This key selects current flight and navigation data.

HOLD KEY (HLD) This selects the hold page for entering or exiting holding patterns.

DEPARTURE/ARRIVAL (DEP ARR) This key selects the page for entering or changing departure and arrival procedures for the airports on the active route.

LEGS KEY (LEGS) This key does the following: Selects the leg page showing the lateral and vertical details of each leg of the route.

Selects the page for modifying lateral and vertical waypoints

Selects the page for displaying HSI plan mode.

NUMERIC KEYS These keys enter numbers and symbols into the scratchpad for data entry via a line select key.

ALPHA KEYS These keys enter alphabetical characters into the scratchpad for data entry via a line select key.

CREW OPERATIONS

On the CDU the pilot can select a company route stored in the computer by using an alpha numeric code. If however the route is not stored in the computer the pilot can build up his own route by inserting the airports, waypoints and airways as required. Which ever method is used the pilot can visually check his selected route with reference to the CDU and HSI. (The HSI must be selected to the plan mode for route checking).



In normal operation one CDU is used to insert information while the other is monitored as a cross check to ensure the information is correct. The pilot entering the information does so via the scratch pad, at the bottom of the screen. Once the information is on the scratch pad it can be transferred to the relevant line by operation of the line select key. Information is supplied to the FMCs by the pilot filling boxes or dashes on the CDU display (Fig 3). When the required information is completed, the management system calculates the required data, whilst passing the information to the other FMC to act simultaneously. Data entry can only be made through one CDU at a time. Whilst entering data into one FMC, the second FMC becomes a slave awaiting to receive that data, so it cannot be accessed until the information has been activated or executed to both FMCs. When a FMC is switched on it will always take approximately 30 seconds to re-synchronise, during which time it carries out a BITE CHECK and checks that it has the same database as the FMC, and copies any information entered into computer at that time before staring up in dual. Any difference found between FMCUs would lead to independent operation.

The significance of the required data is indicated in two ways, as shown at Fig 3.

FIG 3

BOXES indicate data required for full L NAV and V NAV capability. This information must be entered before the FMC can function correctly.

DASHES indicate data required by the system to improve its performance, which should be entered if known. The system would however still operate without the information.

SYSTEM OPERATION

When the HSI is in the map mode it is fed with navigation information from its respective FMC, and with information from the pilot and the supporting systems the FMC calculates the aircrafts present position along with pitch roll and thrust commands required to fly an optimum flight profile. The systems which feed data into the FMC to enable it to carry out this task include:

Outputs are displayed to the crew on the ADI/HSIs; commands are passed to active flight control systems.



LATERAL NAVIGATION (L-NAV)

The lateral navigation from the FMC is mainly great circle guidance. The route can be monitored in flight with the HSI selected to the map position. In most aircraft the FMC determines its position using inputs from the IRS, DME, VOR and LOC receivers. It then uses this information to give steering commands along the active route.

After entering the gate position on the ground, when the aircraft moves the FMC now calculates its present position from the IRS. As IRS accumulates errors with time so will the FMCs. These can then be corrected by using radio updating of the FMC position. These position errors can be observed by the position of the aircraft on the HSI map. The systems which feed into the FMCs to enable it to carry out this task are:

Inertial reference system (IRS) HDG/Aircraft accelerations

Distance measuring equipment (DME) Slant range

VHF omni range (VOR) Bearing

Instrument landing system (ILS) Localiser centre line

Clocks Time

Air data computer (ADC) Altitude and TAS

VERTICAL NAVIGATION (V-NAV)

V-NAV may be engaged after completion of take off procedure, and provides automatic vertical navigation and thrust management functions. Climb and descent profiles are automatically flown, if required, for selected routes; speeds and power settings are automatically maintained to achieve economic fuel consumption. To follow thrust reduction vertical profiles the FMCs require information from the following system:

Fuel quantity and fuel flow systems Fuel/Weight computation

Air data computer SAT, TAT, AoA, CAS, Altitude and barometric settings.

Engine indications Feedback for thrust computations.

Pressurisation Descent profile

Weight switch Air/Ground sensing

Flaps/Slats Configuration

Clock Time



CDU MESSAGES

Messages are of two types:

Those affecting aircraft, or system performance and requiring possible crew action are of a high priority, and will also bring on the master caution display.

Those of lower priority (second level) which are displayed on the CPU indicating an FMC entry error, or the FMC requires additional data to perform its functions.

ANNUNCIATORS

Annunciators are lights which alert the crew when a change of FMS condition occurs. Typically they include:

OFFSET LIGHT

A white light which illuminates when the LNAV flight plan being followed is displaced from the active plan by a fixed amount left or right.

FMC FAIL LIGHT

An amber light which illuminates when, a failure has been detected in the related CDU or FMC. If the CDU fails, the display blanks; if the FMC fails the CDU may display information from the other FMC if active.

DISPLAY LIGHT

A white light which illuminates when, the displayed data on the CDU is not related to active route leg on climb/cruise/descent schedule.

FUEL MONITORING

Fuel data is fed to the FMC from the aircraft fuel quantity system and EICAS.

When the engines are started the FMC calculates the fuel used by monitoring fuel flow inputs. Under normal operating conditions, the FMC calculated value of fuel on board should agree with the aircraft’s fuel quantity systems de-totaliser reading. If the FMC determines a significant difference between the FMCs calculation and the de-totaliser, a quantity error is displayed on the scratch pad of the CDU.

The FMC continually estimates the amount of fuel remaining at destination. If the estimate is less than reserve fuel, an insufficient fuel message is displayed on the CDU.



NOTES:



SECTION 2 : GPS

INTRODUCTION

Navigation over long distances has suffered in the past from inaccuracies of inertial navigation systems. These systems required continual updating to eliminate drift errors.

The introduction of satellite navigation, on a worldwide scale, has allowed very accurate navigation to be achieved.

There are two satellite systems orbiting the earth:

NAVSTAR – Global Positioning System (GPS) (American Department of Defence)

GLONASS – Global Orbiting Navigation System (former USSR)

This module deals exclusively with the American system.

The NAVSTAR GPS has 3 functional elements:

A space segment

A control segment

A user segment

Fig 1 illustrates these segments.

FIG 1



SPACE SEGMENT

The space segment consists of a constellation of 24 satellites orbiting the earth at an altitude of just over 20,200 km (10,900 nm) in six strategically defined orbital planes. Three of the satellites are operating as spares with the remaining 21 in the constellation sufficient to provide global navigation coverage.

Fig 2 shows the orbital configuration of the satellites.

FIG 2

The objective of the GPS satellite configuration is to provide a ‘window’ of at least five satellites in view from any point on earth.

The satellites take approximately 12 hours to complete an orbit. The orbital position of each satellite is know precisely at all times.

Psuedo-Random Code

Each satellite transmits its position and precise time of transmission, plus a separate signal used by the receiver to establish range from the satellite. This is achieved by the satellite transmitting a navigation message and a unique encoded signal known as a PSEUDO RANDOM CODE. It repeats itself every millisecond and is used by the GPS receivers to recognise and track individual satellites for ranging purposes. The psuedo-random code uses a precision (P) code, also known as the Precise Positioning Service (PPS), which permits extremely precise position resolution.

A minimum of 3 satellites is required to determine a 2 dimensional fix, if altitude is known.

A minimum of 4 satellites is required to determine a 3 dimensional fix.



The navigation message contains information on satellite.

ephemeris (position)

GPS time reference

clock corrections

almanac data (orbital positions of the satellites)

date on system maintenance status

CONTROL SEGMENT

The controlling authority is the United States Department of Defence. By letter of agreement between the United States Government and the International Civil Aviation Organisation (ICAO) civilian access is permitted on a no cost basis for the foreseeable future.

The control segment includes monitoring stations at various locations around the world, ground antennas and up-links, and a master station as shown in Fig 1. The stations track all satellites in view passing information to a master control station which controls the satellites clock and orbit states, and the currency of the navigation messages.

Satellites are frequently updated with new data for the compilation of the navigation messages transmitted to system users.

USER SEGMENT (THE RECEIVER)

As previously mentioned, the receiver identifies each satellite being received by its unique pseudo-random code. It then starts to receive and process navigation information. Ephemeris data takes about 6 seconds to transmit, but almanac data takes about 13 seconds.

For this reason, almanac data is stored in the receiver’s memory. During operation, almanac data in the receiver is changed on a continuous basis. On start-up, the receiver recalls the data that was last in memory on the preceding shut down.

From this information and the stored almanac data, the receiver determines which satellites should be in view and then searches for their respective codes. It then establishes ranges to the satellites and by knowing their position, computes aircraft position, velocity and time. This process is known as PSEUDO-RANGING.

Range determination is a simple matter of measuring the interval between the time of transmission and the time of reception of each satellite P code and multiplying that time interval by the speed of light in free space. The time reference is provided by synchronised high precision atomic clocks in the satellites.

If the satellite transmits at 10:00:00 and this signal is received by the receiver at 10:00:02, it has taken 2 sec for the signal to travel from the satellite to the receiver. The speed of light is 300 x 106m/sec, so for 2 secs, the range is 2 x3 00 x 106m/sec = 600,000 Kms.



FIXING POSITION

A three-dimensional position in space (position and altitude) is accomplished by the receiver determining where it must be located to satisfy the ranges to four or more appropriately positioned satellites. A two-dimensional fix requires only three satellites in view of altitude is known. The synchronisation of the receiver’s time reference with that of the satellites’ is important to this process.

Timing errors are detected and eliminated by the receiver’s computer. Fig 3 shows a two-dimensional position established assuming the respective clocks are synchronised perfectly.

FIG 3

Fig 4 shows the situation if the receiver’s clock is one second fast.

FIG 4



The period between transmission and reception with respect to each of the three satellites interrogated will be sensed initially as taking one second longer. This will be represented as a gross error in all three ranges and thus, rather than producing a precise fix, will create a very large area anywhere within the receiving aircraft could be positioned.

The receiver’s computer senses this and immediately begins a trimming process until it arrives at an answer which allows all ranges to arrive at the one and only position possible. This process automatically eliminates the effect of receiver clock error for subsequent tracking and position fixing.

RECEIVER DESIGN

The capability of making range calculations to three, four or more satellites has an impact on the design, cost and accuracy of GPS receivers, ie. whether they are single-channel receivers providing multiple channels operating simultaneously.

RECEIVER AUTONOMOUS INTEGRITY MONITORING (RAIM)

RAIM is a special receiver function which analyses the signal integrity and relative positions of all satellites which are in view, so as to select only the best four or more, and isolating and discarding any anomalous satellites. At least five satellites must be in view to have RAIM find an anomalous situation, and six to actually isolate the unacceptable satellite.



MASK ANGLE

The masking function in the GPS receiver software ensures that any satellite which, although in view, lies below a fixed angle of elevation relative to the receiver, will be ignore. This is due to the range errors that will be generated because of the greater distances that its signals will have to travel through the Ionosphere and Troposphere to reach the receiver.

The fixed angle stored in the receiver is known as the Mask Angle. In some receivers it is selected automatically by the receiver depending on the strength of the transmitted signals at low angles of elevation, receiver sensitivity and acceptable low elevation errors. When fixed, it is typically set at around 7.5.

Fig 5 shows the mask angle.

FIG 5



RECEIVER DISPLAYS

Displays for the pilot vary from one GPS unit to another. Flight planning data is usually entered via an appropriate keypad on a control display unit (CDU) or control panel. The usual navigation information ie. position, track, groundspeed, estimated elapsed time and with a TAS input, TAS and wind, is displayed. The unit must also be capable of showing satellite status, satellites in view and being tracked.

OPERATING MODES

GPS receivers normally provide three modes of operation:

navigation with RAIM

navigation (two or three dimensional) without RAIM

loss of navigation (annunciated as ‘DR’ in some receivers).

GPS ERRORS AND LIMITATIONS

So far the errors we have covered are receiver clock error and how it is resolved.

There are other errors which can affect GPS performance, for example:

Interference

Because GPS signals are relatively weak, harmful interference can cause significant degradation in navigation or complete loss of navigation capability under certain conditions. With more and more extensive use of all bands of the electromagnetic spectrum, the potential for interference problems to occur has increased. The trend is likely to continue.

Interference to GPS operation can occur from electromagnetic influences on board the aircraft eg. insufficient shielding from VHF transmitters and other equipment, and from external sources eg. high powered radar, TV and FM stations in the vicinity of the receiver. To offset these problems, appropriate shielding systems are employed.



GEODETIC CONSIDERATIONS

We know that the closest shape that the earth resembles is an oblate spheroid. However, this is too gross an approximation for precision mapping purposes since the earth has in reality, a much more irregular shape.

Fig 6 shows a representation of geodetic mapping.

FIG 6

In other words, the shape of the earth at a particular locality will differ somewhat to the shape of the earth at another, as shown in Fig 6.

It is common practice to adopt a local ellipsoid, ie. an ellipsoid (mathematical model or geodetic datum), which provides the closest approximation to the shape of the earth or geoid over the particular area of interest.



ADVANTAGES OF GPS

World-wide use at all present speeds and altitudes

Very high accuracy

Continuously available

3-dimensional positioning

Unrestricted range

Space based

With INS makes other aids redundant

When full operational aircraft separation may be reduced

Available in simplified form for small aircraft

DISADVANTAGES

Uncertainty as to the effect of radio interference

The sky must be visible from the antenna

No immediate indication of failure, therefore not usable as a precision approach aid because of regulatory requirements.



NOTES|:



SECTION 3 : AIRCRAFT COMMUNICATION ADDRESSING AND REPORTING SYSTEM

INTRODUCTION

The Aircraft Communications Addressing and Reporting System (ACARS) is a data-link system which sends information between an aircraft and the airline ground base.

MESSAGE INFORMATION

ACARS messages are sent from the aircraft via a VHF communication transceiver and ground network to the airline ground operations base, and vice versa.

There is nothing new about sending messages between the aircraft and the ground. What makes ACARS unique is that messages concerning everything from the contents of the fuel tanks and maintenance problems to food and liquor supplies can be sent by ACARS in a fraction of the time it takes using voice communications, in many cases without involving the flight crew.

ACARS MESSAGE FORMAT

Each ACARS message is compressed and takes about one second of air time to transmit. Sending and receiving data over the ACARS network reduces the number of voice contacts required on any one flight, thereby reducing communication workload. ACARS messages are limited to a length of 220 characters which is adequate for routine messages. Longer messages, known as multi-block messages, can be sent as a series of separate ACARS messages.



ACARS NETWORK

The ACARS network is made up of 3 sections:

the airborne system

the service provider ground network

the airline operations centre

FIG 1



THE AIRBORNE SYSTEM

ACARS may be connected to other aircraft systems such as the digital flight data acquisition unit (DFDAU). The DFDAU collects data from many of aircraft systems such as air data, navigation, and engine instruments, and in turn makes the data available to the ACARS. More recent ACARS installations have been connected to the flight management computer, permitting flight plan updates, predicted wind data, takeoff data and position reports to be sent over the ACARS network.

Some of the communication applications of ACARS that are common to many airlines are:

crew identification

out of gate time

off the ground time

on the ground time

in the gate time

dispatch and weather updates

engine performance

fuel status

passenger services

maintenance information

ATIS (automatic terminal information service)



FIG 2

THE GROUND NETWORK

The ACARS ground system is made up of two parts

The first part is the radio and message handling network, which is controlled in the United States by Aeronautical Radio Incorporated (ARINC).

The service provider operates the remote radio sites, the ACARS front end processing system and the electronic switching system act like a post office and ensure that messages are routed to the correct addressee.

All ACARS messages originated in the United States are relayed from the remote sites at which they are received to the message handling centre in Chicago. The ground systems in other parts of the world work in a similar way to the US system.

THE AIRLINE OPERATIONS CENTRE

The ARINC network is connected to the airline operations centre by a landline. At the airline, the message handling is performed by a computer system which sends received messages to the appropriate department (operations, engineering, maintenance, customer services) for the appropriate action. Messages from an airline department, such as a request from engineering for engine data, follow the same route in reverse.



The ACARS in use vary greatly from one airline to another and are tailored to meet each airline’s operational needs. When satellite communication systems are adopted in the near future, ACARS will take on a truly global aspect.



SECTION 4 : TRAFFIC ALERT AND COLLISION AVOIDANCE SYSTEM

INTRODUCTION

The Traffic Alert and Collision Avoidance System (TCAS) is designed to provide aircraft with protection against collision with other aircraft.

TCAS II is required to interrogate other aircraft (rather than listen to replies elicited by ground interrogators) to allow accurate measurements of the range of proximate aircraft and to make TCAS operation independent of ground facilities. Such independence is necessary in oceanic and other non-radar airspace.

TCAS II SYSTEM

The TCAS II system:

uses a Mode-S transponder to communicate with each other

provides vertical resolution advisories.

USE OF MODE-S TRANSPONDER

The Mode-S transponder provides the two way data link which allows TCAS-II equipped aircraft to co-ordinate their RAs. This data link may also be used to seek data from other aircraft to aid in accurate determination of the level of threat. The calculations to support RAs is performed in the TCAS-II unit.

ANTENNA DIVERSITY

TCAS-II installations require top and bottom antennae. The top antenna must be directional and have direction finding capability.

The bottom antenna may be either omni-directional or directional.

The associated Mode-S transponders installations also require top and bottom antennas. The Mode-S transponder has two complete receivers, one per antenna. The reply to an interrogation is transmitted via the antenna which received the interrogation with greater signal strength.

The total of two top and two bottom antennas are required to ensure timely detection and adequate communication reliability regardless of the closure speed and relative position of the aircraft to each other.


A RESOLUTION ADVISORY (RA) provides positive information to the pilot in the form of action to be taken to avoid the other (threat) aircraft.


TRAFFIC ADVISORY

Once a target aircraft is acquired, the TCAS II unit continuously monitors time-to-collision. Since TCAS II systems provide both a visual (instrument) and aural indication of approaching aircraft, the crew must be trained to respond to these combined inputs.

In many situations the first indication would be an aural warning of TRAFFIC TRAFFIC as the target aircraft enters the Traffic Advisory limit which for TCAS II is 45 SECONDS from collision.

Fig 1 shows a typical display for a Traffic Advisory.

FIG 1

The indication gives information relative to the intruder aircraft from the host aircraft.

The symbol for the intruder aircraft may vary dependent on system software.

The arrow indicates the vertical trend of the intruder:

The indicates climbing

The indicates descending

No arrow indicates level flight

The digital readout indicates the height of the intruder to the host aircraft in hundreds of feet.

The – minus sign indicates the intruder is below

The positive sign indicates the intruder is above



RESOLUTION ADVISORY

A TA is normally issued 5 to 20 seconds in advance of the resolution advisory (RA).

The RA is issued when time-to-collision is between 15 and 35 seconds. (The term collision is not usually used, rather the term ‘closest point of approach’, abbreviated CPA, is generally used).

TCAS II generates RAs in combined aural and visual commands to create a vertical miss distance of 400 ft to 700 ft. This is to minimise the generation of additional encounters with aircraft on adjacent Flight Levels.

TCAS II reassess the encounter once per second, as the situation changes both the sense and required vertical rate of the RA may change. Changes to the sense of a RA are most likely to occur if the threat aircraft changes its vertical rate or an additional threat aircraft is detected. For TCAS II to be effective the pilot must act on changes to the RA.

For example, in a situation where the target aircraft is approaching from below, the TCAS system will command a climb. In such a case the aural instruction would be CLIMB CLIMB accompanied by VSI indications showing RED for all negative rates up to + 1,500 fpm and GREEN from + 1,500 fpm. In this case the pilot should smoothly establish a rate of climb of at least 1,500 fpm.

In such an example, as the geometry of the two flight paths changes, so too will the value of the red and green vertical rate VSI sectors.


To maintain adequate separation, the pilot must maintain vertical speed in the green sector.


Fig 2 shows a typical TCAS II display.

FIG 2

An intruder is located inside the dotted 2 nm range ring. It is 300 ft low and climbing.

A green sector on the VSI is displayed between + 1500 and + 2000 fpm.

The aircraft is now climbing at 1800 fpm.

As the conflict is being controlled, aural warnings will change to MAINTAIN VERTICAL SPEED and finally CLEAR OF CONFLICT.



RESOLUTION ADVISORY ACCURACY

The Mode S transponder allows complex calculations required for resolution advisories to be completed in a very short time. When two TCAS II equipped aircraft are interrogating each other using Mode S, a high degree of resolution accuracy is achieved.

The provision of a Mode S transponder also allows the TCAS II system to supply information to Mode S compatible air traffic radar systems.

TCAS CONTROLLER

Control for the TCAS II system is normally provided on a combined transponder/TCAS controller.

Fig 3 shows a typical control panel.

FIG 3

EFIS equipped aircraft can display TCAS II RA pitch commands on the ADI, and TA and RA traffic on the HSI when TFC is selected on the EFIS control panel.

TCAS AND ALTIMETRY ERRORS

TCAS uses the altitude information of both own and threat aircraft transponder pressure altitude encoder to determine the most appropriate escape manoeuvre. Should either of these encoders provide erroneous data, the accuracy of TCAS II TA display and TCAS II RAs will be adversely affected.



SUMMARY

The following points summarise the use of TCAS:

TCAS provides no protection against aircraft which either do not have a transponder or the transponder is not switched on.

A Mode A/C transponder with pressure altitude encoder is sufficient to provide maximum protection in an encounter with a TCAS II equipped aircraft.

TCAS II can only generate RAs if the threat aircraft is transponding Pressure Altitude.

Transponder control panels have provision to switch off pressure altitude reporting. This provision is used to allow pilots to disable pressure altitude reporting when the pressure altitude data is known to be erroneous.

To maximise the effectiveness of TCAS, all aircraft should operate at all times with their transponder on and altitude reporting enabled.

Altitude reporting accuracy is verified by ATC. When an aircraft enters controlled airspace and is radar identified, the controller uses actual altitude reported by the pilot to validate the pressure altitude which is received by ground radar and displayed by the controller. Should this validation fail, the pilot is instructed to disable altitude reporting, the transponder should remain on. The failure should be recorded in the maintenance log.



SECTION 5 : FLY-BY-WIRE

INTRODUCTION

Fly-by-wire aircraft use electronic control systems to control the pitch, roll and yaw in flight instead of mechanical push-pull tubes, cables and pulleys etc.

TYPICAL FLY-BY-WIRE SYSTEM

In a fly-by-wire control system, the pilot’s stick is connected to transducers which convert stick movements into electrical signals.

These signals are processed by Flight Control Computers and sent to Powered Flying Control Units (PFCUs) to hydraulically move the flying control surfaces.

Fig 1 shows a basic fly-by-wire layout.

FIG 1

The Airbus A320 use fly-by-wire digital technology using a side stick controller.

The Boeing 777 uses fly-by-wire digital technology using a conventional control column.

The Concorde uses an analogue fly-by-wire system.

Actuators control the movement of control surfaces such as:

elevators

ailerons

spoilers

SYSTEM SAFETY

Signals are converted to digital data in the Flight Control Computers.

The Flight Control Computers are also connected, via data buses to other computers including the Autopilot Computer, receiving and providing information.

With an input demand, the Flight Control Computer decides if a manoeuvre is able to be carried out to keep the aircraft in a safe flight profile.

If the demand is acceptable the Flight Control Computer will then send a signal to the PFCUs to move the control surfaces.

FLY-BY-WIRE ACTION

Fig 2 shows a fly-by-wire layout.



FIG 2

The Flight Computer shows inputs from either the:

autopilot computer

side stick (transducers)

The computed order is fed to a hydraulic actuator which moves the control surface.

Feedback from the hydraulic actuator is fed to the Flight Control Computer to control the amount of demand to the actuator.

Feedback from the control surface (response) is also fed back to the Flight Control Computer to ensure that the output matches the demand.

If the aircraft is flying using Autopilot and a demand is input, using the sidestick, the auto pilot disengages and is flown manually.

When the aircraft control surfaces have reacted to the demand and the stick controller released, the autopilot holds the aircraft to the new flight parameters.



SECTION 6 : AIR DATA COMPUTER

INTRODUCTION

Air data systems and air data instruments depend on pitot pressure, static pressure and air temperature sensing.

Pitot air pressure is the pressure of the outside air developed due to the motion of the aircraft through the air.

Static air pressure is the pressure of the outside motionless air at the location of the aircraft.

Total air temperature is the static air temperature plus the rise in temperature due to the pitot effect. Increasing the air pressure increases the temperature.

PITOT STATIC SENSING

The locations and shapes of pitot and static sensors vary dependent on the type of aircraft and system that is fitted.

Fig 1 shows a flush mounted static port

FIG 1


Pitot and static pressures are equal in a parked aircraft


Fig 2 shows a combined pitot static probe.

FIG 2

Fig 3 shows typical locations of fit on an aircraft.

FIG 3

Pitot probes are liable to icing, under some conditions, and it is necessary to use a built-in heater to keep it ice-free.

Flush mounted static ports may also be heated where necessary.



TOTAL AIR TEMPERATURE SENSING

Fig 4 shows a Total Air Temperature (TAT) probe.

FIG 4

The TAT probe is constructed similar to a pitot pressure probe, only more complicated. There is a need to provide de-icing heat to the probe.

The TAT probe requires some air flow to avoid heating the measured air. The flow of air is so small through the metered orifices, there is only a small influence on the pitot effect.



TYPICAL CENTRAL AIR DATA COMPUTER

Fig 5 shows a block diagram of a Central Air Data Computer (CADC)

FIG 5

The inputs are pitot and static pressures and total air temperature.

From these inputs, many parameters can be calculated in the 4 modules that comprises the CADC.

Altitude Module

Indicated Airspeed Module

Mach Module

True Air Speed Module.



CENTRAL AIR DATA COMPUTER SCHEMATIC

Fig 6 shows a schematic of the 4 modules within the analogue CADC.

FIG 6

ALTITUDE MODULE

Fig 7 shows the internal workings of the altitude module.

FIG 7

The static pressure is applied to a sealed diaphragm in a static pressure chamber.



Altitude Rate

The diaphragm is connected to one side of an EI bar with the output from the E pick-off.

If the aircraft is parked or holding altitude, static pressure is constant.

The E pick-off armature is in the neutral position.

If the aircraft takes off, static pressure decreases progressively.

The armature is no longer at NULL.

An error signal drives the servo motor which drives a tacho generator. This turns the gear train, causing the I bar to take up a neutral position so removing the error output to the motor.

The amount of altitude rate output is proportional to the rate of climb of the aircraft.

If the aircraft descends, the servo motor drives in the opposite direction, keeping the I bar armature neutral. The tachogenerator runs in the opposite direction with a phase reversal.

The PHASE determines if the aircraft is CLIMBING OR DESCENDING the amplitude determines how FAST.

Altitude

The servo motor also drives, through the gear train, a potentiometer wiper arm and a course and fine synchro pair.

As the aircraft altitude changes, the potentiometer wiper arm changes and the positions of the coarse and fine synchro rotors change.

The altitude outputs can be used to provide information to relevant systems.

The potentiometer output provides altitude information to the Mach Module.

Altitude Hold

The altitude error synchro is held in a neutral position until an altitude hold signal disengages the holding clutch.

Once the clutch is disengaged, any change in aircraft altitude develops an error signal.

The error signal, to the autopilot or flight direction system in altitude hold, will be one phase for going above the desired altitude and the opposite phase for being below the desired altitude.

The amount of error amplitude is dependent on the amount of deviation from the desired altitude.

ATC

The analogue altitude signal is converted to digital and is used by the ATC transponder.



Cabin Pressure

The potentiometer outputs altitude information to the cabin pressure computer which maintains the desired pressurisation of the aircraft with respect to the outside air pressure.

INDICATED AIR SPEED MODULE

The pitot pressure is applied to a diaphragm with static pressure surrounding it in a sealed pressure chamber.

The difference between pitot and static pressure surrounding it in a sealed pressure chamber.

The difference between pitot and static is produced.

An E-pick-off drives a servo motor which drives

Q pots for gain control in flight directors and autopilots

A synchro to give remote readings of indicated airspeed

A potentiometer to supply and input to the Mach Module.

MACH MODULE

The Mach Module produces Mach information by combining indicated airspeed and altitude.

The speed of sound is dependent upon the temperature of the air.

To simplify the system construction, altitude is substituted for temperature. The air temperatures above 25,000 ft are fairly constant. It is therefore possible to use altitude instead of temperature above 25000 ft.

The speed indicated in a Mach meter is indicating the aircraft speed relative to the speed of sound.

The Mach Module combines the imps from the Altitude Module and Indicated Air Speed Module.

The signal produced drives a servo motor which drives 3 potentiometers.

One is a follow-up as feedback for the servo motor drive circuit

One produces Mach as an output to systems such as the autopilot

One provides an output to the True Air Speed Module.

True airspeed and indicated airspeed are the same at sea level.

The difference between true airspeed and indicated airspeed varies dependent on temperature and altitude.



A speed of 400 knots at Sea Level = 450 knots at 10000 ft

= 550 knots at 20000 ft

A speed of 600 knots at Sea Level = 525 knots at 36000 ft.

TRUE AIR SPEED

The module develops true airspeed by combining Mach information and Total Air Temperature information.

Static Air Temperature (SAT) is also produced from the Total Air Temperature.

TAT = SAT

SAT = TAT -

TAT is produced from the probe.

TAS is produced from the Mach Module.

DIGITAL AIR DATA COMPUTER

Fig 8 shows a typical digital ADC

FIG 8

The digital ADC uses digital computing and electronic circuits rather than servo motors.

Analogue inputs are converted to digital and any analogue output required is converted to analogue from digital using converters.



CHAPTER 13 : SUPPLEMENTARY REVISION QUESTIONS

INTRODUCTION

The following questions are intended to be answered using the ‘Open Book’ method by finding the information in the notes.

QUESTIONS

SECTION 1

1 Complete the table shown below:

Decimal Binary Octal Hexadecimal

181

65

1011010

300

6E



SECTION 2

1 Complete the following truth tables:

B A O/P

0 0

0 1

1 0

1 1

B A O/P

0 0

0 1

1 0

1 1

B A O/P

0 0

0 1

1 0

1 1

2 Draw a logic diagram for the following boolean expression:


i) NAND

ii) OR

iii) XOR


3 Draw the logic gate symbol for the following boolean expressions:

i)

ii)

ii)

4 Positive logic is when the active state is a 1, negative logic is when the active state is what?

5 Write down the boolean expression for the truth table below:

C B A O/P

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0



6 Draw the logic gate circuit that is equivalent to 2 switches in parallel followed by 1 switch in series:

7 For the circuit above, draw an equivalent circuit, using NAND gates only:

(show truth table and/or boolean expression to assist with this question)



SECTION 3

1 What advantage does a R-2R network have over a weighted resistor network when used in a DAC:

2 An Approximation ADC conversion time is dependent on what?

3 A 12 bit Approximation ADC requires how many clock pulses to produce the correct digital output representing any analogue input?

4 In a Fast Parallel ADC (or Flash Converter) with 20 comparators each with a step voltage of 0.5 volts between them. What is the maximum detectable voltage:

5 Write down 1 disadvantage of a Fast Parallel ADC:

6 In a 4 bit DAC with a quantisation interval of 0.5 volts and an input code of 01012. What is the quantisation level?



SECTION 4

1 In an ARINC 429 data bus, the data word is in 5 parts. Complete the following table:

Part Bits Purpose

Label

9 and 10

11 to 28

Sign Status Matrix

32 Error checking

2 The ARINC 429 uses 32 bit serial/parallel data (delete incorrect one).

3 What type of shielding is used on ARINC 429 data bus cables?

4 In an ARINC 429 data bus system, how is synchronisation achieved between data words?

5 What are the 3 voltage states used by the data word in an ARINC 429?



SECTION 4

1 Complete the following table:

ARINC 429 ARINC 629

Cable protection Shielded

Speed

Transmits data Two way

2 In an ARINC 429 data bus system, how many transmitters and receivers are required in each LRU, for 2 LRUS to transmit and receive data from each other?

3 In an ARINC 429 data bus system, what is the binary code for a label of 205?

4 In an ARINC 429 data bus system, what are pad bits used for?

5 In an ARINC 429 data bus system,……………………………parity is used, therefore the number of bits in the data word must count up to an ……………...……….number.



6 In an ARINC 629 data bus system, how many word strings are available?

7 In an ARINC 629 data bus system, how many words does a word string contain?

8 In an ARINC 629 data bus system, how many words does a word string contain?

9 In an ARINC 629 data bus system, how many labels are used for each data word string?

10 In an ARINC 629 data bus system, the stub cable consists of:

11 …………………..set(s) of unshielded/shielded twisted pair of wires (delete as appropriate).

12 In an ARINC 629 data bus system, what size of resistor terminates the data cable?

13 In an ARINC 629 data bus system, how many bits are used for:

a)a label

b)each data word



14 In the ARINC 629 data bus system, how many transmissions can be on the data cables at any one time.



SECTION 5

1 In a computer system, each memory location is accessed by putting the memory location on which bus?

2 In a computer system, the read/write commands are controlled by which bus?

3 In a computer system, what is the purpose of the ALU?

4 In a computer system, is the data bus one way or two way?

5 In a computer system, is the address bus one or two way?

6 In a computer system, what is the purpose of the control signal: MEMW

7 In a computer system, a ROM is: volatile or non-volatile?

8 In a computer system, a RAM is: volatile or non-volatile?



9 Complete the following table:

Type Programme Method

No of times it can be programmed

Erasable or not

Reset/healed method

ROM Mask programmed

PROM

EPROM YES Electrical current

EEPROM Many times

10 In a computer system, a RAM is: volatile or non-volatile?

11 What does the term ‘random access’ mean?

12 In a computer system, read and write functions can be carried out by ROM or RAM or both (choose).



SECTION 6

1 A segment of an LCD is energised when the square wave between terminals are

……………………………………………….phase.

2 In an LCD, light passes straight through the crystal when it is:

energised/de-energised (delete incorrect one).

3 How many wires are required for a multiplexed 7 segment LED display that has 6 displays?

4 What limits the current to an LED?

5 How is the cathode of an LED identified?

6 In a CRT, which plates move the electron beam vertically?

7 In a CRT, what is the purpose of the shadow mask?



8 What is a luminophore in a CRT?

9 What 3 colours are produced on the luminophores of a CRT?

10 How many guns does a colour CRT have?

11 How is the electron beam produced in a CRT?

12 What stops colour distortion on the CRT?

13 In a TFT display what is the purpose of the capacitor?



SECTION 7

1 Which type of connection can be used for a permanent connection of a fibre optic cable?

2 List the disadvantages of fibre optics when compared to wire cables.

3 List the advantages of fibre optics when compared to wire cables.

4 What is the purpose of fibre optic couplers?

5 State 2 types of coupler.

6 Complete the following table for fibre optic cabling.

Link How many directions?

Simplex

Bi-directional but not at the same time

Full Duplex



7 What is destructive interference?

8 What is constructive interference

9 There are 3 layers in a fibre optic construction, list them

a)

b)

c)

10 In a fibre optic cable, the core is………………………………..dense than the………………………………………..

11 What 2 materials are used to construct a fibre optic?

12 What is monochromatic?



SECTION 8

1 An ESDS device may be damaged due to static electricity. Complete the following.

a) An ESDS may be damaged by discharges as little as:

…………………………………………………………

b) Most people cannot feel a discharge below………………………………..

c) A visible spark is typically over…………………………………………….

2 How can a technician remove any static he may have acquired?

3 What is the purpose of a large resistor in the earth strap?

4 How can a technician remove a static charge from tools?

5 How must ESDS equipment be transported?



SECTION 9

1 Who is responsible for HIRF design in an aircraft?

2 What is the main inspection technique to discover HIRF protection degradation?

3 What is the purpose of static wicks on an aircraft?

4 What is the purpose of bonding of an aircraft?

5 How can cables be protected from radiated interference?

6 What is a passive filter?

7 Radiated interference can be reduced by introducing……………………………. at the…………………………………………..of the interference, or as close as possible.



8 What are the two types of interference?

9 What types of degradation need to be checked for on bonding straps?

10 What is a HIRF primary structure?

11 What is a HIRF secondary structure?



SECTION 10

Complete the following table.


Software Level

Effect on Occupants

Effect on crew efficiency

Safety

Minor

C

Large reduction

in safety margins

Fatalities



SECTION 11

1 A basic EFIS system consists of:

a)…………………………………display (2………………..and 2….……………..)

b)………………………………..symbol generators

c)………………………………...control panels

d)……………………………..…light sensors

2 What is the purpose of the centre symbol generator in a basic EFIS system?

3 In a basic EFIS system what modes are available?

a)………………………………………………….

b)………………………………………………….

c)………………………………………………….

d)………………………………………………….

4 For a basic EFIS system, complete the following table for radio altitude display at specific heights.

Height Display on screen

above

between Digital only

below 1000 ft



5 In a basic EFIS system, between which latitudes can true and magnetic north be selected on the HSI?

6 In a basic EFIS system, what indications will be present should a display cooling fail?

7 What is the purpose of the brilliance control sensor to EFIS displays?

8 In a basic EFIS system, red indicates a?

9 In a basic EFIS system, amber indicates a?



10 What is the purpose of the ECAM system System/Status display?

11 What action is required by the crew for the following, in an ECAM system?

a) red warning

b) amber caution

12 In an ECAM system describe:

a) an independent failure

b) a primary failure

c) a secondary failure

13 In an EICAS system, what action is required by the crew for?

a) a warning message

b) a cautionary message

c) an advisory message



14 In an EICAS system, what happens should one of the displays fail?

15 In an EICAS system, what message is in amber and indented to the right?

16 In an EICAS system, how many messages can be held on each page?

17 In an EICAS system, what information is displayed full time?



SECTION 12

1 In a Flight Management System, the primary function is to provide?

a

b

c

2 In a Flight Management System, the secondary function is to provide?

3 In a Flight Management System, what is the purpose of the ALTN switches?

4 In a Flight Management System, what information is fed into the FMCs?

1

2

3

4

5

6

7

8



5 In a Flight Management System, what is CDU an abbreviation for?

6 In a Flight Management System, the database is split into what 2 sections?

1

2

7 In a Flight Management System, the database is updated every………………. days and covers a…………………day cycle.

8 In a Flight Management System, when one CDU is used to insert information, the other is?

9 In a Flight Management System, information is input through the CDU, what is indicated by?

Boxes

Dashes

10 In a Flight Management System, what are annunciators used for?

11 In a Flight Management System, fuel is monitored in the FMC, what is checked under normal conditions?



12 In a GPS system, how many satellites are normally used?

13 In a GPS system, name the 3 functional elements?

1

2

3

14 In a GPS system, what is the purpose of RAIM?

15 In a GPS system, how long is the orbit of a satellite?

16 In a GPS system, how many satellites are required for?

1 a 2 dimensional fix

2 a 3 dimensional fix

17 In an ACARS system, what frequency range is used for transmissions?



18 In an ACARS system, what 3 sections make up the network?

1

2

3

19 In a TCAS system, what is a Traffic Advisory?

20 In a TCAS system, what is a Resolution Advisory?

21 In a TCAS system, what is the Mode-S transponder used for?

22 In a TCAS system, in which direction does the aircraft fly to avoid a collision?

23 In a TCAS system, an intruder aircraft with an arrow pointing down and a digital readout of +400 means?



24 In a Fly-by-Wire system, what control surfaces are controlled by actuators?

1

2

3

25 In an ADC , what is pitot air pressure?

26 In an ADC, what is static air pressure?

27 In an ADC, what is Total Air Temperature?

28 In an ADC, what happens to the static pressure when the aircraft takes off?

29 In an ADC, how is altitude derived?

30 In an ADC, name the 4 modules?

1

2

3

4



31 In an ADC, what is the difference between True Air Speed and Indicated Air Speed at sea level?

32 In a Digital ADC, what is used for calculations rather than servo motors?



NOTES:


Documents

Copy of Mod 5 - Digital Techniques & Eis (Basic)