Controlling Robot by Gsm Sms

8/16/2019 Controlling Robot by Gsm Sms

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CONTROLLING ROBOT BY GSM SMS


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(ABSTRACT)

AIM:

The main aim the project is to design “CONTROLLING ROBOT BY

GSM SMS”.

COMPONENTS:

LPC2148 (ARM!" #$M modem" %ri&er 'C and %C motor.

EXISTING METHOD:

'n the eisting method )e can contro* the ro+ot +, -sing the R

remote contro* )hich cons-mes more po)er and )hich is not sec-red /or )ire*ess

transmission o/ commands /or contro**ing ro+ot. 0e cannot -se this ro+ot )here

radio /re-enc, signa*s are not present.

PROPOSED METHOD:

Mo+i*e ro+ots per/orm &ario-s )a,s o/ tass to ser&e h-mans s-ch as

home ro+ot" inspection ro+ot" sec-rit, ro+ot" schoo* ed-cation ro+ot" reha+i*itation

ro+ot" and so on. The con&entiona* mo+i*e ro+ots ha&e -sed /ront3steering and rear3

)hee* dri&ing mechanism to response a** needed ro+ot o+&io-s motions" +-t the

motion restriction is a major pro+*em in the -se o/ s-ch mechanism. The

contro**ing the R5T +, #$M $M$ is a most s-ggested mechanism /or mo+i*e

ro+ot" )hich ha&e the capa+i*it, o/ changing directions /or the *ong range

distances.

'n this project )e are going to contro* the R5T +, -sing #$M $M$ /rom

the remote *ocation. Commands recei&ed /rom the #$M mo+i*e )i** +e gi&en to

the #$M recei&er. 0hose signa*s )i** +e gi&en to the ro+ot )hich consists 8671


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+ased microcontro**er according to the commands gi&en /rom the #$M Mo+i*e the

ro+ot )i** mo&e.

The s,stem -ses a compact circ-itr, +-i*t aro-nd LPC2148 (ARM!

microcontro**er Programs are de&e*oped in m+edded C. *ash magic is -sed /or

*oading programs into Microcontro**er

SOFTWARE: m+edded 9C:

TOOLS: ;ei*" *ash magic.

TARGET DEVICE: LPC2148 (ARM! Microcontro**er.

APPLICATIONS:


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INTRODUCTION


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DESIGN AND DEVEPLOPMENT OFHARDWARE


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Main Circi! Dia"ra# an$ i!% &'ra &*ra!i&n:

SCHEMATIC DIAGRAM:


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INTERNAL WOR+ING EXPLANATION:

Main*, the +*oc diagram consists o/ /o**o)ing parts>

• Po)er s-pp*, circ-it

• Micro Contro**er

• #$M Modem

• %ri&er 'C

• %C motor

The de&ices that act as inp-t are

• Po)er s-pp*,

• #$M Modem

The de&ices that act as o-tp-t are

• %ri&er 'C

• %C motor


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POWER SUPPLY INTERNAL WOR+ING EXPLANATION:

#enera**, in 'ndia" )e get 2?6& AC po)er s-pp*, /rom mains +-t )e need on*,

?.?& %C s-pp*, /or the LPC2148. The act-a* &o*tage )hat )e get /rom the s)itch

+oards is 2?6& AC )e need to con&ert this 2?6& AC into ?.?& %C +, -sing a

simp*e circ-it. This circ-it consists o/ trans/ormer" +ridge recti/ier" and capacitor

and &o*tage reg-*ator. irst the 2?6& AC po)er s-pp*, is gi&en as inp-t to the step

do)n trans/ormer (1236!)hich step do)ns the 2?6& AC into 12& AC and /rom

there )e send 12& AC as an inp-t to the +ridge recti/ier" the +ridge recti/ier

con&erts the 12& ac into a p-*sating 12& %C (sti** contains some AC components in

it!. $ince the o-tp-t o/ the +ridge recti/ier is not p-re 12& %C )e need a /i*ter to

/i*ter a** the remaining AC components so )e are -sing capacitor as a /i*ter. The

12& %C (p-*sating! is sent to the capacitor (1666-/! it charges (*ie it in taes!

)hene&er it /inds the AC components and sends the %C components a)a, /rom it.

Then the o-tp-t o/ the capacitor is p-re 12& %C. $ince )e re-ire on*, ?.?& %C

then send 12& %C into a &o*tage reg-*ator (LM?1! )hich reg-*ates the 12& %Cinto ?.?& %C )hich is the eact &o*tage s-pp*, re-ired /or LPC2148

contro**er. 5, this proced-re" )e are con&erting the o-tp-t &o*tage to o-r desired

&o*tage. The desired &o*tage is gi&en to the @CC (pin! @#B% (pin! o/ LPC2148

microcontro**er.


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HOW TO INTERFACE DEVICES TO THE LPC,-./

MICRO CONTROLLER


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In!r0acin" GSM !& !1 LPC,-./ #icr& c&n!r&r:

The #$M modem inter/aced to contro**er thro-gh MA32?2 and R$32?2

ca+*e. The #$M modem )ors +, -sing AT commands. The #$M modem is

initia*i=ed +, -sing AT commands in code. or sending the message" recei&ing

messages" message /ormat and /or de*eting message e&er,thing is done +,

eec-ting AT commands" /or each and e&er, tas there is separate AT commands.

ATDCM# E 1 /or /ormatting message

ATDCM#$ E “mo+i*e n-m+er” /or sending message

ATDCM#R E “inde n-m+er” /or reading message

ATDCM#L /or *isting a** the messages in in+o

ATDCM#% E “inde n-m+er” /or de*eting message

In!r0acin" RS2,3, 4 MAX2,3, !& !1 LPC,-./ Micr& c&n!r&r:

The R$2?2 is the most )ide*, -sed seria* 'F inter/acing standard. This is

-sed in most PC:s and n-mero-s t,pes o/ e-ipment. $ince this standard )as

introd-ced *ong +e/ore the ad&ent o/ TTL *ogic /ami*," its inp-t and o-tp-t &o*tage

*e&e*s are not TTL compati+*e.

'n R$2?2" a 91: is represented +, 3?& to 327&" )hi*e a 96: +it is D?& to D27&

and a*so maing 3?& to D?& is -nde/ined. or this reason" to connect an, R$2?2 to

a micro contro**er s,stem )e m-st -se &o*tage con&erts s-ch as MA2?2 to

con&ert the TTL *ogic *e&e*s to the R$2?2 &o*tage *e&e*s" and &ice &ersa. MA2?2

chips are common*, re/erred to as *ine dri&ers. $o to inter/ace an, #$M or #P$ or

R'% or PR$ mod-*es R$2?2 and MA2?2 are the -sed to inter/ace to the micro


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contro**er /or seria* comm-nication. The *ine dri&ers -sed /or transmitting T% in

MA2?2 are T1 (T13in and T13o-t! and T2 (T23in and T23o-t!. The *ine dri&ers

-sed /or recei&ing the data is R1 (R13in and R13o-t! and R2 (R23in and R23o-t!.

or transmitting the data to the other de&ice the T% pin o/


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T&!a circi! in!rna 5&r6in" 7*ana!i&n:

The main aim is to design a $M$ contro**ed ro+ot. The ro+ot mo&ement is

tota**, contro**ed +, -sing messages.

Contro**er is inter/aced to %C motors thro-gh %ri&er 'C:s these 'C can a*so

+e ca**ed as *ine dri&er. 5ased on the messages sent thro-gh mo+i*e the direction o/

ro+ot is changed /or /or)ard direction" +ac)ard direction" right direction" *e/t

direction /or a** directions speci/ic messages )i** +e sent thro-gh mo+i*e /or

changing direction o/ ro+ot. The #$M modem is inter/aced to contro**er thro-gh

R$32?2 ca+*e to


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Hence the direction o/ ro+ot is changes +, -sing mo+i*e thro-gh messages.


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BLOCK DIAGRAM AND DESCRIPTION


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BLOC+ DIAGRAM:


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ARM Arc1i!c!r


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ARM Arc1i!c!r 4 Pr&"ra##in"

ARM Hi%!&r8

Arc1i!c!r

ARM r"i%!r 0i 4 #&$% &0 &*ra!i&n

In%!rc!i&n S!

ARM Hi%!&r8

The ARM (Ac&rn RISC Mac1in!architect-re is de&e*oped at Acron

Comp-ter Limited o/ Cam+ridge" ng*and +et)een 1G8?31G87. ARM Limited

/o-nded in 1GG6. ARM +ecame as the A$'anc$ RISC Mac1in is a ?23+it

R'$C processor architect-re that is )ide*, -sed in em+edded designs. ARM cores

*icensed to semicond-ctor partners )ho /a+ricate and se** to their c-stomers.

Today, the ARM family accounts for approximately 75%

of all embedded 32-bit R!" "#$s, main& it the most 'idely used

32-bit architecture( ARM "#$s are found in most corners of

consumer electronics, from portable de)ices *#+As, mobile

phones, i#ods and other di&ital media and music players,

handheld &amin& units, and calculators to computer peripherals

*hard dri)es, destop routers(


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ARM architecture

RISC:

R'$C" or Reduced Instruction Set Computer . is a t,pe o/ microprocessor

architect-re that -ti*i=es a sma**" high*,3optimi=ed set o/ instr-ctions" rather than a

more specia*i=ed set o/ instr-ctions o/ten /o-nd in other t,pes o/ architect-res.

Histor!

The rst R!" pro.ects came from /M, !tanford, and $"-/ereley

in the late 70s and early 10s( The /M 10, !tanford M#!, and/ereley R!" and 2 'ere all desi&ned 'ith a similar philosophy

'hich has become no'n as R!"( "ertain desi&n features ha)e

been characteristic of most R!" processors

• one cycle execution time

• pipelining

• large number of registers

5ased -pon R'$C Architect-re )ith enhancements to meet re-irements o/

em+edded app*ications ARM is ha&ing

1. A *arge -ni/orm register /i*e

2. Load3store architect-re ")here data processing operations operate on

register contents on*,

?.


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. High Code %ensit,

A V&n N#ann arc1i!c!r store program and data in the same memor, area

)ith a sing*e +-s. $o this +-s on*, is -sed /or +oth data trans/ers and instr-ction

/etches" and there/ore data trans/ers and instr-ction /etches m-st +e sched-*ed 3

the, can not +e per/ormed at the same time. Most o/ the genera*3p-rpose

microprocessors s-ch as Motoro*a I8666 and 'nte* 868I -se this architect-re. 't is

simp*e in hard)are imp*ementation" +-t the data and program are re-ired to share

a sing*e +-s.

ARM Pr&c%%&r C&r :

The /ig-re sho)s the ARM core data/*o) mode*. 'n )hich the ARM core as

/-nctiona* -nits connected +, data +-ses". And the arro)s represent the /*o) o/

data" the *ines represent the +-ses" and +oes represent either an operation -nit or a


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storage area. The /ig-re sho)s not on*, the /*o) o/ data +-t a*so the a+stract

components that mae -p an ARM core.

ig > ARM core data/*o) mode*

9ARM B% Tc1n&&"8 :

m+edded s,stems -se di//erent +-s techno*ogies. m+edded de&ices -se

an on3chip +-s that is interna* to the chip and a**o)s di//erent periphera* de&ices to

+e inter connected )ith an ARM core.

There are t)o di//erent t,pes o/ de&ices connected to the +-s

1. 5-s Master

2. 5-s $*a&e

1. B% Ma%!r : A *ogica* de&ice capa+*e o/ initiating a data trans/er )ith

another de&ice across the same +-s (ARM processor core is a +-s Master !.

2. B% Sa' : A *ogica* de&ice capa+*e on*, o/ responding to a trans/er re-est/rom a +-s master de&ice ( Periphera*s are +-s s*a&es !

#enera**, A 5-s has t)o architect-re *e&e*s

P18%ica ': 0hich co&ers e*ectrica* characteristics a +-s )idth (1I" ?2" I4 +-s!.

Pr&!&c& ': This dea*s )ith protoco*

AMBA (A$'anc$ Micr&c&n!r&r B% Arc1i!c!r) B% *r&!&c&:

AM5A 5-s )as introd-ced in 1GGI and has +een )ide*, adopted as the n

Chip +-s architect-re -sed /or ARM processors.

The /irst AM5A +-ses )ere


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1. ARM $,stem 5-s ( A$5 !

2. ARM Periphera* 5-s ( AP5 !

Later ARM introd-ced another +-s design ca**ed the ARM High per/ormance 5-s (

AH5 !


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T J Th-m+ 1I +it decoder

% J KTA# de+-g

M J /ast m-*tip*ier

' J m+edded'C macroce**

J enhanced instr-ction ( ass-mes T%M' !

K J Ka=e**e

J &ector /*oating3point -nit

$ J s,nthesi=i+*e &ersion

A** ARM cores a/ter the ARMT%M' inc*-de the T%M' /eat-res e&en

tho-gh the, ma, not inc*-de those *etters a/ter the “ ARM ” *a+e*

The processor /ami*, is a gro-p o/ processor imp*ementations that share the

same hard)are characteristics. or eamp*e" the ARMT%M'" ARM46T"

and ARM26T a** share the same /ami*, characteristics and +e*ong to the

ARM /ami*,

JTAG is descri+ed +, ' 114G.1 standard Test Access Port and +o-ndar,

scan architect-re. 't is a seria* protoco* -sed +, ARM to send and recei&e

de+-g in/ormation +et)een the processor core and test e-ipment

EmbeddedICE macrocell is the de+-g hard)are +-i*t into the processor that

a**o)s +reapoints and )atchpoints to +e set

Synthesizable means that the processor core is s-pp*ied as so-rce code that

can +e compi*ed into a /orm easi*, -sed +, %A too*s


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In!r&$c!i&n !& ARM>TDMI c&r

The ARM7T+M core is a 32-bit embedded R!" processor

deli)ered as a hard macrocell optimi4ed to pro)ide the best

combination of performance, po'er and area characteristics( The

ARM7T+M core enables system desi&ners to build embedded

de)ices reuirin& small si4e, lo' po'er and hi&h performance(

ARM7TDMI Features

• 326-bit R!" architecture *ARM )8T

• 32-bit ARM instruction set for maximum performance and

9exibility

• -bit Thumb instruction set for increased code density

• $nied bus interface, 32-bit data bus carries both

instructions and data

• Three-sta&e pipeline

•

32-bit A:$• ;ery small die si4e and lo' po'er consumption

• TA? interface unit

ARM7TDMI Microcontrollers

1. Available AR!T"I icrocontrollers

2( Analo& +e)ices A+u" 7xxx

3( Atmel AT@!AM7

8(


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5( B#6#hilips :#"2000

#. ST STR!1$

7(Texas nstruments TM!870

"#$ ARM Re%ister &'e ( )o*es o+ o,eratio-

Re%isters ! ?eneral #urpose re&isters hold either data or address

they are identied 'ith the letter r prexed to the re&ister

number( All re&isters are of 32 bits(

ARM 1a% 3> r"i%!r% in !&!a? a &0 51ic1 ar 3,2@i!% &n"

1 dedicated program co-nter

1 dedicated c-rrent program stat-s register

7 dedicated sa&ed program stat-s registers

?6 genera* p-rpose registers

Ho)e&er these are arranged into se&era* +ans" )ith the accessi+*e +an +eing

go&erned +, the processor mode. ach mode can access a partic-*ar set o/ r63r12

registers" a partic-*ar r1? (the stac pointer! and r14 (*in register!" r17 (the

program co-nter!" cpsr (the c-rrent program stat-s register!

and pri&i*eged modes can a*so access a partic-*ar spsr (sa&ed program stat-s

register!.

'n -ser mode 1I data registers and 2 stat-s registers are &isi+*e. %epending -pon

contet" register r1? and r14 can a*so +e -sed as #enera* P-rpose Registers. 'n

ARM state the registers r6 to r1? are Orthogonal that means 3 an, instr-ction

)hich -se r6 can as )e** +e -sed )ith an, other #enera* P-rpose Register (r13

r1?!.


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The ARM processor has three registers assigned to a partic-*ar tas or specia*

/-nction> r1?"r14 and r17. The, are /re-ent*, gi&en di//erent *a+e*s to di//erentiate

them /rom the other registers.

Register r1% is traditiona**, -sed as the stac pointer ( sp! and stores the head

o/ the stac in the c-rrent processor mode

Register r1& is ca**ed the *in register ( lr ' and is )here the core p-ts the

ret-rn address )hene&er it ca**s a s-+ro-tine.

Register r1( is the program co-nter ( pc ! and contains the address o/ the

net instr-ction to +e /etched +, the processor

The register /i*e contains a** the registers a&ai*a+*e to a programmer. 0hich

registers are &isi+*e to the programmer depend -pon the c-rrent mode o/ the

processor.

Crrn! *r&"ra# %!a!% r"i%!r :

The ARM core -ses the cpsr to monitor and contro* interna* operations. The

cpsr is a dedicated ?23+it register and resides in the register /i*e. The /o**o)ing

/ig-re sho)s the generic program stat-s register.


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ig> Program $tat-s Register ig> Program $tat-s Register

The M6" M1" M2" M? and M4 +its are the mode +its

Pr&c%%&r M&$%: Processor modes determine )hich register are acti&e" and

access rights to CP$R register itse*/. ach processor mode is either Pri&i*eged or Bon3pri&i*eged. ARM has se&en modes. These modes are di&ided into t)o t,pes.

Pri'i"$ :2 -** read3)rite access to the CP$R.


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access to the condition /*ags.

U%r(-):


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ach pri&i*eged mode (ecept s,stem mode! has associated )ith it a $a&e Program

$tat-s Register" or $P$R. This $P$R is -sed to sa&e the state o/ CP$R (C-rrent

program stat-s Register! )hen the pri&i*eged mode is entered in order that the -ser

state can +e /-**, restored )hen the -ser processor is res-med

Mode Changing >

Mode changes +, )riting direct*, to CP$R or +, hard)are )hen the processor

responds to eception or interr-pt. To ret-rn to -ser mode a specia* ret-rn

instr-ction is -sed that instr-cts the core to restore the origina* CP$R and +aned

registers


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LPC,-./ MICROCONTROLLER


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LPC ,-./ MICROCONTROLLER

Gnra $%cri*!i&n &0 LPC ,-./:

The LPC2148 microcontro**ers is +ased on a ?23+it ARMT%M'3$

CP< )ith rea*3time em-*ation and em+edded trace s-pport" that com+ine

microcontro**ers )ith em+edded high3speed /*ash memor, ranging /rom ?2 5 to

712 5. A 1283+it )ide memor, inter/ace and -ni-e acce*erator architect-re

ena+*e ?23+it code eec-tion at the maim-m c*oc rate. or critica* code si=e

app*ications" the a*ternati&e 1I3+it Th-m+ mode red-ces code +, more than ?6

)ith minima* per/ormance pena*t,.

%-e to their tin, si=e and *o) po)er cons-mption" LPC2141F42F44F4IF48

are idea* /or app*ications )here miniat-ri=ation is a e, re-irement" s-ch as

access contro* and point3o/3sa*e. $eria* comm-nications inter/aces ranging /rom a


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can +e erased and Re programmed )itho-t remo&a* /rom the circ-it +oard. 'n order

to per/orm '$P operations the microcontro**er is po)ered -p in a specia* “'$P

mode”. '$P mode a**o)s the microcontro**er to comm-nicate )ith an eterna* host

de&ice thro-gh the seria* port" s-ch as a PC or termina*. The microcontro**er

recei&es commands and data /rom the host" erases and reprograms code memor,"

etc. nce the '$P operations ha&e +een comp*eted the de&ice is recon/ig-red so

that it )i** operate norma**, the net time it is either reset or po)er remo&ed and

reapp*ied. A** o/ the Phi*ips microcontro**ers sho)n in Ta+*e 1 and Ta+*e 2 ha&e a

1 +,te /actor,3mased RM *ocated in the -pper 1 +,te o/ code memor, space

/rom C66 to . This 1 +,te RM is in addition to the memor, +*ocs sho)n

in Ta+*e 1 and Ta+*e 2. This RM is re/erred to as the “5ootrom”. This 5ootrom

contains a set o/ instr-ctions )hich a**o)s the microcontro**er to per/orm a n-m+er

o/ *ash programming and erasing /-nctions. The 5ootrom a*so pro&ides

comm-nications thro-gh the seria* port. The -se o/ the 5ootrom is e, to the

concepts o/ +oth '$P and 'n3App*ication Programming ('AP!. The contents o/ the

+ootrom are pro&ided +, Phi*ips and mased into e&er, de&ice. 0hen the de&ice is

reset or po)er app*ied" and the AF pin is high or at the @PP &o*tage" the

microcontro**er )i** start eec-ting instr-ctions /rom either the -ser code memor,

space at address 6666h (“norma* mode”! or )i** eec-te instr-ctions /rom the

5ootrom ('$P mode!.

Gnra O'r'i5 &0 IN APPLICATION PROGRAMMING:

$ome app*ications ma, ha&e a need to +e a+*e to erase and program code memor,-nder the contro* /o the app*ication. or eamp*e" an app*ication ma, ha&e a need

to store ca*i+ration in/ormation or perhaps need to +e a+*e to do)n*oad ne) code

portions. This a+i*it, to erase and program code memor, in the end3-ser

app*ication is “'n3App*ication Programming” ('AP!. The 5ootrom ro-tines )hich


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per/orm /-nctions on the *ash memor, d-ring '$P mode s-ch as programming"

erasing" and reading" are a*so a&ai*a+*e to end3-ser programs. Th-s it is possi+*e /or

an end3-ser app*ication to per/orm operations on the *ash memor,. A common

entr, point (6h! to these ro-tines has +een pro&ided to simp*i/, inter/acing to

the end3-sers app*ication. -nctions are per/ormed +, setting -p speci/ic registers

as re-ired +, a speci/ic operation and per/orming a ca** to the common entr,

point. Lie an, other s-+ro-tine ca**" a/ter comp*etion o/ the /-nction" contro* )i**

ret-rn to the end3-ser:s code. The 5ootrom is shado)ed )ith the -ser code

memor, in the address range /rom C66h to h. This shado)ing is contro**ed

+, the B5T +it (A


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FEATURES OF LPC,-./(ARM>) ARCHITECTURE

+8 0a!r%:

1I3+itF?23+it ARMT%M'3$ microcontro**er in a tin, LNPI4 pacage

8 5 to 46 5 o/ on3chip static RAM and ?2 5 to 712 5 o/ on3chip /*ash

memor,O 1283+it )ide inter/aceFacce*erator ena+*es high3speed I6 MH=

operation

'n3$,stem ProgrammingF'n3App*ication Programming ('$PF'AP! &ia on3chip

+oot *oader so/t)are" sing*e /*ash sector or /-** chip erase in 466 ms and

programming o/ 27I 5 in 1 ms.

m+edded 'C RT and m+edded Trace inter/aces o//er rea*3time

de+-gging )ith the on3chip Rea* Monitor so/t)are and high3speed tracing o/

instr-ction eec-tion


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channe*s each!" P0M -nit (si o-tp-ts! and )atchdog.

Lo) po)er Rea*3Time C*oc (RTC! )ith independent po)er and ?2 H=

c*oc inp-t

M-*tip*e seria* inter/aces inc*-ding t)o

CP< operating &o*tage range o/ ?.6 @ to ?.I @ (?.? @ 16 ! )ith 7 @ to*erant

'F pads.

BLOC+ DIAGRAM:


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PIN CONFIGURATION:


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Pin D%cri*!i&n:

P !& P3- IO P&r! : Port 6 is a ?23+it 'F port )ith indi&id-a* direction

contro*s /or each +it. Tota* o/ ?1 pins o/ the Port 6 can +e -sed as a genera*

p-rpose +idirectiona* digita* 'Fs )hi*e P6.?1 is o-tp-t on*, pin. The operation o/

port 6 pins depends -pon the pin /-nction se*ected &ia the pin connect +*oc.

PTXDPWM-:

P #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TXD Transmitter o-tp-t /or


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P,SCL CAP:

P, #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

SCL '2C6 c*oc inp-tFo-tp-t" open3drain o-tp-t (/or '2C3+-s

comp*iance!

CAP Capt-re inp-t /or Timer 6" channe* 6

P3SDA MATEINT->

P3 #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

SDA '2C6 data inp-tFo-tp-t" open3drain o-tp-t (/or '2C3+-s

comp*iance!

MAT Match o-tp-t /or Timer 6" channe* 6

EINT- terna* interr-pt 1 inp-t

P.SC+ CAP-AD

P. #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

SC+ $eria* c*oc /or $P'6" $P' c*oc o-tp-t /rom master or inp-t to

s*a&e

CAP- Capt-re inp-t /or Timer 6" channe* 6

AD A%C 6" inp-t I.

PMISO MAT-AD>

P #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

MISO Master 'n $*a&e


40/120

MOSI Master o-t $*a&e 'n /or $P'6" data o-tp-t /rom $P' master or

data 'np-t to $P' s*a&e

CAP, Capt-re inp-t /or Timer 6" channe* 2

AD- A%C 1" inp-t 6" a&ai*a+*e in LPC2144F4IF48 on*,

P>SSELPWM,EINT,

P> #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

SSEL $*a&e $e*ect /or $P'6" se*ects the $P' inter/ace as a s*a&e

PWM, P-*se 0idth Mod-*ator o-tp-t 2

EINT, terna* interr-pt 2 inp-t

P/TXD-PWM.AD--

P/ #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TXD- Transmitter o-tp-t /or


41/120

AD-, A%C 1" inp-t 2" a&ai*a+*e in LPC2144F4IF48 on*,

P--CTS- CAP--SCL-:

P-- #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

CTS- C*ear to send inp-t /or


42/120

P-. #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

DCD- %ata Carrier %etect inp-t /or CAP-, SC+-MAT-,:

P-> #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

CAP-, Capt-re inp-t /or Timer 1" channe* 2

SC+- $eria* C*oc /or $$P" c*oc o-tp-t /rom master or inp-t to

s*a&e

MAT-, Match o-tp-t /or Timer 1" channe* 2

P-/CAP-3MISO-MAT-3:


43/120

P-/ #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

CAP-3 Capt-re inp-t /or Timer 1" channe* ?

MISO- Master 'n $*a&e -t /or $$P" data inp-t to $P' master or

data o-tp-t /rom $$P s*a&e

MAT-3 Match o-tp-t /or Timer 1" channe* ?

P-MAT-,MOSI-CAP-,:

P- #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

MAT-, Match o-tp-t /or Timer 1" channe* 2

MOSI- Master o-t $*a&e 'n /or $$P" data o-tp-t /rom $$P master or

data 'np-t to $$P s*a&e

CAP-, Capt-re inp-t /or Timer 1" channe* 2

P,MAT-3SSEL-EINT3:

P, #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

MAT-3 Match o-tp-t /or Timer 1" channe* ?

SSEL- $*a&e $e*ect /or $$P" se*ects the $$P inter/ace as a s*a&e

EINT3 terna* interr-pt ? inp-t

P,-PWMAD-CAP-3:

P,- #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

PWM P-*se 0idth Mod-*ator o-tp-t 7

AD- A%C 1" inp-t I" a&ai*a+*e in LPC2144F4IF48 on*,

CAP-3 Capt-re inp-t /or Timer 1" channe* ?

P,,AD->CAPMAT:

P,, #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!


44/120

AD-> A%C 1" inp-t " a&ai*a+*e in LPC2144F4IF48 on*,


MAT Match o-tp-t /or Timer 6" channe* 6

P,3VBUS:

P,3 #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

VBUS 'ndicates the presence o/


45/120

P3 #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

AD3 A%C 6" inp-t ?

EINT3 terna* interr-pt ? inp-t


P3-UPJLEDCONNECT

P3- #enera* p-rpose o-tp-t on*, digita* pin (#P!

UPJLED


46/120

P--/TRACEP+T,

P--/ #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TRACEP+T, Trace Pacet" +it 2" standard 'F port )ith interna*

p-**3-p

P--TRACEP+T3

P-- #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TRACEP+T3 Trace Pacet" +it ?" standard 'F port )ith interna*

p-**3-p

P-,TRACESYNC

P-, #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TRACESYNC Trace $,nchroni=ation" standard 'F port )ith

interna* p-**3-p

P-,-PIPESTAT

P-,- #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

PIPESTAT Pipe*ine $tat-s" +it 6" standard 'F port )ith interna*

p-**3-p

P-,,PIPESTAT-

P-,, #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

PIPESTAT- Pipe*ine $tat-s" +it 1" standard 'F port )ith interna*

p-**3-p

P-,3PIPESTAT,

P-,3 #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

PIPESTAT, Pipe*ine $tat-s" +it 2" standard 'F port )ith interna* p-**3-p

P-,.TRACECL+

P-,. #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TRACECL+ Trace C*oc" standard 'F port )ith interna* p-**3-p


47/120

P-,EXTIN


EXTIN terna* Trigger 'np-t" standard 'F )ith interna* p-**3-p

P-,RTC+


RTC+ Ret-rned Test C*oc o-tp-t" etra signa* added to the KTA#

port" assists de+-gger s,nchroni=ation )hen processor /re-enc, &aries"

+idirectiona* pin )ith interna* p-**3-p

P-,>TDO

P-,> #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TDO Test %ata o-t /or KTA# inter/ace

P-,/TDI

P-,/ #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TDI Test %ata in /or KTA# inter/ace

P-,TC+

P-, #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!TC+ Test C*oc /or KTA# inter/ace

P-3TMS

P-3 #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TMS Test Mode $e*ect /or KTA# inter/ace

P-3-TRST

P-3- #enera* p-rpose inp-tFo-tp-t digita* pin (#P'!

TRST Test Reset /or KTA# inter/ace

DK>


48/120

RESET E7!rna r%! in*!: A L0 on this pin resets the de&ice" ca-sing 'F

ports and periphera*s to tae on their de/a-*t states" and processor eec-tion to

+egin at address 6" TTL )ith h,steretic" 7 @ to*erant

XTAL-> 'np-t to the osci**ator circ-it and interna* c*oc generator circ-its

XTAL,> -tp-t /rom the osci**ator amp*i/ier

RTCX-> ' 'np-t to the RTC osci**ator circ-it

RTCX,> -tp-t /rom the RTC osci**ator circ-it

VSS> I" 18" 27" 42" 76 pins are /or s-pp*, &o*tage.

Gr&n$: 6 @ re/erence.

VSSA Ana&" "r&n$: 6 @ re/erence" this sho-*d nomina**, +e the same &o*tage

as @$$" +-t sho-*d +e iso*ated to minimi=e noise and error

VDD ,3? .3? - I 33 V *&5r %**8: This is the po)er s-pp*, &o*tage /or the

core and 'F ports.

VDDA > I Ana&" 33 V *&5r %**8: This sho-*d +e nomina**, the same

&o*tage as @%% +-t sho-*d +e iso*ated to minimi=e noise and error" this &o*tage is

on*, -sed to po)er the on3chip A%C(s! and %AC

VREF ADC r0rnc '&!a": This sho-*d +e nomina**, *ess than or e-a* to the

@%% &o*tage +-t sho-*d +e iso*ated to minimi=e noise and error" *e&e* on this


49/120

Pin is -sed as a re/erence /or A%C(s! and %AC

VBAT RTC *&5r %**8 '&!a": ?.? @ on this pin s-pp*ies the po)er to the

RTC.

Fnc!i&na D%cri*!i&n:

Arc1i!c!ra O'r'i5:

The ARMT%M'3$ is a genera* p-rpose ?23+it microprocessor" )hich

o//ers high per/ormance and &er, *o) po)er cons-mption. The ARM architect-re

is +ased on Red-ced 'nstr-ction $et Comp-ter (R'$C! princip*es" and the

instr-ction set and re*ated decode mechanism are m-ch simp*er than those o/ micro

programmed Comp*e 'nstr-ction $et Comp-ters (C'$C!. This simp*icit, res-*ts in

a high instr-ction thro-ghp-t.

ssentia**," the ARMT%M'3$ processor has t)o instr-ction sets>

The standard ?23+it ARM set

A 1I3+it Th-m+ set

The Th-m+ set:s 1I3+it instr-ction *ength a**o)s it to approach t)ice the densit, o/

standard ARM code )hi*e retaining most o/ the ARM:s per/ormance ad&antage

o&er a traditiona* 1I3+it processor -sing 1I3+it registers. This is possi+*e +eca-se

Th-m+ code operates on the same ?23+it register set as ARM code. Th-m+ code is

a+*e to pro&ide -p to I7 o/ the code si=e o/ ARM" and 1I6 o/ the per/ormance

o/ an e-i&a*ent ARM processor connected to a 1I3+it memor, s,stem. The

partic-*ar /*ash imp*ementation in the LPC2141F42F44F4IF48 a**o)s /or /-** speed

eec-tion a*so in ARM mode. 't is recommended to program per/ormance critica*

and short code sections (s-ch as interr-pt ser&ice ro-tines and %$P a*gorithms! in


50/120

ARM mode. The impact on the o&era** code si=e )i** +e minima* +-t the speed can

+e increased +, ?6 o&er Th-m+ mode.

On2C1i* Fa%1 Pr&"ra# ##&r8:

The LPC2141F42F44F4IF48 incorporate a ?2 5" I4 5" 128 5" 27I 5 and 712

5 /*ash memor, s,stem respecti&e*,. This memor, ma, +e -sed /or +oth code and

data storage. Programming o/ the /*ash memor, ma, +e accomp*ished in se&era*

)a,s. 't ma, +e programmed 'n $,stem &ia the seria* port. The app*ication

program ma, a*so erase andFor program the /*ash )hi*e the app*ication is r-nning"

a**o)ing a great degree o/ /*ei+i*it, /or data storage /ie*d /irm)are -pgrades" etc.

%-e to the architect-ra* so*-tion chosen /or an on3chip +oot *oader" /*ash memor,

a&ai*a+*e /or -ser:s code on LPC2141F42F44F4IF48 is ?2 5" I4 5" 128 5" 27I

5 and 766 5 respecti&e*,.

The LPC2141F42F44F4IF48 /*ash memor, pro&ides a minim-m o/ 166666

eraseF)rite c,c*es and 26 ,ears o/ data3retention.

On2C1i* S!a!ic RAM:

n3chip static RAM ma, +e -sed /or code andFor data storage. The

$RAM ma, +e accessed as 83+it" 1I3+it" and ?23+it. The LPC2141" LPC2142F44

and LPC214IF48 pro&ide 8 5" 1I 5 and ?2 5 o/ static RAM respecti&e*,. 'n

case o/ LPC214IF48 on*," an 8 5 $RAM +*oc intended to +e -ti*i=ed main*, +,

the


51/120

The LPC2141F42F44F4IF48 memor, map incorporates se&era* distinct

regions" as sho)n +e*o).

In!rr*! c&n!r&r:


52/120

The @ectored 'nterr-pt Contro**er (@'C! accepts a** o/ the

interr-pt re-est inp-ts and categori=es them as ast 'nterr-pt Re-est ('N!"

&ectored 'nterr-pt Re-est ('RN!" and non3&ectored 'RN as de/ined +,

programma+*e settings. The programma+*e assignment scheme means that

priorities o/ interr-pts /rom the &ario-s periphera*s can +e d,namica**, assigned

and adj-sted. ast interr-pt re-est ('N! has the highest priorit,.

In!rr*! S&rc%:

ach periphera* de&ice has one interr-pt *ine connected to the @ectored

'nterr-pt Contro**er" +-t ma, ha&e se&era* interna* interr-pt /*ags. 'ndi&id-a*

interr-pt /*ags ma, a*so represent more than one interr-pt so-rce.

Pin C&nnc! B&c6:

The pin connect +*oc a**o)s se*ected pins o/ the microcontro**er to

ha&e more than one /-nction. Con/ig-ration registers contro* the m-*tip*eers to

a**o) connection +et)een the pin and the on chip periphera*s. Periphera*s sho-*d

+e connected to the appropriate pins prior to +eing acti&ated" and prior to an,

re*ated interr-pt(s! +eing ena+*ed. Acti&it, o/ an, ena+*ed periphera* /-nction that

is not mapped to a re*ated pin sho-*d +e considered -nde/ined.

Fa%! Gnra *r*&% Para IO:

%e&ice pins that are not connected to a speci/ic periphera* /-nction

are contro**ed +, the #P' registers. Pins ma, +e d,namica**, con/ig-red as inp-ts

or o-tp-ts. $eparate registers a**o) the setting or c*earing o/ an, n-m+er o/ o-tp-tssim-*taneo-s*,. The &a*-e o/ the o-tp-t register ma, +e read +ac" as )e** as the

c-rrent state o/ the port pins. LPC2141F42F44F4IF48 introd-ces acce*erated #P'

/-nctions o&er prior LPC2666 de&ices>


53/120

- @i! ADC:

The LPC2141F42 contain one and the LPC2144F4IF48 contain t)o ana*og

to digita* con&erters. These con&erters are sing*e 163+it s-ccessi&e approimation

ana*og to digita* con&erters. 0hi*e A%C6 has si channe*s" A%C1 has eight

channe*s. There/ore" tota* n-m+er o/ a&ai*a+*e A%C inp-ts /or LPC2141F42 is I

and /or LPC2144F4IF48 is 14.

- @i! DAC:

The %AC ena+*es the LPC2141F42F44F4IF48 to generate a &aria+*e ana*og

o-tp-t. The maim-m %AC o-tp-t &o*tage is the @R &o*tage.

USB , D'ic c&n!r&r:

The


54/120

a-to3CT$FRT$ /*o)3contro* /-nctions are /-**, imp*emented in hard)are (


55/120

m-*tip*e masters and s*a&es on the +-s. Ho)e&er" on*, a sing*e master and a sing*e

s*a&e can comm-nicate on the +-s d-ring a gi&en data trans/er. The $$P s-pports

/-** d-p*e trans/ers" )ith data /rames o/ 4 +its to 1I +its o/ data /*o)ing /rom the

master to the s*a&e and /rom the s*a&e to the master. /ten on*, one o/ these data

/*o)s carries meaning/-* data.

Gnra Pr*&% !i#r%7!rna 'n! c&n!r%

The TimerFCo-nter is designed to co-nt c,c*es o/ the periphera* c*oc

(PCL;! or an eterna**, s-pp*ied c*oc and optiona**, generate interr-pts or

per/orm other actions at speci/ied timer &a*-es" +ased on /o-r match registers. 't

a*so inc*-des /o-r capt-re inp-ts to trap the timer &a*-e )hen an inp-t signa*s

transitions" optiona**, generating an interr-pt. M-*tip*e pins can +e se*ected to

per/orm a sing*e capt-re or match /-nction" pro&iding an app*ication )ith 9or: and

9and:" as )e** as 9+roadcast: /-nctions among them. The LPC2141F42F44F4IF48 can

co-nt eterna* e&ents on one o/ the capt-re inp-ts i/ the minim-m eterna* p-*se is

e-a* or *onger than a period o/ the PCL;.

Wa!c1$&" Ti#r

The p-rpose o/ the )atchdog is to reset the microcontro**er )ithin a

reasona+*e amo-nt o/ time i/ it enters an erroneo-s state. 0hen ena+*ed" the

)atchdog )i** generate a s,stem reset i/ the -ser program /ai*s to 9/eed: (or re*oad!

the )atchdog )ithin a predetermined amo-nt o/ time.

Ra Ti# C&c6:

The RTC is designed to pro&ide a set o/ co-nters to meas-re time )hen

norma* or id*e operating mode is se*ected. The RTC has +een designed to -se *itt*e

po)er" maing it s-ita+*e /or +atter, po)ered s,stems )here the CP< is not

r-nning contin-o-s*, ('d*e mode!.


56/120

P% 5i$!1 #&$a!&r

The P0M is +ased on the standard timer +*oc and inherits a** o/ its

/eat-res" a*tho-gh on*, the P0M /-nction is pinned o-t on the

LPC2141F42F44F4IF48. The timer is designed to co-nt c,c*es o/ the periphera*

c*oc (PCL;! and optiona**, generate interr-pts or per/orm other actions )hen

speci/ied timer &a*-es occ-r" +ased on se&en match registers. The P0M /-nction is

a*so +ased on match register e&ents.

S8%!# C&n!r&

- Cr8%!a O%cia!&r>

n3chip integrated osci**ator operates )ith eterna* cr,sta* in

range o/ 1 MH= to 27 MH=. The osci**ator o-tp-t /re-enc, is ca**ed /osc and the

ARM processor c*oc /re-enc, is re/erred to as CCL; /or p-rposes o/ rate

e-ations" etc. /osc and CCL; are the same &a*-e -n*ess the PLL is r-nning and

connected.

, PLL:

The PLL accepts an inp-t c*oc /re-enc, in the range o/ 16

MH= to 27 MH=. The inp-t /re-enc, is m-*tip*ied -p into the range o/ 16 MH= to

I6 MH= )ith a C-rrent Contro**ed sci**ator (CC!. The m-*tip*ier can +e an

integer &a*-e /rom 1 to ?2 (in practice" the m-*tip*ier &a*-e cannot +e higher than I

on this /ami*, o/ microcontro**ers d-e to the -pper /re-enc, *imit o/ the CP

The CC operates in the range o/ 17I MH= to ?26 MH=" so there is an additiona*di&ider in the *oop to eep the CC )ithin its /re-enc, range )hi*e the PLL is

pro&iding the desired o-tp-t /re-enc,. The o-tp-t di&ider ma, +e set to di&ide +,

2" 4" 8" or 1I to prod-ce the o-tp-t c*oc. $ince the minim-m o-tp-t di&ider &a*-e

is 2" it is ins-red that the PLL o-tp-t has a 76 d-t, c,c*e. The PLL is t-rned o//


57/120

and +,passed /o**o)ing a chip reset and ma, +e ena+*ed +, so/t)are. The program

m-st con/ig-re and acti&ate the PLL" )ait /or the PLL to Loc" then connect to the

PLL as a c*oc so-rce. The PLL sett*ing time is 166 ms.

3 R%! an$ Wa6 * Ti#r:

Reset has t)o so-rces on the LPC2141F42F44F4IF48> the R$T

pin and )atchdog reset. The R$T pin is a $chmitt trigger inp-t pin )ith an

additiona* g*itch /i*ter. Assertion o/ chip reset +, an, so-rce starts the 0ae3-p

Timer (see 0ae3-p Timer description +e*o)!" ca-sing the interna* chip reset to

remain asserted -nti* the eterna* reset is de3asserted" the osci**ator is r-nning" a

/ied n-m+er o/ c*ocs ha&e passed" and the on3chip /*ash contro**er has comp*eted

its initia*i=ation

. Br&5n &! D!c!&r

The LPC2141F42F44F4IF48 inc*-des 23stage monitoring o/ the &o*tage

on the @%% pins. '/ this &o*tage /a**s +e*o) 2.G @" the 5% asserts an interr-pt

signa* to the @'C. This signa* can +e ena+*ed /or interr-ptO i/ not" so/t)are can

monitor the signa* +, reading dedicated register.

C&$ Scri!8

This /eat-re o/ the LPC2141F42F44F4IF48 a**o)s an app*ication to

contro* )hether it can +e de+-gged or protected /rom o+ser&ation. '/ a/ter reset on3

chip +oot *oader detects a &a*id checs-m in /*ash and reads 68I7 4?21 /rom

address 61C in /*ash" de+-gging )i** +e disa+*ed and th-s the code in /*ash )i**

+e protected /rom o+ser&ation. nce de+-gging is disa+*ed" it can +e ena+*ed on*,

+, per/orming a /-** chip erase -sing the '$P.

E7!rna In!rr*! In*!%:


58/120

The LPC2141F42F44F4IF48 inc*-de -p to nine edge or *e&e* sensiti&e

terna* 'nterr-pt 'np-ts as se*ecta+*e pin /-nctions. 0hen the pins are com+ined"

eterna* e&ents can +e processed as /o-r independent interr-pt signa*s. The

terna* 'nterr-pt 'np-ts can optiona**, +e -sed to )ae3-p the processor /rom

Po)er3do)n mode. Additiona**, capt-re inp-t pins can a*so +e -sed as eterna*

interr-pts )itho-t the option to )ae the de&ice -p /rom Po)er3do)n mode.

> M#&r8 Ma**in" C&n!r&

The Memor, Mapping Contro* a*ters the mapping o/ the interr-pt &ectors

that appear +eginning at address 66666 6666. @ectors ma, +e mapped to the

+ottom o/ the on3chip /*ash memor," or to the on3chip static RAM. This a**o)s

code r-nning in di//erent memor, spaces to ha&e contro* o/ the interr-pts.

/ P&5r C&n!r&:

The LPC2141F42F44F4IF48 s-pports t)o red-ced po)er modes> 'd*e

mode and Po)er3do)n mode.

VPB BUS:

The @P5 di&ider determines the re*ationship +et)een the processor

c*oc (CCL;! and the c*oc -sed +, periphera* de&ices (PCL;!. The @P5 di&ider

ser&es t)o p-rposes. The /irst is to pro&ide periphera*s )ith the desired PCL; &ia

@P5 +-s so that the, can operate at the speed chosen /or the ARM processor. 'n

order to achie&e this" the @P5 +-s ma, +e s*o)ed do)n to 1Q2 to 1Q4 o/ the

processor c*oc rate. 5eca-se the @P5 +-s m-st )or proper*, at po)er3-p (and

its timing cannot +e a*tered i/ it does not )or since the @P5 di&ider contro*

registers reside on the @P5 +-s!" the de/a-*t condition at reset is /or the @P5 +-s


59/120

to r-n at 1Q4 o/ the processor c*oc rate. The second p-rpose o/ the @P5 di&ider is

to a**o) po)er sa&ings )hen an app*ication does not re-ire an, periphera*s to r-n

at the /-** processor rate. 5eca-se the @P5 di&ider is connected to the PLL o-tp-t"

the PLL remains acti&e (i/ it )as r-nning! d-ring 'd*e mode.

- E#a!i&n an$ D@""in":

The LPC2141F42F44F4IF48 s-pport em-*ation and de+-gging &ia a KTA#

seria* port. A trace port a**o)s tracing program eec-tion. %e+-gging and trace

/-nctions are m-*tip*eed on*, )ith #P's on Port 1. This means that a**

comm-nication" timer and inter/ace periphera*s residing on Port6 are a&ai*a+*e

d-ring the de&e*opment and de+-gging phase as the, are )hen the app*ication is

r-n in the em+edded s,stem

-- E#@$$$ ICE

$tandard ARM m+edded 'C *ogic pro&ides on3chip de+-g s-pport.

The de+-gging o/ the target s,stem re-ires a host comp-ter r-nning the de+-gger

so/t)are and an m+edded 'C protoco* con&erter. m+edded 'C protoco*

con&erter con&erts the remote de+-g protoco* commands to the KTA# data needed

to access the ARM core.

-, E#@$$$ Trac:

$ince the LPC2141F42F44F4IF48 ha&e signi/icant amo-nts o/ on3chip memor," it

is not possi+*e to determine ho) the processor core is operating simp*, +,

o+ser&ing the eterna* pins. The m+edded Trace Macro ce** (TM! pro&ides rea*3

time trace capa+i*it, /or deep*, em+edded processor cores. 't o-tp-ts in/ormation

a+o-t processor eec-tion to the trace port. The TM is connected direct*, to the


60/120

ARM core and not to the main AM5A s,stem +-s. 't compresses the trace

in/ormation and eports it thro-gh a narro) trace port.

-3 Ra M&ni!&r:

Rea* Monitor is a con/ig-ra+*e so/t)are mod-*e" de&e*oped +, ARM 'nc." )hich

ena+*es rea*3time de+-g. 't is a *ight)eight de+-g monitor that r-ns in the

+acgro-nd )hi*e -sers de+-g their /oregro-nd app*ication. 't comm-nicates )ith

the host -sing the %CC" )hich is present in the m+edded 'C *ogic. The

LPC2141F42F44F4IF48 contains a speci/ic con/ig-ration o/ Rea* Monitor so/t)are

programmed into the on3chip /*ash memor,


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REGULATED POWER SUPPLY


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REGULATED POWER SUPPLY

A &aria+*e reg-*ated po)er s-pp*," a*so ca**ed a &aria+*e +ench po)er

s-pp*," is one )here ,o- can contin-o-s*, adj-st the o-tp-t &o*tage to ,o-r

re-irements. @ar,ing the o-tp-t o/ the po)er s-pp*, is the recommended

)a, to test a project a/ter ha&ing do-+*e checed parts p*acement against

circ-it dra)ings and the parts p*acement g-ide.

This t,pe o/ reg-*ation is idea* /or ha&ing a simp*e &aria+*e +ench po)er

s-pp*,. Act-a**, this is -ite important +eca-se one o/ the /irst projects a

ho++,ist sho-*d -ndertae is the constr-ction o/ a &aria+*e reg-*ated po)er

s-pp*,. 0hi*e a dedicated s-pp*, is -ite hand, "its m-ch handier to ha&e a

&aria+*e s-pp*, on hand" especia**, /or testing.

Main*, the ARM contro**er needs ?.? &o*t po)er s-pp*,. To -se these parts

)e need to +-i*d a reg-*ated ?.? &o*t so-rce.


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@o-t range 1.27@ 3 ?@

@in 3 @o-t di//erence ?@ 3 46@

peration am+ient temperat-re 6 3 127SC

-tp-t 'ma 1.7A

Minim-m Load C-rrentma 16Ma

A c-rrent3*imiting circ-it constr-cted )ith LM?1

Part pino-t o/ LM?1 sho)ing its constant &o*tage re/erence

LM3-> is the standard part n-m+er /or an integrated three3termina* adj-sta+*e

*inear &o*tage reg-*ator. LM?1 is a positi&e &o*tage reg-*ator s-pporting inp-t

&o*tage o/ ?@ to 46@ and o-tp-t &o*tage +et)een 1.27@ and ?@. A t,pica* c-rrent

rating is 1.7A a*tho-gh se&era* *o)er and higher c-rrent mode*s are a&ai*a+*e.

@aria+*e o-tp-t &o*tage is achie&ed +, -sing a potentiometer or a &aria+*e &o*tage

/rom another so-rce to app*, a contro* &o*tage to the contro* termina*. LM?1 a*so

has a +-i*t3in c-rrent *imiter to pre&ent the o-tp-t c-rrent /rom eceeding the rated

c-rrent" and LM?1 )i** a-tomatica**, red-ce its o-tp-t c-rrent i/ an o&erheat

condition occ-rs -nder *oad. LM?1 is man-/act-red +, man, companies"


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inc*-ding Bationa* $emicond-ctor" airchi*d $emicond-ctor" and

$TMicroe*ectronics.

A*tho-gh LM?1 is an adj-sta+*e reg-*ator" it is sometimes pre/erred /or high3

precision /ied &o*tage app*ications instead o/ the simi*ar LM8 de&ices +eca-se

the LM?1 is designed )ith s-perior o-tp-t to*erances. or a /ied &o*tage

app*ication" the contro* pin )i** t,pica**, +e +iased )ith a /ied resistor net)or" a

Uener diode net)or" or a /ied contro* &o*tage /rom another so-rce. Man-/act-rer

datasheets pro&ide standard con/ig-rations /or achie&ing &ario-s design

app*ications" inc*-ding the -se o/ a pass transistor to achie&e reg-*ated o-tp-t

c-rrents in ecess o/ )hat the LM?1 a*one can pro&ide.

LM?1 is a&ai*a+*e in a )ide range o/ pacage /orms /or di//erent app*ications

inc*-ding heat sin mo-nting and s-r/ace3mo-nt app*ications. Common /orm

/actors /or high3c-rrent app*ications inc*-de T3226 and T3?. LM?1 is capa+*e

o/ dissipating a *arge amo-nt o/ heat at medi-m to high c-rrent *oads and the -se o/

a heat sin is recommended to maimi=e the *i/espan and po)er3hand*ing

capa+i*it,.

LM?? is the negati&e &o*tage comp*ement to LM?1 and the speci/ications and

/-nction are essentia**, identica*" ecept that the reg-*ator m-st recei&e a contro*

&o*tage and act on an inp-t &o*tage that are +e*o) the gr o-nd re/erence point

instead o/ a+o&e it.

BLOC+ DIAGRAM

http://en.wikipedia.org/wiki/Pinouthttp://en.wikipedia.org/wiki/Voltagehttp://en.wikipedia.org/wiki/Ampacityhttp://en.wikipedia.org/wiki/Ampacityhttp://en.wikipedia.org/wiki/Potentiometerhttp://en.wikipedia.org/wiki/Pinouthttp://en.wikipedia.org/wiki/Linear_regulatorhttp://en.wikipedia.org/wiki/Voltagehttp://en.wikipedia.org/wiki/Ampacityhttp://en.wikipedia.org/wiki/Ampacityhttp://en.wikipedia.org/wiki/Potentiometerhttp://en.wikipedia.org/wiki/Current_limiter


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0 CAB @B


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GSM


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GSM

G&@a S8%!# 0&r M&@i c#nica!i&n% (GSM> origina**, /rom Groupe

Sp)cial obile! is the most pop-*ar standard /or mo+i*e phones in the )or*d. 'ts

promoter" the #$M Association" estimates that 82 o/ the g*o+a* mo+i*e maret

-ses the standard #$M is -sed +, o&er 2 +i**ion peop*e across more than 212

co-ntries and territories. 'ts -+i-it, maes internationa* roaming &er, common

+et)een mo+i*e phone operators" ena+*ing s-+scri+ers to -se their phones in man,

parts o/ the )or*d. #$M di//ers /rom its predecessors in that +oth signa*ing and

speech channe*s are digita* ca** -a*it," and th-s is considered a second *eneration

(2#! mo+i*e phone s,stem. This has a*so meant that data comm-nication )as +-i*t

into the s,stem -sing the ?rd #eneration Partnership Project (?#PP!.

The -+i-it, o/ the #$M standard has +een ad&antageo-s to +oth cons-mers ()ho

+ene/it /rom the a+i*it, to roam and s)itch carriers )itho-t s)itching phones! and

a*so to net)or operators ()ho can choose e-ipment /rom an, o/ the man,

&endors imp*ementing #$M. #$M a*so pioneered a *o)3cost a*ternati&e to &oice

ca**s" the $hort message ser&ice ($M$" a*so ca**ed Vtet messagingV!" )hich is no)

s-pported on other mo+i*e standards as )e**.

Be)er &ersions o/ the standard )ere +ac)ard3compati+*e )ith the origina* #$M

phones. or eamp*e" Re*ease G o/ the standard added pacet data capa+i*ities" +,

means o/ #enera* Pacet Radio $er&ice (#PR$!. Re*ease GG introd-ced higher

speed data transmission -sing nhanced %ata Rates /or #$M &o*-tion (%#!

#$M (#*o+a* $,stem /or Mo+i*e comm-nication! is a digita* mo+i*e te*ephone

s,stem that is )ide*, -sed in -rope and other parts o/ the )or*d. #$M -ses a

&ariation o/ Time %i&ision M-*tip*e Access (T%MA! and is the most )ide*, -sed


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o/ the three digita* )ire*ess te*ephone techno*ogies (T%MA" #$M" and C%MA!.

#$M digiti=es and compresses data" then sends it do)n a channe* )ith t)o other

streams o/ -ser data" each in its o)n time s*ot. 't o perates at either the G66 MH= or

1"866 MH= /re-enc, +and.

#$M is the de /acto )ire*ess te*ephone standard in -rope. #$M has o&er one

+i**ion -sers )or*d)ide and is a&ai*a+*e in 1G6 co-ntr ies. $ince man, #$M

net)or operators ha&e roaming agreements )ith /oreign operators" -sers can o/ten

contin-e to -se their mo+i*e phones )hen the, tra&e* to other co-ntries.

M&@i Frnc8 Ran"R7 > G273GI6O T> 8863G17

M!i* Acc%% M!1&$ > T%MAF%M

D*7 M!1&$ > %%

N#@r &0 C1ann%- > 24 (8 -sers per channe*!

C1ann S*acin" > 266H=

M&$a!i&n > #M$; (6.? #a-ssian i*ter!

C1ann Bi! Ra! > 26.8??;+

History

'n 1G82" the -ropean Con/erence o/ Posta* and Te*ecomm-nications

Administrations (CPT! created the #ro-pe $pWcia* Mo+i*e (#$M! to de&e*op a

standard /or a mo+i*e te*ephone s,stem that co-*d +e -sed across -rope. X7Y 'n

1G8" a memorand-m o/ -nderstanding )as signed +, 1? co-ntries to de&e*op a

common ce**-*ar te*ephone s,stem across -rope.XIYXY

http://en.wikipedia.org/wiki/Mobile_phonehttp://en.wikipedia.org/wiki/GSM_Associationhttp://en.wikipedia.org/wiki/1000000000_(number)http://en.wikipedia.org/wiki/Roaminghttp://en.wikipedia.org/wiki/Mobile_phone_operatorhttp://en.wikipedia.org/wiki/2Ghttp://en.wikipedia.org/wiki/3GPPhttp://en.wikipedia.org/wiki/Short_message_servicehttp://en.wikipedia.org/wiki/Short_message_servicehttp://en.wikipedia.org/wiki/Mobile_phonehttp://en.wikipedia.org/wiki/GSM_Associationhttp://en.wikipedia.org/wiki/1000000000_(number)http://en.wikipedia.org/wiki/Roaminghttp://en.wikipedia.org/wiki/Mobile_phone_operatorhttp://en.wikipedia.org/wiki/Digital_call_qualityhttp://en.wikipedia.org/wiki/2Ghttp://en.wikipedia.org/wiki/3GPPhttp://en.wikipedia.org/wiki/Short_message_servicehttp://en.wikipedia.org/wiki/3GPP#Standardshttp://en.wikipedia.org/wiki/General_Packet_Radio_Servicehttp://en.wikipedia.org/wiki/Enhanced_Data_Rates_for_GSM_Evolution


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'n 1G8G" #$M responsi+i*it, )as trans/erred to the -ropean Te*ecomm-nications

$tandards 'nstit-te (T$'! and phase ' o/ the #$M speci/ications )ere p-+*ished in

1GG6. The /irst #$M net)or )as *a-nched in 1GG1 +, Radio*inja in in*and )ith

joint technica* in/rastr-ct-re maintenance /rom ricsson.X8Y 5, the end o/ 1GG?"

o&er a mi**ion s-+scri+ers )ere -sing #$M phone net)ors +eing operated +, 6

carriers across 48 co-ntries.XGY

Technical details

GSM i s a ce**-*ar net)or " )hich means that mo+i*e phones connect to it +,

searching /or ce**s in the immediate &icinit,. #$M net)ors operate in /o-r

di//erent /re-enc, ranges. Most #$M net)ors operate in the G66 MH= or 1866

MH= +ands. $ome co-ntries in the Americas (inc*-ding Canada and the


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a*ternate /rames in the same times*ot. The channe* data rate is 26.8?? +itFs" and

the /rame d-ration is 4.I17 ms.

The transmission po)er in the handset is *imited to a maim-m o/ 2 )atts in

#$M876FG66 and 1 )att in #$M1866F1G66.

#$M has -sed a &ariet, o/ &oice codecs to s-ee=e ?.1 H= a-dio into +et)een 7.I

and 1? +itFs. rigina**," t)o codecs" named a/ter the t,pes o/ data channe* the,

)ere a**ocated" )ere -sed" ca**ed Ha*/ Rate (7.I +itFs! and -** Rate (1? +itFs!.

These -sed a s,stem +ased -pon *inear predicti&e coding (LPC!. 'n addition to

+eing e//icient )ith +itrates" these codecs a*so made it easier to identi/, moreimportant parts o/ the a-dio" a**o)ing the air inter/ace *a,er to prioriti=e and +etter

protect these parts o/ the signa*.

#$M )as /-rther enhanced in 1GGX16Y )ith the nhanced -** Rate (R! codec" a

12.2 +itFs codec that -ses a /-** rate channe*. ina**," )ith the de&e*opment o/


71/120

a /e) do=en metersO the, are main*, -sed indoors.


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In!r0rnc 5i!1 a$i& $'ic%

This is a /orm o/ R'" and co-*d +e mitigated or e*iminated +, -se o/ additiona*

shie*ding andFor +,pass capacitors in these a-dio de&ices.Xcitation needed Y Ho)e&er" the

increased cost o/ doing so is di//ic-*t /or a designer to j-sti/,.

't is a common occ-r rence /or a near+, #$M handset to ind-ce a Vdit" dit di3dit" dit

di3dit" dit di3ditV o-tp-t on PAs" )ire*ess microphones" home stereo s,stems"

te*e&isions" comp-ters" cord*ess phones" and persona* m-sic de&ices. 0hen these

a-dio de&ices are in the near /ie*d o/ the #$M handset" the radio signa* is strong

eno-gh that the so*id state amp*i/iers in the a-dio chain act as a detector . Thec*icing noise itse*/ represents the po)er +-rsts that carr, the T%MA signa*. These

signa*s ha&e +een no)n to inter/ere )ith other e*ectronic de&ices" s-ch as car

stereos and porta+*e a-dio p*a,ers. This a*so depends on the handsets design" and

its con/ormance to strict r-*es" and reg-*ations a**ocated +, the CC in part 17 o/

CC r-*es and reg-*ation pertaining to inter/erence to e*ectronic de&ices.

N!5&r6 %!rc!r

The net)or +ehind the GSM s,stem seen +, the c-stomer is *arge and

comp*icated in order to pro&ide a** o/ the ser&ices )hich are re-ired. 't is di&ided

into a n-m+er o/ sections and these are each co&ered in separate artic*es.

• The 5ase $tation $-+s,stem (the +ase stations and their contro**ers!.

• The Bet)or and $)itching $-+s,stem (the part o/ the net)or most simi*ar

to a /ied net)or!. This is sometimes a*so j-st ca**ed the core net)or.

• The #PR$ Core Bet)or (the optiona* part )hich a**o)s pacet +ased

'nternet connections!.

http://en.wikipedia.org/wiki/Kilometrehttp://en.wikipedia.org/wiki/Milehttp://en.wikipedia.org/wiki/Timing_advancehttp://en.wikipedia.org/wiki/Cellular_repeaterhttp://en.wikipedia.org/wiki/Frequency_shift_keyinghttp://en.wikipedia.org/wiki/Frequency_shift_keyinghttp://en.wikipedia.org/wiki/Frequency_shift_keyinghttp://en.wikipedia.org/wiki/Gaussian_functionhttp://en.wikipedia.org/wiki/Low-pass_filterhttp://en.wikipedia.org/wiki/Frequency_modulationhttp://en.wikipedia.org/wiki/Interferencehttp://en.wikipedia.org/wiki/Kilometrehttp://en.wikipedia.org/wiki/Milehttp://en.wikipedia.org/wiki/Timing_advancehttp://en.wikipedia.org/wiki/Cellular_repeaterhttp://en.wikipedia.org/wiki/Modulationhttp://en.wikipedia.org/wiki/Gaussian_minimum-shift_keyinghttp://en.wikipedia.org/wiki/Frequency_shift_keyinghttp://en.wikipedia.org/wiki/Gaussian_functionhttp://en.wikipedia.org/wiki/Low-pass_filterhttp://en.wikipedia.org/wiki/Frequency_modulationhttp://en.wikipedia.org/wiki/Interference


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• A** o/ the e*ements in the s,stem com+ine to prod-ce man, #$M ser&ices

s-ch as &oice ca**s and $M$.

ne o/ the e, /eat-res o/ #$M is the $-+scri+er 'dentit, Mod-*e ($'M!"

common*, no)n as a SIM car$. The $'M is a detacha+*e smart card containingthe -sers s-+scription in/ormation and phone+oo. This a**o)s the -ser to retain

his or her in/ormation a/ter s)itching handsets. A*ternati&e*," the -ser can a*so

change operators )hi*e retaining the handset simp*, +, changing the $'M. $ome

operators )i** +*oc this +, a**o)ing the phone to -se on*, a sing*e $'M" or on*, a

$'M iss-ed +, themO this practice is no)n as $'M *ocing" and is i**ega* in some

co-ntries.

'n A-stra*ia" Canada" -rope and the


74/120

remo&e the *oc /or a /ee" -ti*i=e pri&ate ser&ices to remo&e the *oc" or mae -se

o/ amp*e so/t)are and )e+sites a&ai*a+*e on the 'nternet to -n*oc the handset

themse*&es. 0hi*e most )e+ sites o//er the -n*ocing /or a /ee" some do it /or /ree.

The *ocing app*ies to the handset" identi/ied +, its 'nternationa* Mo+i*e

-ipment 'dentit, ('M'! n-m+er" not to the acco-nt ()hich is identi/ied +, the

$'M card!. 't is a*)a,s possi+*e to s)itch to another (non3*oced! handset i/ s-ch a

handset is a&ai*a+*e.

$ome pro&iders )i** -n*oc the phone /or /ree i/ the c-stomer has he*d an acco-nt

/or a certain time period. Third part, -n*ocing ser&ices eist that are o/ten -icer

and *o)er cost than that o/ the operator. 'n most co-ntries" remo&ing the *oc is

*ega*.


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the net)or (and not &ice &ersa!. The sec-rit, mode* there/ore o//ers con/identia*it, and

a-thentication" +-t *imited a-thori=ation capa+i*ities" and no non3rep-diation.

#$M -ses se&era* cr,ptographic a*gorithms /or sec-rit,. The A7F1 and A7F2 stream ciphe

are -sed /or ens-ring o&er3the3air &oice pri&ac,. A7F1 )as de&e*oped /irst and is a stronge

a*gorithm -sed )ithin -rope and the


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GSM AT COMMANDS

S8n!a7 R% FOR GSM

A command string sho-*d start )ith VATV or VatV" ecept /or the commands

VAFV and VDDDV. At or aT are in&a*id.

$e&era* commands can +e gi&en in one command string.

The commands can +e gi&en in -pper or *o)er case.

A command string sho-*d contain *ess than 46 characters.

0hen an error is made d-ring the t,ping o/ the command" it can +e corrected

-sing the +acspace e,.

Commands and command strings m-st +e terminated )ith an BTR\"

ecept DDD and AF

A te*ephone n-m+er can eist o/ /o**o)ing characters> 1 2 ? 4 7 I 8 G ] E" O

^ D \ . A** other characters are ignored (space" -nderscore!. The, he*p

/ormatting the dia*string.

Commands that -se a n-merica* parameter can +e -sed )itho-t a n-merica*

&a*-e. 'n this case the command )i** +e iss-ed )ith the &a*-e =ero.

'/ the command string contains t)o consec-ti&e commands )itho-t

parameter" as disc-ssed a+o&e" the modem )i** respond )ith an error.

http://en.wikipedia.org/wiki/Cryptographic_keyhttp://en.wikipedia.org/wiki/Subscriber_Identity_Modulehttp://en.wikipedia.org/wiki/Ciphertext-only_attackhttp://en.wikipedia.org/wiki/Ciphertext-only_attackhttp://www.tech-faq.com/gprs-general-packet-radio-service.shtmlhttp://www.tech-faq.com/gprs-general-packet-radio-service.shtmlhttp://www.tech-faq.com/edge.shtmlhttp://www.tech-faq.com/edge.shtmlhttp://en.wikipedia.org/wiki/Non-repudiationhttp://en.wikipedia.org/wiki/A5/1http://en.wikipedia.org/wiki/A5/2http://en.wikipedia.org/wiki/Stream_cipherhttp://en.wikipedia.org/wiki/Cryptographic_keyhttp://en.wikipedia.org/wiki/Cryptographic_keyhttp://en.wikipedia.org/wiki/Subscriber_Identity_Modulehttp://en.wikipedia.org/wiki/Ciphertext-only_attackhttp://www.tech-faq.com/hscsd-high-speed-circuit-switched-data.shtmlhttp://www.tech-faq.com/gprs-general-packet-radio-service.shtmlhttp://www.tech-faq.com/edge.shtmlhttp://www.tech-faq.com/edge.shtmlhttp://www.tech-faq.com/gsm.shtml


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A/ter the command ATU has +een iss-ed" a pa-se o/ t)o seconds sho-*d +e

respected +e/ore entering the net commands

GSM AT COMMANDS

AT

AT4D

ATKIFC

ATCMGF-

ATKCNMI,,

AT c#an$% 0a!r%

1 Wa'c in %!!in"%

A seria* *in hand*er is set )ith the /o**o)ing de/a-*t &a*-es (/actor, settings!>

a-to+a-d" 8 +its data" 1 stop +it" no parit," RT$ FCT$ /*o) contro*.

P*ease -se the D'PR" D'C and D'C commands to change these settings.

, C#an$ in


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Commands a*)a,s start )ith AT ()hich means ATtention! and /inish )ith a CR\

character.

? In0&r#a!i&n r%*&n%% an$ r%! c&$%

Responses start and end )ith CR\L\" ecept /or the AT@6 %C response

/ormat! and the ATN1 (res-*t code s-ppression! commands.

'/ command s,nta is incorrect" an RRR string is ret-rned.

'/ command s,nta is correct +-t )ith some incorrect parameters" the DCM

RRR> rr\ or DCM$ RRR> $msrr\ strings are ret-rned )ith

di//erent error codes.

'/ the command *ine has +een per/ormed s-ccess/-**," an ; string is

ret-rned.

'n some cases" s-ch as “ATDCP'B_” or (-nso*icited! incoming e&ents" the prod-ct

does not ret-rn the ; string as a response. 'n the /o**o)ing eamp*es CR\ and

CR\L\ are intentiona**, omitted.

SIM In%r!i&n? SIM R#&'a


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$'M card 'nsertion and Remo&a* proced-res are s-pported. There are so/t)are

/-nctions re*,ing on positi&e reading o/ the hard)are $'M detect pin. This pin state

(openFc*osed! is permanent*, monitored.

0hen the $'M detect pin indicates that a card is present in the $'M connector" the

prod-ct tries to set -p a *ogica* $'M session. The *ogica* $'M session )i** +e set -p

or not depending on )hether the detected card is a $'M Card or not.

The ATDCP'B_ command de*i&ers the /o**o)ing responses>

・'/ the $'M detect pin indicates “a+sent”" the response to ATDCP'B_ 's “DCM

RRR 16” ($'M not inserted!.

'/ the $'M detect pin indicates “present”" and the inserted Card is a $'M

Card" the response to ATDCP'B_ is “DCP'B> ” depending on $'M P'B

state.

'/ the $'M detect pin indicates “present”" and the inserted Card is not a $'M

Card" the response to ATDCP'B_ is CM RRR 16.

These *ast t)o states are not gi&en immediate*, d-e to +acgro-nd

initia*i=ation. 5et)een the hard)are $'M detect pin indicating “present” and

the pre&io-s res-*ts the ATDCP'B_ sends “DCM RRR> 717” (P*ease

)ait" init in progress!.

0hen the $'M detect pin indicates card a+sence" and i/ a $'M Card )as

pre&io-s*, inserted" an 'M$' detach proced-re is per/ormed" a** -ser data is

remo&ed /rom the prod-ct (Phone+oos" $M$ etc.!. The prod-ct then s)itches to

emergenc, mode mode.


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Bac6"r&n$ ini!iai

)hen tr,ing to eec-te another AT command +e/ore the pre&io-s one is

comp*eted (+e/ore response!"

)hen s)itching /rom A%B to %B (or %B to A%B! and tr,ing to read the

re*e&ant phone+oo immediate*,"

)hen asing /or DCP'B_ stat-s immediate*, a/ter $'M insertion and +e/ore

the prod-ct has determined i/ the inserted card is a &a*id $'M Card.

, AT4D

$et %TR signa* %

Description


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This command contro*s the %ata Termina* Read, (%TR! signa*. %TR is a signa*

indicating that the comp-ter is read, /or transmission.

I. To dia* the remote M%M dem" ,o- need to -se the termina* program. o-

sho-*d dia* the modem +, sending the /o**o)ing command>

II AT %6 %T telephone number +E,ample- AT"$ "T 1/ 0&%&&(####'

III The 9%6: command te**s the modem to not hang -p the *ine )hen the %TR

signa* is dropped. $ince )e )i** ha&e to eit the termina* program" the

comm-nications port is reset and the %TR signa* is dropped. '/ the modem

disconnected at this point" )e )o-*dn:t +e a+*e to connect to the PLC )ith %irect

$o/t. 0ith some modems (


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not +e a+*e to get contro* o/ the comm-nications port and ,o- )i** not +e a+*e to

get on*ine.

V. $tart %irect$o/t *ie ,o- )o-*d norma**,. Create a ne) *in -sing the

comm-nications port that ,o-r modem is connected to.

3 AT K IFC (?)

D%cri*!i&n

Command s,nta> ATD'CE%C`+,`%T\"%T`+,`%C\

This command is -sed to contro* the operation o/ *oca* /*o) contro* +et)een the

%T and %C

The terms %T and %C are &er, common in the data comm-nications maret.

%T is short /or %ata Termina* -ipment and %C stands /or %ata

Comm-nications -ipment. 5-t )hat do the, rea**, mean_ As the /-** %T

name indicates this is a piece o/ de&ice that ends a comm-nication *ine" )hereas

the %C pro&ides a path /or comm-nication.

. AT CMGF -


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%escription>

The message /ormats s-pported are tet mode and P%< mode.

'n P%< mode" a comp*ete $M$ Message inc*-ding a** header in/ormation is gi&en

as a +inar, string (in headecima* /ormat!. There/ore" on*, the /o**o)ing set o/

characters is a**o)ed> 96:":1:":2:":?:":4:":7:":I:"::":8:":G:" 9A:"

95:":C:":%:"::"::b. ach pair or characters are con&erted to a +,te (e.g.> 941: is

con&erted to the A$C'' character 9A:" )hose A$C'' code is 641 or I7!.

'n Tet mode" a** commands and responses are in A$C'' characters. The /ormat

se*ected is stored in PRM +, the DC$A$ command.

ATKCNMI ,,

ATKCNMI: N5 M%%a" in$ica!i&n !& TE


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C#an$ P&%%i@ r%*&n%(%)

DCBM'EXmode\X"mt\X"+m\X"ds\X"+/r\Y

YYYY

DCBM'_DCBM'>

mode\"mt\"+m\"ds\"+/r\

DCBM'E_

DC$C5> (*ist o/ s-pported

mode\s"mt\s"+m\s"ds\s"+/

r\s!

mode\> 6> +-//er in TAO

1> discard indication and reject ne) $M$ )hen T3TA *in is reser&edO other)ise

/or)ard direct*,O

2> +-//er ne) $ms )hen T3TA *in is reser&ed and /*-sh them to T a/ter

reser&ationO other)ise /or)ard direct*, to the TO

?> /or)ard direct*, to TO mt\> 6> no $M$3%L'@R are ro-ted to TO

1> DCMT'> mem\"inde\ ro-ted to TO

2> /or a** $M$`%L'@Rs ecept c*ass 2> DCMT> .... ro-ted to TOc*ass 2 is

indicated as in mt\E1O

?> C*ass ?> as in mt\E2O


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other c*asses> As in mt\E1O

+m\> same as mt\" +-t /or C5MsO

ds\> 6> Bo $M$3$TAT $M$3$TAT


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7.Recei&ing sms -sing AT commands

I.


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#o to $TARTProgramsAccessoriesComm-nicationsH,perTermina* (0in 2666!

to create a ne) connection" eg. VM, >

3 CM Port >> As indicated in the T3Modem Contro* Too*

3 5its per second >> 2?6466 ( or s*o)er !

3%ata 5its > 8

3 Parit, > Bone

3 $top 5its > 1

3 *o) Contro* > Hard)are

o- are no) read, to start )oring )ith AT commands. T,pe in VATV and ,o-

sho-*d get a V;V" e*se ,o- ha&e not set-p ,o-r H,perTermina* correct*,. Chec

,o-r port settings and a*so mae s-re ,o-r #$M modem is proper*, connected and

the dri&ers insta**ed.

3 Ini!ia %!* AT c#an$%

0e are read, no) to start )oring )ith AT commands to set-p and chec the

stat-s o/ the #$M modem.

AT Ret-rns a V;V to con/irm that modem is )oring

ATDCP'BEVV To enter the P'B /or ,o-r $'M ( i/ ena+*ed !

ATDCR#_A V6"1V rep*, con/irms ,o-r modem is connected to #$M

net)or

ATDC$N 'ndicates the signa* strength" ?1.GG is maim-m.

http://www.control.com.sg/docs%5CT-ModemUSB_Quick_Start.pdfhttp://www.control.com.sg/docs%5CT-ModemUSB_Quick_Start.pdfhttp://www.control.com.sg/docs%5CT-ModemUSB_Quick_Start.pdfhttp://www.control.com.sg/docs%5CT-ModemUSB_Quick_Start.pdf


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. Sn$in" SMS %in" AT c#an$%

0e s-ggest tr, sending a /e) $M$ -sing the Contro* Too* a+o&e to mae s-re ,o-r

#$M modem can send $M$ +e/ore proceeding. Lets *oo at the AT commands

in&o*&ed ..

ATDCM#E1 To /ormat $M$ as a TT message

ATDC$CAEVDV$et ,o-r $M$ centers n-m+er. Chec )ith ,o-r

pro&ider.

To send a $M$" the AT command to -se is ATDCM#$ ..

ATDCM#$EVD,,,,,V nter\

\ o-r $M$ tet message here Ctr*3U\

The VD,,,,,V is ,o-r receipents mo+i*e n-m+er. Bet" )e )i** *oo at recei&ing

$M$ &ia AT commands.

Rci'in" SMS %in" AT c#an$%

The #$M modem can +e con/ig-red to response in di//erent )a,s )hen it recei&es

a $M$.

a! 'mmediate 3 )hen a $M$ is recei&ed" the $M$s detai*s are immediate*, sent to

the host comp-ter (%T! &ia the DCMT command


ATDCBM'E1"2"6"6"6 $et ho) the modem )i** response )hen a $M$ is


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recei&ed

0hen a ne) $M$ is recei&ed +, the #$M modem" the %T )i** recei&e the

/o**o)ing..

DCMT > VDI1V " " V64F68F?6"2?>26>66D46V

This the tet $M$ message sent to the modem

o-r comp-ter (%T! )i** ha&e to contin-o-s*, monitor the CM seria* port" read

and parse the message.

+! Boti/ication 3 )hen a $M$ is recei&ed" the host comp-ter ( %T ! )i** +e

noti/ied o/ the ne) message. The comp-ter )i** then ha&e to read the message

/rom the indicated memor, *ocation and c*ear the memor, *ocation.


ATDCBM'E1"1"6"6"6$et ho) the modem )i** response )hen a $M$ is

recei&ed

0hen a ne) $M$ is recei&ed +, the #$M modem" the %T )i** recei&e the

/o**o)ing ..

DCMT'> V$MV"? Boti/ication sent to the comp-ter. Location ? in $'M

memor,


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ATDCM#RE? nter\AT command to send read the recei&ed $M$ /rom

modem

The modem )i** then send to the comp-ter detai*s o/ the recei&ed $M$ /rom the

speci/ied memor, *ocation ( eg. ? ! ..

DCM#R> VRC RA%V"VDI1V""V64F68F28"22>2I>2GD46V

This is the ne) $M$ recei&ed +, the #$M modem

A/ter reading and parsing the ne) $M$ message" the comp-ter (%T! sho-*d send

a AT command to c*ear the memor, *ocation in the #$M modem ..

ATDCM#%E? nter\ To c*ear the $M$ recei&e memor, *ocation in the #$M

modem

'/ the comp-ter tries to read a empt,Fc*eared memor, *ocation" a DCM$ RRR>

?21 )i** +e sent to the comp-ter.

U%in" a c*!r *r&"ra# !& %n$ an$ rci' SMS

nce )e are a+*e to )or the modem -sing AT commands" )e can -se high3*e&e*

programming ( eg. @5" C" Ka&a ! to send the AT A$C'' commands to and readmessages /rom the CM seria* port that the #$M modem is attached to.

#$M 'BTRAC% T M'CRCBTRLLR


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#$M M%


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RS,3, (%ria *&r!)

R$32?2 (Recommended $tandard 3 2?2! is a te*ecomm-nications standard /or +inar, seria* comm-nications +et)een de&ices. 't s-pp*ies the roadmap /or the )a,

de&ices spea to each other -sing seria* ports. The de&ices are common*, re/erred

to as a %T (data termina* e-ipment! and %C (data comm-nications

e-ipment!O /or eamp*e" a comp-ter and modem" respecti&e*,.

R$2?2 is the most no)n seria* port -sed in transmitting the data in

comm-nication and inter/ace. &en tho-gh seria* port is harder to program than the

para**e* port" this is the most e//ecti&e method in )hich the data transmission

re-ires *ess )ires that ,ie*ds to the *ess cost. The R$2?2 is the comm-nication

*ine )hich ena+*es the data transmission +, on*, -sing three )ire *ins. The three

*ins pro&ides 9transmit:" 9recei&e: and common gro-nd...

The 9transmit: and 9recei&e: *ine on this connecter send and recei&e data +et)een

the comp-ters. As the name indicates" the data is transmitted seria**,. The t)o pins

are T% R%. There are other *ines on this port as RT$" CT$" %$R" %TR" and

RT$" R'. The 91: and 96: are the data )hich de/ines a &o*tage *e&e* o/ ?@ to 27@

and 3?@ to 327@ respecti&e*,.

he e*ectrica* characteristics o/ the seria* port as per the 'A (*ectronics 'nd-str,

Association! R$2?2C $tandard speci/ies a maim-m +a-d rate o/ 26"666+ps"

)hich is s*o) compared to toda,:s standard speed. or this reason" )e ha&e chosen

the ne) R$32?2% $tandard" )hich )as recent*, re*eased.

The R$32?2% has eisted in t)o t,pes. i.e." %3TP 27 pin connector and %3

TP G pin connector" )hich are ma*e connectors on the +ac o/ the PC. o- need


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a /ema*e connector on ,o-r comm-nication /rom Host to #-est comp-ter. The pin

o-ts o/ +oth %3G %327 are sho) +e*o)

%3T,pe3G

pin no.

%3T,pe327

pin no.

Pin o-ts -nction

? 2 R% Recei&e %ata ($eria* data inp-t!

2 ? T% Transmit %ata ($eria* data o-tp-t!

4 RT$ Re-est to send (acno)*edge to modem

that


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0hen comm-nicating )ith &ario-s micro processors one needs to con&ert the

R$2?2 *e&e*s do)n to *o)er *e&e*s" t,pica**, ?.? or 7.6 @&!% Here is a cheap and

simp*e )a, to do that. Sria RS2,3, (@.24! comm-nication )ors )ith &o*tages

317@ to D17@ /or high and *o). n the other hand" TTL *ogic operates +et)een

6@ and D7@ . Modern *o) po)er cons-mption *ogic operates in the range o/ 6@

and D?.?@ or e&en *o)er.

RS2,3, TTL L&"ic

317@ 3?@ D2@ D7@ High

D?@ D17@ 6@ D6.8@ Lo)

Th-s the R$32?2 signa* *e&e*s are /ar too high TTL c!r&nic%? and the negati&e

R$32?2 &o*tage /or high can:t +e hand*ed at a** +, comp-ter *ogic. To recei&e seria*


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data /rom an R$32?2 inter/ace the &o*tage has to +e red-ced. A*so the *o) and

high &o*tage *e&e* has to +e in&erted. This *e&e* con&erter -ses a Ma7,3, and /i&e

ca*aci!&r%. The ma2?2 is -ite cheap (*ess than 7 do**ars! or i/ ,o-re *-c, ,o-

can get a /ree samp*e /rom Ma7i# The MA2?2 /rom Ma7i# )as the /irst 'C

)hich in one pacage contains the necessar, dri&ers and recei&ers to adapt the R$3

2?2 signa* &o*tage *e&e*s to TTL *ogic. 't +ecame pop-*ar" +eca-se it j-st needs one

&o*tage (D7@ or D?.?@! and generates the necessar, R$32?2 &o*tage *e&e*s.

MA 2?2 P'B %'A#RAM

D333F333D

1 3C1D @cc3 1I

2 3@D gnd3 17

? 3C13 T13 14

4 3C2D R1'3 1?

7 3C23 R13 12

I 3@3 T1'3 11 3T2 T2'3 16

8 3R2' R23 G

D33333333D

RS,3, INTERFACED TO MAX ,3,


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J 2

1

2

3

4

5

6

7

8

9

P 3 . 0

5 V

C 4

0 . 1 u f

C 7

0 . 1 u f

T X D

C 6

0 . 1 u f

P 3 . 1

T 1 O U T

C 1

1 u f

T 1 O U T

U 3

M A X 3 2 3 2 1 5

1 6

1 3

8

1 0

1 1

1

3

4

5

2

6

1 2

9

1 4

7

G

N

D

V

C

CR 1 I N

R 2 I N

T 2 I N

T 1 I N

C 1 +

C 1 -

C 2 +

C 2 -

V +

V -

R 1 O U T

R 2 O U T

T 1 O U T

T 2 O U T

C 5

0 . 1 u f

R X D

Rs2?2 is G pin d+ connector" on*, three pins o/ this are -sed ie 2"?"7 the transmit

pin o/ rs2?2 is connected to r pin o/ microcontro**er

Ma7,3, in!r0ac$ !& #icr&c&n!r&r

MA2?2 is connected to the microcontro**er as sho)n in the /ig-re a+o&e 11" 12

pin are connected to the 16 and 11 pin ie transmit and recei&e pin o/

microcontro**er


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DC MOTOR

Princi*% &0 &*ra!i&n

'n an, e*ectric motor" operation is +ased on simp*e e*ectromagnetism. A

c-rrent3carr,ing cond-ctor generates a magnetic /ie*dO )hen this is then p*aced in

an eterna* magnetic /ie*d" it )i** eperience a /orce proportiona* to the c-rrent in

the cond-ctor" and to the strength o/ the eterna* magnetic /ie*d. As ,o- are )e**

a)are o/ /rom p*a,ing )ith magnets as a id" opposite (Borth and $o-th! po*arities

attract" )hi*e *ie po*arities (Borth and Borth" $o-th and $o-th! repe*. The interna*

con/ig-ration o/ a %C motor is designed to harness the magnetic interaction

+et)een a c-rrent3carr,ing cond-ctor and an eterna* magnetic /ie*d to generate

rotationa* motion.

Lets start +, *ooing at a simp*e 23po*e %C e*ectric motor (here red

represents a magnet or )inding )ith a VBorthV po*ari=ation" )hi*e green represents

a magnet or )inding )ith a V$o-thV po*ari=ation!.


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&er, %C motor has si +asic parts 33 a*e" rotor (a..a." A@Rat-re!" stator"

comm-tator" /ie*d magnet(s!" and +r-shes. 'n most common %C motors (and a**

that 5AMers )i** see!" the eterna* magnetic /ie*d is prod-ced +, high3strength

permanent magnets1. The stator is the stationar, part o/ the motor 33 this inc*-des

the motor casing" as )e** as t)o or more permanent magnet po*e pieces. The rotor

(together )ith the a*e and attached comm-tator! rotate )ith respect to the stator.

The rotor consists o/ )indings (genera**, on a core!" the )indings +eing

e*ectrica**, connected to the comm-tator. The a+o&e diagram sho)s a common

motor *a,o-t 33 )ith the rotor inside the stator (/ie*d! magnets.

The geometr, o/ the +r-shes" comm-tator contacts" and rotor )indings

http://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.html


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are s-ch that )hen po)er is app*ied" the po*arities o/ the energi=ed )inding and

the stator magnet(s! are misa*igned" and the rotor )i** rotate -nti* it is a*most

a*igned )ith the stators /ie*d magnets. As the rotor reaches a*ignment" the +r-shes

mo&e to the net comm-tator contacts" and energi=e the net )inding. #i&en o-r

eamp*e t)o3po*e motor" the rotation re&erses the direction o/ c-rrent thro-gh the

rotor )inding" *eading to a V/*ipV o/ the rotors magnetic /ie*d" dri&ing it to contin-e

rotating.

'n rea* *i/e" tho-gh" %C motors )i** a*)a,s ha&e more than t)o po*es (three

is a &er, common n-m+er!. 'n partic-*ar" this a&oids Vdead spotsV in the

comm-tator. o- can imagine ho) )ith o-r eamp*e t)o3po*e motor" i/ the rotor is

eact*, at the midd*e o/ its rotation (per/ect*, a*igned )ith the /ie*d magnets!" it

)i** get Vst-cV there. Mean)hi*e" )ith a t)o3po*e motor" there is a moment )here

the comm-tator shorts o-t the po)er s-pp*, (i.e." +oth +r-shes to-ch +oth

comm-tator contacts sim-*taneo-s*,!. This )o-*d +e +ad /or the po)er s-pp*,"

)aste energ," and damage motor components as )e**. et another disad&antage o/

s-ch a simp*e motor is that it )o-*d ehi+it a high amo-nt o/ tor-e Vripp*eV (the

amo-nt o/ tor-e it co-*d prod-ce is c,c*ic )ith the position o/ the rotor!.

$o since most sma** %C motors are o/ a three3po*e design" *ets tiner )ith the

)orings o/ one &ia an interacti&e animation (Ka&a$cript re-ired!>

http://encyclobeamia.solarbotics.net/articles/beam.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/beam.html


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o-** notice a /e) things /rom this 33 name*," one po*e is /-**, energi=ed at a time

(+-t t)o others are Vpartia**,V energi=ed!. As each +r-sh transitions /rom one

comm-tator contact to the net" one coi*s /ie*d )i** rapid*, co**apse" as the net

coi*s /ie*d )i** rapid*, charge -p (this occ-rs )ithin a /e) microsecond!. 0e** see

more a+o-t the e//ects o/ this *ater" +-t in the meantime ,o- can see that this is a

direct res-*t o/ the coi* )indings series )iring>

Theres pr o+a+*, no +etter )a, to see ho) an a&erage %C motor is p-t together"

than +, j-st opening one -p.

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