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Controlling of an FPGA-Based Multi-Unit Permanent Magnet
Synchronous Motor Drive System
by
Sarayut Amornwongpeeti
A dissertation submitted in partial fulfillment of the requirements for the
degree of Doctoral of Engineering in
Microelectronics and Embedded Systems
Examination Committee: Dr. Mongkol Ekpanyapong (Chairperson)
Dr. Júlio M. de Sousa Barreiros Martins (Co-Chairperson)
Dr. Manukid Parnichkun
Dr. João Luiz Afonso (External Expert)
Dr. Nattapon Chayopitak (External Expert)
External Examiner: Prof. Carlos Alberto C.M. Couto
Department of Industrial Electronics
University of Minho
Portugal
Nationality: Thai
Previous Degree: Master of Engineering in Microelectronics
Asian Institute of Technology
Thailand
Scholarship Donor: Royal Thai Government-AIT Fellowship
Asian Institute of Technology
School of Engineering and Technology
Thailand
December 2015
ii
ACKNOWLEDGEMENTS
I would like to express my deepest gratitude to my thesis advisor, Dr. Mongkol
Ekpanyapong, for his patience and continuous supports during a long journey of my
research endeavor. I am also extremely grateful to Dr. Mongkol for providing me with
invaluable ideas, problem-solving discussions, and personal matter advice. Indeed, I feel
greatly honored and appreciated to have worked under his supervision throughout the
period of my academic life from the Master Degree to the Doctoral Degree at the Asian
Institute of Technology (AIT), Thailand. This thesis work would not have been possible
without his guidance, valuable time, and steadfast supports during my graduate
program.
I would like to express my extremely gratitude to my thesis co-advisor,
Dr. Julio Martins for his generous supports and assistance during my stay at the
University of Minho, Portugal. It was a great privilege for me to have been supervised
by him. I am very grateful to Prof. Dr. João Monteiro for his benevolence and giving me
an opportunity to join a graduate program with the Department of Industrial Electronics
at the University of Minho in Portugal.
I also would like to express my extremely gratitude to Dr. João Luiz Afonso for
his constant supports, fruitful guidance, wonderful encouragements, and insightful
suggestions on all my works. In addition, I would like to extend my profound gratitude
for his gentleness and kindness making me feel welcome and very comfortable during
working at the Group of Energy and Power Electronics Laboratory (GEPE), the
University of Minho.
I am deeply grateful and especially thank Dr. Nattapon Chayopitak for his
constant encouragements, helpful discussions, and supporting me technically and
emotionally since I came to the Industrial and Control Automation Laboratory (ICA),
NECTEC, Thailand. He has actively taken a personal interest for reviewing in details,
and also has offered a wealth of suggestions. I am truly indebted to him for his valuable
ideas and cheering me up always until the completion of this thesis work.
I would like to express my sincere gratitude to Dr. Manukid Parnichkun for
serving as a thesis committee and his useful suggestions. I am very grateful to
Prof. Dr. Carlos Couto for serving as an external examiner and reviewing this thesis
work. I am grateful to Dr. Kanokvate Tungpimolrat for his generous supports at the ICA
Laboratory. I am thankful to Dr. Nobutaka Ono for his kindness during my internship
program at the National Institute of Informatics (NII) in Tokyo, Japan. I would like to
thank all GEPE members, Bruno Exposto and friends, for their helps and made my time
at the GEPE laboratory very pleasant and memorable. I also would like to extend my
thanks to all ICA members for their supports at the ICA Laboratory.
Finally, words may not express my deepest gratitude to my dear parents,
Mr. Pornchai Sae-Tae and Ms. Anchalee Amornwongpeeti. I would like to thank them
for being always a source of my motivation and being patient along with me on the way
of my academic journey. I am forever indebted to them for understanding me in all my
pursuits and the way that I would love to do. To dad, although I could initially sense
that you did not encourage me, but at the end of the day I realized that you always
inspire me to follow my passion along this pathway. To mom, I'm deeply grateful for all
the years of working hard to grow me up to this point. There is no any suitable word to
express how much I love you as you are the only person I love the most. Deepest thank
for teaching me the meaning of perseverance. This thesis work is dedicated to my
beloved parents for all their supports in everything throughout my life and their truly
love. To them, I owe the most.
iii
ABSTRACT
The use of multiple unit controllers for parallel processing of multi-unit motor
drive systems can significantly reduce the execution time of the control algorithm.
However, this approach does not only increase the system cost but also incurs in
additional cost of hardware and software interconnections. This thesis presents a fully
integrated single chip Field Programmable Gate Array (FPGA) based solution for
controlling of an independent multi-unit Permanent Magnet Synchronous Motor
(PMSM) drive system with Space Vector Pulse Width Modulation (SVPWM) based
vector control. For multi-unit motor systems, the complexity of control algorithms often
exceeds the resource availability of low-cost FPGA devices. Thus, a system-level
time-division multiplexing scheme applicable for multi-motor control systems is
proposed. Using the proposed method, large identical complex control algorithms can
be simplified into a single compact algorithm, which is fitted and configured into a
low-cost FPGA. The experimental results are shown, confirming the effectiveness of the
proposed multi-unit PMSM motor drive system using an inexpensive controller based
on system-level time-division multiplexing scheme, which can operate simultaneously
with robustness under different operating conditions.
iv
TABLE OF CONTENTS
CHAPTER TITLE PAGE
TITLE PAGE i
ACKNOWLEDGEMENTS ii
ABSTRACT iii
TABLE OF CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES xi
LIST OF ABBREVIATIONS xii
1 INTRODU CTION 1
1.1 Background of the study 1
1.2 Objective of the study 3
1.3 Scope of the study 4
2 LITERATURE REVIEW 5
2.1 Permanent Magnet Synchronous Motor (PMSM) 5
2.2 Mathematical model of PMSM motor 7
2.2.1 Three-phase model of PMSM motor 7
2.2.2 Rotating d-q (Clark's and Park's) transformation 10
2.2.3 The d-q model of PMSM motor 11
2.3 Vector control of PMSM motor drive system 15
2.4 Space Vector Pulse Width Modulation (SVPWM) technique 17
2.5 Review of controller platform for multi-motor control system 22
2.5.1 Software-based MCU controller 25
2.5.2 Hardware-based FPGA controller 26
2.5.3 Multi-unit software/hardware-based controller 27
2.6 FPGA and design flow overview 29
2.6.1 Features of Xilinx Spartan-3E FPGA family 29
2.6.2 Xilinx System Generator (XSG) design flow 29
3 METHODOLOGY 31
3.1 Proposed method of system-level time-division multiplexing 31
3.1.1 Review of design strategies for multi-motor control system 31
3.1.2 Description of the system-level time-division multiplexing 32
scheme
3.1.3 Delay balancing technique 34
3.2 FPGA-based controller design using XSG 36
3.2.1 Position and speed calculation module 36
3.2.2 Speed and current PI regulators module 37
3.2.3 Three-phase SVPWM generator module 38
3.2.4 Rotating coordinate transformation module 38
3.2.5 Time multiplexing and demultiplexing module 39
3.3 Application of a single FPGA chip multi-motor control system 42
3.3.1 Description of cross-coupling multi-motor control system 42
3.3.2 Cross-coupling control for speed synchronization 43
3.4 System development and implementation 46
3.4.1 Simulation model of SVPWM-based vector control PMSM 46
v
motor drive system
3.4.2 FPGA-based controller development 50
3.4.3 Dead time generator circuit 84
3.4.4 Hardware solution using analog multiplexer 86
3.4.5 Experimental setup 89
4 RESULTS AND DISCUSSION 92
4.1 Position and speed calculation module 92
4.2 Single-unit PMSM motor drive system with SVPWM-based 93
vector control scheme
4.3 Multi-unit PMSM motor drive system with SVPWM-based 94
vector control scheme
4.4 Performance analysis of multi-unit PMSM motor drive system 97
4.5 Speed synchronization performance of a cross-coupling 100
multi-motor drive system
5 CONCLUSIONS AND RECOMMENDATIONS 104
5.1 Conclusions 104
5.2 Recommendations 104
6 REFERENCES 106
Appendix A: PMSM motor specifications and parameters 111
Appendix B: Lists of components and datasheets 113
vi
LIST OF FIGURES
FIGURE TITLE PAGE
Figure 1.1 Different FPGA controller topologies for multi-unit PMSM motor 2
drive system: (a) Multi-unit controller; (b) Single high performance
controller with multiple control modules (conventional method);
(c) Single low-cost controller with single control module
(proposed method)
Figure 1.2 Structure of a single chip FPGA-based controller for multi-unit PMSM 2
motor drive system
Figure 2.1 Different machine topologies of PMSM motor: (a) RFPM motor; 6
(b) AFPM motor; (c) TFPM motor
Figure 2.2 Rotor configuration of RFPM motor: (a) Surface Mounted Permanent 7
Magnet (SPM) type; (b) Surface Inset Permanent Magnet (SIPM) type;
(c) Interior/buried Permanent Magnet (IPM) type
Figure 2.3 Conventional wired-wound two-pole three-phase synchronous motor 8
with salient pole rotor
Figure 2.4 PMSM motor d-q axes equivalent circuit: (a) The d-axis; 13
(b) The q-axis
Figure 2.5 Schematic diagram of the SVPWM-based vector control with zero 16
direct-axis current control strategy
Figure 2.6 Block diagram of the decoupling feed-forward d-q axes current 16
controller
Figure 2.7 Block diagram of the d-q axes current controller and the motor model 17
Figure 2.8 Typical circuit of three-phase Voltage Source Inverter (VSI) 17
Figure 2.9 Voltage space vector in the two-axis stationary α-β reference frame 19
Figure 2.10 Reference vector with two adjacent vectors of sector 1 21
Figure 2.11 Switching patterns of SVPWM at each sector 22
Figure 2.12 XSG design flow for motor control system 30
Figure 3.1 Comparison of the system timing diagram: (a) System-level 32
pipelining method; (b) System-level time-division multiplexing
method
Figure 3.2 Block diagram of an overview of the control system hardware 33
implementation with system-level time-division multiplexing
Figure 3.3 Internal hardware architecture with the delay latency of the vector 34
control algorithm
Figure 3.4 Example of the design: (a) With the balancing delay; (b) Without the 35
balancing delay
Figure 3.5 Block diagram of the proposed hardware circuit of position and speed 37
calculation module
Figure 3.6 Block diagram of the digital PI controller 37
Figure 3.7 Block diagram of the three-phase SVPWM generator module 38
Figure 3.8 Block diagram of the time multiplexing and demultiplexing modules 40
Figure 3.9 Timing diagram of the demultiplexing module for motor currents 41
Figure 3.10 Simplified execution diagram of the time multiplexing and 41
demultiplexing modules
Figure 3.11 Arrangement of two rolling stands and motor drive systems 42
Figure 3.12 Structure of a single chip FPGA-based controller for four rolling mill 43
drives
vii
Figure 3.13 Block diagram of the relative-coupling control structure for a 44
four-unit motor drive system
Figure 3.14 Internal structure of a SVPWM-based vector control scheme with 45
relative-coupling control for one rolling mill drive
Figure 3.15 Block diagram of the relative speed block 46
Figure 3.16 Simulation model of the SVPWM-based vector control PMSM motor 46
drive system
Figure 3.17 Simulation model of the SVPWM-based vector control subsystem 47
Figure 3.18 Simulation model of the PMSM motor subsystem 47
Figure 3.19 Simulation model of: (a) The abc-dq transformation subsystem; 47
(b) The dq-αβ transformation subsystem
Figure 3.20 Simulation results showing: (a) Mechanical speed; 48
(b) Electromagnetic torque
Figure 3.21 Simulation results showing: (a) Line-to-line terminal voltage; 48
(b) Three-phase stator current
Figure 3.22 Simulation results showing: (a) The d-axis current; (b) The q-axis 49
current; (c) The d-q axes current
Figure 3.23 Simulation results showing: (a) The d-axis command voltage; 49
(b) The q-axis command voltage; (c) The d-q axes command voltage
Figure 3.24 Simulation results showing: (a) Filtered PWM; (b) Vector sector 50
Figure 3.25 Simulation results showing: (a) Zoom-in view of filtered PWM; 50
(b) Zoom-in view of vector sector
Figure 3.26 Simplified overall system of the XSG-based FPGA controller 51
Figure 3.27 Overall system of the XSG-based FPGA controller 52
Figure 3.28 Internal structure of a FPGA-based speed controller with 53
SVPWM-based vector control scheme
Figure 3.29 Top-level block diagram of the overall motor control system 53
Figure 3.30 Top-level block diagram of the global timing control module 54
Figure 3.31 Flowchart diagram of the global timing control module 54
Figure 3.32 Timing diagram of the global timing control module 55
Figure 3.33 Top-level block diagram of the ADC interface module 55
Figure 3.34 Pin interface and functional diagram of AD7476 55
Figure 3.35 AD7476 serial interface timing diagram 56
Figure 3.36 State machine diagram of the ADC interface module 56
Figure 3.37 Timing diagram of the ADC interface module 56
Figure 3.38 Top-level block diagram of the serial-to-parallel converter module 57
Figure 3.39 Flowchart diagram of the serial-to-parallel converter module 57
Figure 3.40 Timing diagram of the serial-to-parallel converter module 58
Figure 3.41 Top-level block diagram of the parallel-to-serial converter module 58
Figure 3.42 Flowchart diagram of the parallel-to-serial converter module 59
Figure 3.43 Timing diagram of the parallel-to-serial converter module 59
Figure 3.44 Top-level block diagram of the DAC interface module 60
Figure 3.45 Pin interface and functional diagram of DAC121S101 60
Figure 3.46 DAC121S101 serial interface timing diagram 60
Figure 3.47 State machine diagram of the DAC interface module 61
Figure 3.48 Timing diagram of the DAC interface module 61
Figure 3.49 Top-level block diagram of the UART interface module 62
Figure 3.50 Block diagram of a complete UART module 62
Figure 3.51 Simplified block diagram of the UART transmitter 63
Figure 3.52 State machine diagram of the UART transmitter 63
viii
Figure 3.53 Simplified block diagram of the UART receiver 63
Figure 3.54 State machine diagram of the UART receiver 64
Figure 3.55 Connection diagram for the character LDC interface 64
Figure 3.56 State machine diagram of the LDC interface module 65
Figure 3.57 Top-level block diagram of the analog multiplexer interface module 66
Figure 3.58 XSG circuit of the analog multiplexer interface module 66
Figure 3.59 Timing diagram of the analog multiplexer interface module 66
Figure 3.60 Top-level block diagram of DSP for the SVPWM-based vector 67
control algorithm
Figure 3.61 DSP for the SVPWM-based vector control algorithm 68
Figure 3.62 XSG circuit of the digital demultiplexer circuit 69
Figure 3.63 XSG circuit: (a) Time multiplexer module; (b) Time demultiplexing 69
module
Figure 3.64 RTL schematic of the digital demultiplexer, signal conditioning 70
circuit, and time multiplexer module
Figure 3.65 Block diagram of the position and speed calculation module 71
Figure 3.66 Top-level block diagram of the position and speed calculation module 71
Figure 3.67 XSG circuit of the fault trip and interlock circuit 72
Figure 3.68 Top-level block diagram of the SVPWM-based vector control 72
algorithm
Figure 3.69 RTL schematic of the SVPWM-based vector control algorithm 73
Figure 3.70 XSG circuit of the SVPWM-based vector control algorithm with 74
balancing delays
Figure 3.71 Top-level block diagram of the abc-dq transformation 75
Figure 3.72 RTL schematic of the abc-dq transformation 75
Figure 3.73 XSG circuit of the abc-dq transformation 76
Figure 3.74 Top-level block diagram of the speed PI regulator 76
Figure 3.75 XSG circuit of the speed PI regulator 76
Figure 3.76 Top-level block diagram of the dq-αβ transformation 77
Figure 3.77 RTL schematic of the dq-αβ transformation 77
Figure 3.78 XSG circuit of the dq-αβ transformation 78
Figure 3.79 Top-level block diagram of the three-phase SVPWM generator 78
module
Figure 3.80 XSG circuit of the three-phase SVWPM generator module 79
Figure 3.81 CORDIC sin-cos: (a) Top-level block diagram; (b) XSG blocksets 79
Figure 3.82 CORDIC arctan: (a) Top-level block diagram; (b) XSG blocksets 79
Figure 3.83 CORDIC divider: (a) Top-level block diagram; (b) XSG blocksets 79
Figure 3.84 CORDIC square root: (a) Top-level block diagram; (b) XSG blocksets 79
Figure 3.85 Top-level block diagram of the vector sector calculation subsystem 80
Figure 3.86 XSG circuit of the vector sector calculation subsystem 80
Figure 3.87 Top-level block diagram of the time phase calculation subsystem 81
Figure 3.88 RTL schematic of the time phase calculation subsystem 81
Figure 3.89 XSG circuit of the time phase calculation subsystem 82
Figure 3.90 Top-level block diagram of the triangular generator subsystem 82
Figure 3.91 XSG circuit of the triangular generator subsystem 83
Figure 3.92 Top-level block diagram of the PWM generator subsystem 83
Figure 3.93 RTL schematic of the PWM generator subsystem 84
Figure 3.94 XSG circuit of the PWM generator subsystem 84
Figure 3.95 Circuit diagram of the dead time generator circuit 85
Figure 3.96 Timing diagram of the dead time generator circuit 85
ix
Figure 3.97 Experimental results: (a) PWM_in (Yellow) with frequency of 16 kHz 85
at x-axis = 25 μs/div; (b) PWM_in (Yellow) with frequency of 16 kHz
at x-axis = 10 μs/div; (c) PWM_out (Pink) with dead time of 3 μs
at x-axis = 1 μs/div; (d) PWM_outbar (Green) with dead time of
3.5 μs at x-axis = 1 μs/div
Figure 3.98 Connection diagram of the hardware solution using an analog 86
multiplexer (measuring current phase-A)
Figure 3.99 Timing diagram of the analog multiplexer interface module 87
Figure 3.100 Pin configuration and functional diagram of MAX4618 87
Figure 3.101 Experimental results showing the analog multiplexer with 88
fs,analog = 50 kHz: (a) Input analog signals of X0(Yellow), X1(Blue),
X2(Pink), X3(Green) at x-axis = 5 ms/div; (b) Control digital signals
of EN(Yellow), A(Blue), B(Pink) and output analog signal of
X(Green) at x-axis = 2.5 ms/div; (c) Zoom-in view at x-axis =
500 μs/div; (d) Zoom-in view at x-axis = 50 μs/div; (e) Zoom-in view
showing the frequency of A and B of 25 kHz and 50 kHz at x-axis =
10 μs/div; (f) Zoom-in view showing the analog output signal of
X(Green) consists of different multiplexed input analog signals
(X0-X3) at each control digital signal period at x-axis = 5 μs/div
Figure 3.102 Schematic diagram of the complete system of the SVPWM-based 89
vector control four-unit PMSM motor drive
Figure 3.103 Connection diagram of the FPGA pin interface for implementing the 90
four-unit PMSM motor drive system
Figure 3.104 Completed hardware prototype and experimental setup 90
Figure 3.105 MATLAB GUI for on-line parameter setting and real-time monitoring 90
of the four-unit motor drive system
Figure 3.106 Four low-power PMSM motors 91
Figure 3.107 PMSM motor coupling with a 250W DC motor on the motor 91
mounting base
Figure 3.108 Experimental setup of the SVPWM-based vector control PMSM 91
motor drive system during the load-test by using resistive-load lamps
Figure 4.1 Experimental results of the speed calculation module verified with the 92
motor shaft encoder
Figure 4.2 Experimental results of the speed calculation module verified with a 92
function generator
Figure 4.3 Experimental results showing: (a) Filtered PWM waveforms; 94
(b) Vector sector; (c) Electrical position when PMSM1 is running at
1200 rpm
Figure 4.4 Experimental results showing the dynamic responses of speed and 95
stator current of two motors during a step speed command applied to
the motor PMSM1
Figure 4.5 Experimental results showing the dynamic responses of speed and 95
stator current of two motors during a step load change applied to the
motor PMSM1
Figure 4.6 Comparison of speed responses between a conventional method 96
(using two identical modules) and the proposed method
(time-division multiplexing)
Figure 4.7 Experimental results showing dynamic speed responses of four 96
x
motors during a step speed command applied to the motor PMSM1
Figure 4.8 Experimental results showing stator currents of four motors during 97
a step load change applied to the motor PMSM1
Figure 4.9 Experimental results showing dynamic speed responses during load 101
disturbances applied to PMSM1: (a) Conventional control scheme;
(b) Cross-coupling control scheme
Figure 4.10 Experimental results showing speed synchronization error: 101
(a) Conventional control scheme; (b) Cross-coupling control scheme
Figure 4.11 Experimental results showing a comparison of speed responses 102
between a single-motor system and the proposed four-motor system
with time-division multiplexing during step load changes
Figure 4.12 Comparison of the system-timing diagram for the proposed 102
four-motor control system: (a) Single module with pipelining;
(b) Single module with time-division multiplexing
xi
LIST OF TABLES
TABLE TITLE PAGE
Table 2.1 Comparison between the BLDC motor and the PMSM motor 6
Table 2.2 Summary of switching vectors, phase voltage, and line-to-line output 18
voltage
Table 2.3 Switching time calculation for each switching device 21
Table 2.4 Review of the software-based MCU/DSP controller 26
Table 2.5 Review of the hardware-based FPGA controller 27
Table 2.6 Review of the multi-unit software/hardware-based controller 28
Table 2.7 Features of the Spartan-3E FPGA family 29
Table 3.1 LCD character display command set 65
Table 3.2 Truth table of the analog multiplexer IC MAX4618 87
Table 4.1 Detail of resource utilization for controlling of a single-unit of PMSM 93
motor drive system on Xilinx XC3S1600E FPGA Table 4.2 Detail of resource utilization for implementing the proposed 98
time-division multiplexing scheme on XCS1600E FPGA Table 4.3 Comparison of resource utilization for controlling different units of 98
PMSM motors Table 4.4 Comparison of resource utilization between VHDL and XSG 99
implementations for four-unit motors with the proposed time-division
multiplexing scheme Table 4.5 Comparison of chip costs between low-cost and high performance 99
Xilinx FPGAs suitable for this implementation Table 4.6 Comparison of chip costs between commercial MCUs and 100
a low-cost Xilinx FPGA suitable for this implementation
Table 4.7 Comparison of resource utilization for a single-unit and for 103
a four-unit PMSM motor drive system
xii
LIST OF ABBREVIATIONS
AC Alternating current
ADC Analog-to-digital converter
AFPM Axial flux permanent magnet synchronous motor
BLAC Brushless AC
BLDC Brushless DC
CAN Controller area network
CLB Configurable logic block
CORDIC Coordinate Rotation Digital Computer
CPLD Complex programmable logic device
CPU Central processing unit
DAC Digital-to-analog converter
DC Direct current
DSP Digital signal processor
EMF Electromotive force
FOC Field-oriented control
FPGA Field programmable gate array
FSM Finite-state machine
GUI Graphical user interface
HDL Hardware description language
HP Horsepower
HVAC Heating ventilating and air conditioning
IC Integrated circuit
IGBT Insulated-gate bipolar transistor
IP Intellectual property
IPM Interior permanent magnet
LCD Liquid crystal display
LUTs Lookup tables
MIPS Million instructions per second
MCU Microcontroller
MOSFET Metal-oxide-semiconductor field-effect transistor
PC Personal computer
PI Proportional-integral
PID Proportional-integral-derivative
PMSM Permanent magnet synchronous motor
PPR Pulse per revolution
PWM Pulse width modulation
QEP Quadrature encoder pulse
RAM Random access memory
RFPM Radial flux permanent magnet synchronous motor
RTL Register-transfer level
SIPM Surface inset permanent magnet
SHEPWM Selected harmonic elimination pulse width modulation
SPI Serial peripheral interface
SPM Surface mounted permanent magnet
SPWM Sinusoidal pulse width modulation
SoC System on chip
SVPWM Space vector pulse width modulation
THD Total harmonic distortion
xiii
TI Texas Instruments
TFPM Transverse flux permanent magnet synchronous motor
UART Universal asynchronous receiver/transmitter
VHDL VHSIC hardware description language
VSI Voltage source inverter
XSG Xilinx system generator
ZOH Zero-order hold
1
CHAPTER 1
INTRODUCTION
1.1 Background of the study
With the advances in the semiconductor technology and in the modern control
theory, the use of high performance computing and powerful digital controllers in the
area of AC motor control have become ubiquitous in recent years. Nowadays Field
Programmable Gate Arrays (FPGAs) have become a good alternative solution and have
widely been recognized as a promising candidate for the controller platform in high
performance embedded control systems, [1],[2],[3]. This is especially true for
sophisticated motor drive systems [4],[5],[6],[7],[8], such as fully integrated controllers,
sensorless control, sensorless control with an extended Kalman filter algorithms, and
adaptive fuzzy based controller. The hardware-based solution, namely FPGA, provides
some of key advantages over than the traditional software-based solution
(Microcontroller Unit (MCU) and Digital Signal Processing (DSP)), such as fast
computation time, design flexibility, and reliability. By using Hardware Description
Languages (HDLs), such as VHSIC hardware description language (VHDL) and
Verilog HDL, complex digital circuits can be simply designed in hierarchy of modules
in FPGA. Recently, an automatic code generator from the Xilinx system generator
(XSG) for MATLAB Simulink can be used to build complex control algorithms by
generating the HDL code automatically. From motor control design point of view,
although the automatic code generator cannot provide an optimal solution for the design
with minimum area usage, the XSG tool enables system designers to explore and verify
the control algorithm by simulating the controller model in system-level with the short
amount of time, and allows to ad hoc fine-tune for optimal system efficiency without
translating the design into real hardware, which dramatically reduces the design time
comparing with traditional HDL coding [9],[10].
There are several application domains of industrial control systems that require
more than one motor to be controlled simultaneously, either dependently (synchronized)
or independently, such as automobile, military, steel industry, and industrial automation.
The multiple controlled motors can be employed to execute either the same task or
different tasks at the same time. Often, the demand for optimal and harmonious
operation of multi-unit motor system would require sharing of feedback information
from one drive to other drives. By considering such a system, although commercial
DSPs are optimized for single task, the use of a single DSP controller has some practical
limitations when operating with more than two motor drive systems concurrently [11].
These major issues include the interrupt service routine overhead and the worst case
reaction time for fault-detection and fault-handling. The multi-unit controller structure
as shown in Figure 1.1(a) can offer an ideal solution for independent control loops with
parallel processing. Nevertheless, this approach degrades the system integration and
reliability [6], and requires data communication among chips. A single high
performance FPGA with multiple control modules as shown in Figure 1.1(b) offers
tremendous design flexibility for user-specified tasks, which can fully integrate all
identical separated modules into a single chip. Nevertheless the use of expensive
high-end FPGAs is not suitable for mass production where the system cost is the main
concern. Therefore, to overcome these limitations, this thesis proposes a single chip
low-cost FPGA solution with single control module as shown in Figure 1.1(c). The
2
proposed solution with system-level time-division multiplexing can simplify the entire
system into a single hardware module, which can independently operate a group of
multiple motors while maintaining the aspect of system integration and cost
effectiveness. Within the same chip, multiple control algorithms can transmit processing
data to each other control modules internally at the clock speed, which is faster
compared to a classical buffered serial communication. Figure 1.2 shows the detailed
structure of a single chip FPGA-based controller for multi-unit Permanent Magnet
Synchronous Motor (PMSM) drive system.
FPGA
controller
1 2
3 4
(a)
(b)
(c)
Drive MotorController
Feedback
1 2
3 4
1
Figure 1.1: Different FPGA controller topologies for multi-unit PMSM motor
drive system: (a) Multi-unit controller; (b) Single high performance controller with
multiple control modules (conventional method); (c) Single low-cost controller with
single control module (proposed method)
FPGA
controller
Three-phase IGBT-based
voltage source inverter
AB
C
Inverter #N
PMSM #1
PMSM #2
PMSM #3
PMSM #N
Position and current feedback signals
AB
CAB
C
AB
C
Dig
ital
I/O
pin
s
inte
rfac
e
Figure 1.2: Structure of a single chip FPGA-based controller for multi-unit PMSM
motor drive system
3
In recent years, some past works have successfully demonstrated the use of a
single chip FPGA-based solution in the application of multi-unit motor control. A
motion control system for a X-Y table with two PMSM motors has been presented in
[12]. The two motor controller modules were coded in two identical modules separately,
which leads to a large amount of occupied resources. In [13], a single chip FPGA-based
speed controller for electric vehicle applications has been presented. A multiplier
sharing strategy was proposed to solve the limitation of embedded multipliers that are
available in low-cost FPGAs. In [14], the concept of a single chip controller for
controlling of a set of AC machines was originally proposed based on system-level
pipelined operation whereas the whole control algorithm is entirely executed for each
motor in succession one by one. The centralized control scheme using resource sharing
has been implemented in a modular architecture for four AC machines. According to the
literature, considering a system with a large number of motor units, a massive amount of
FPGA resources and embedded multipliers are required for hardware realization, which
leads to the design constrain for low-cost FPGAs.
The time-division multiplexing is an area-efficient resource sharing technique,
which permits a large design to fit on one chip, and has been applied in various
applications, including static compensator [15], and digital predistortion system
[16],[17]. The concept of time-division multiplexing is to switch two or more input
streams into a series of time slots and transfer the processing data across the same set of
functional-equivalent circuit by running at different time segments. By this way,
multi-channel input systems can fully share the same resource by mapping all identical
functional circuits into a single hardware module improving significantly the total
resource utilization. Nevertheless, in [15],[16] the presented method is not an
area-efficient solution since there is a mixing between the circuit-level time-division
multiplexing and the static hardware circuit (time-division multiplexing for multiplier
sharing). In [17], the entire algorithm is executed at the whole module for each
operation, which is similar to the system-level pipelining approach.
1.2 Objective of the study
The main objective of this thesis is to propose the concept of an area-efficient
design method based on system-level time-division multiplexing scheme applicable for
multi-motor control system. The proposed multi-motor control solution with
time-division multiplexing approach can simplify the entire system into a single
hardware module, which can independently operate a group of multiple motors
simultaneously. A case study of a single chip FPGA solution with time-division
multiplex scheme for controlling of a four-unit PMSM motor drive system is
demonstrated. The second objective is to present a cost-effective solution using a
low-cost FPGA for the independent control of a multi-unit PMSM motor drive system.
In addition, often the demand for optimal and harmonious operation of multi-motor
control system would require sharing of feedback information from one drive to other
drives. From the view point of controller implementation, the use of multi-controller
structure degrades system integration and requires data communication among chips.
Thus, the third objective is to propose a fully integrated single chip solution for
cross-coupling multi-motor control systems whereas the use of single chip FPGA does
not only offer the possibility to transmit processing data among controller modules
within the same device, but also effectively reduces board space, component counts, and
total cost of the system.
4
1.3 Scope of the study
The scope of this thesis is listed as follows:
To propose the concept of system-level time-division multiplexing scheme
applicable for multi-motor control system.
To study, design, and develop a digital hardware circuit for FPGA
implementation of the multi-motor controller module with time-division
multiplexing approach.
To study the efficiency of the HDL code generator by comparing between the
VHDL and the XSG implementations.
To design, develop and implement a complete hardware prototype of single chip
FPGA solution for controlling of a four-unit PMSM motor drive system with
Space Vector Pulse Width Modulation (SVPWM) based vector control scheme.
5
CHAPTER 2
LITERATURE REVIEW
2.1 Permanent Magnet Synchronous Motor (PMSM)
An electric motor is an electromechanical device that converts electrical energy
into mechanical motion and can be broadly classified into two different categories as
[18]: DC motor and AC motor. Over the last several decades, the conventional DC
motor, the AC induction motor, and the AC synchronous motor are the three basic
electric machines serving daily needs from small household appliances to large
industrial plants. The permanent magnets have been widely used for both DC and AC
motors. In the case of DC motors, the DC motor with permanent magnet is generally
called as PM DC motor, which is separately excited with the permanent magnets as the
field excitation source. The permanent magnet AC motor is usually considered as a
synchronous motor type according to the synchronous operation of the motor, and also
commonly termed as brushless permanent magnet motor. The permanent magnet AC
motor can be classified based on the shape of back Electromotive Force (EMF)
waveform as [19],[20]: (1) Brushless DC (BLDC) motor, and (2) Permanent Magnet
Synchronous Motor (PMSM). The BLDC motor produces a trapezoidal back EMF at
constant magnitude for 120º electrical degree in both positive and negative half cycles
according to the concentric windings [21]. The PMSM motor generates a sinusoidal
back EMF according to the distributed windings, and sometimes referred to as
Brushless AC (BLAC) [20],[22]. For a closed-loop control of the BLDC motor with
six-step commutation, the BLDC motor is fed from the three-phase inverter with
rectangular current waveforms shifted with 120º electrical degree from each other. The
three-phase inverter is commutated so that the armature current of the BLDC motor is
conducted in any two phases at the same time (one phase is non-conducting at any time)
[23]. Unlike the BLDC motor control scheme, the PMSM motor is fed with the
three-phase inverter with sinusoidal current waveforms. The three-phase inverter is
commutated so that all three-phase armature currents of the PMSM motor are
continuously conducted at the same time [23].
In recent decades, the emergence and availability of the modern rare-earth
permanent magnet with high energy density leads to the tremendous increasing for two
types of machine topology, namely: BLDC motor and PMSM motor. The BLDC and
PMSM motors are getting rapid highly attention and acceptance in industry for high
performance application because of their salient features, such as high efficiency, high
power-to-weight ratio, high torque-to-inertia ratio, compact shape, low noise, and
robustness. Nowadays, these kinds of motors have been widely used in various
household products and industrial applications. By performance comparison, the BLDC
motor is easier to control with six-step commutation driven with rectangular wave
current and low-cost hardware implementation, but it generates large torque pulsation
with low system efficiency [23]. The PMSM motor has the advantages of constant
torque and high efficiency, which is suitable for high performance applications, except
that it requires a sophisticated control algorithm with complex electronics circuit [23]. A
comparison between the BLDC motor and the PMSM motor is summarized in
Table 2.1.
6
Table 2.1: Comparison between the BLDC motor and the PMSM motor
Parameter BLDC PMSM
Flux density distribution Rectangular Sinusoidal
Back EMF Trapezoidal Sinusoidal
Phase current Rectangular Sinusoidal
Torque ripple High Low
Stator winding Concentrated winding Distributed winding
Position sensor Hall effect Encoder/ Resolver
Control complexity Simple Complicated
Speed range Narrow range Wide range
Inverter cost Low cost High cost
Based on the direction of magnetic field, the PMSM can be broadly classified
into three machine topologies [24]: (1) Radial Flux Permanent Magnet (RFPM) motor,
in which the direction of the magnetic flux is along to the radius of machine. (2) Axial
Flux Permanent Magnet (AFPM) motor, in which the direction of the magnetic flux is
parallel to the rotor shaft. (3) Transverse Flux Permanent Magnet (TFPM) motor, in
which the direction of the magnetic flux is perpendicular to the direction of the rotor
rotation. Figure 2.1 shows different machine topologies of PMSM motor.
(a) (b) (c)
Figure 2.1: Different machine topologies of PMSM motor: (a) RFPM motor;
(b) AFPM motor; (c) TFPM motor [24]
Since the RFPM motor is the most commonly used in industry, hence it is
generally termed as PMSM motor. Based on the rotor configuration, RFPM motor can
be classified according to the location of the permanent magnet on the rotor as
[18],[23],[25]: (1) Surface Mounted Permanent Magnet (SPM) type, where the
permanent magnets are glued on the surface of the rotor; (2) Surface Inset Permanent
Magnet (SIPM) type, where the permanent magnets are partially or fully inset into the
rotor core; (3) Interior/buried Permanent Magnet (IPM) type, where the permanent
magnets are buried inside the rotor core. For surface mounted type PM motor, the d-axis
and q-axis inductances (Ld and Lq) are practically considered equal (variation less than
10%) [23], with the same value: Ld = Lq, whereas the rotor magnetic axis (d-axis) is
defined as the direction of the magnetic flux flows through the center line of magnets.
The d-axis inductance is the stator inductance when the d-axis or the rotor magnet
aligned with the stator winding. Because the permanent magnets are mounted on the
surface of the rotor, this type of PM motor is not physically robust, and hence it is fairly
limited to low speed operation [23]. In addition, mounting magnets on the surface also
Stator
Rotor
Stator
Rotor
Stator
Rotor
7
increases the machine volume. However, this type of PM motor is easy to manufacture
and assemble. For surface inset type PM motor, this type of motor is designed to
enhance high speed capability of SPM type motor, and thus, the rotor assembly is
moderate [23]. For interior type PM motor, this type of motor has the d-axis inductance
larger comparing to the q-axis inductance Lq > Ld, resulting in the reluctance torque that
can be beneficial for this type of motor. By considering the interior rotor configuration,
the magnetic reluctance of the q-axis is lower than the d-axis, due the fact that the q-axis
flux path though the air gap is shorter when comparing to the d-axis flux path though
both the air gap and magnets. In addition, burying the permanent magnets also increase
the mechanical protection due to less centrifugal force resulting in this type of motor is
suitable for high speed application [23]. However, the interior rotor has a complicated
structure for assembly [23]. Figure 2.2 shows different rotor configurations of RFPM
motor.
dqN
S
N
S
NN
N
S
S
S
SS
S
NN
N
dqN
S
N
S
NN
N
S
S
S
SS
S
NN
N
dq
N
S
NS
NN
N
S
S
S
SS
S
NN
N
(a) (b) (c)
Figure 2.2: Rotor configuration of RFPM motor:
(a) Surface Mounted Permanent Magnet (SPM) type; (b) Surface Inset Permanent
Magnet (SIPM) type; (c) Interior/buried Permanent Magnet (IPM) type [23]
2.2 Mathematical model of PMSM motor
This subsection introduces the detailed modeling of a PMSM motor in the
three-phase stationary reference frame. The concept of coordinate transformation of
Clark's and Park's in rotating reference frame is discussed. In order to simplify the
mathematical expressions and the analysis of a PMSM motor in both steady-state and
dynamic behaviors, the two-phase d-q model of a PMSM motor is presented.
2.2.1 Three-phase model of PMSM motor
The PMSM motor is a rotating electrical machine with three-phase stator
windings and permanent magnets at the rotor. In classical machine theory, PMSM can
be modeled as a conventional wired-wound rotor synchronous motor as shown in
Figure 2.3, with the exception that magnetic field is provided by the rotor permanent
magnets, instead of being provided by the excited wired-wound DC rotor field
[19],[20]. Thus, mathematical equations of PMSM can be derived from standard
equations of a conventional synchronous motor by neglecting the equation related to the
excited field current. For simplicity of machine analysis, a two-pole three-phase
star-connected stator winding synchronous motor is considered [26].
8
Field
winding
Axis of
phase a
Rotor
direct-axis
Rotor
quadrature-axis
+a
-a
-c
+c
-b
+b
θr
Stator
windingRotation
Axis of
phase b
Axis of
phase c
Figure 2.3: Conventional wired-wound two-pole three-phase synchronous motor
with salient pole rotor [26]
From classical AC machine theory, three-phase stator winding voltage equations
in stator reference frame of PMSM motor can be expressed as [27],[28]:
a a a a
dv R i λ
dt (2.1)
b b b b
dv R i λ
dt (2.2)
c c c c
dv R i λ
dt (2.3)
where va, vb, vc and ia, ib, ic are three-phase terminal phase voltages and three-phase
stator current, respectively, Ra, Rb, Rc are three-phase stator phase resistances, and a,
b, c, are three-phase total stator winding flux linkages. From (2.1) to (2.3), the stator
winding voltage equation can be written in a matrix form as:
0 0
0 0
0 0
a a a a
b b b b
c c c c
v R i λd
v R i λdt
v R i λ
(2.4)
From (2.4), the total stator winding flux linkage vector is defined as summation of the
stator winding flux linkage contributed by the stator current and the stator winding flux
linkage contributed by the rotor permanent magnet and can be expressed as [28]:
, ,
, ,
, ,
a s a r a
b s b r b
c s c r c
λ λ λ
λ λ λ
λ λ λ
(2.5)
where s,a, s,b, s,c, are three-phase stator winding flux linkages contributed by the
stator current, and r,a, r,b, r,c, are three-phase stator flux linkage contributed by the
rotor permanent magnet. The three-phase stator winding flux linkage contributed by the
rotor permanent magnet of a PMSM motor can be expressed in matrix form as:
9
,
,
,
sin
2sin
3
2sin
3
r
r a
r b m r
r c
r
θλ
πλ λ θ
λπ
θ
(2.6)
where m is the constant amplitude flux linkage produced by the rotor permanent
magnet and θr is the rotor position angle. From (2.5), the stator winding flux linkage
contributed by the stator current is defined as [27],[28]:
,
,
,
s a aa ab ac a
s b ba bb bc b
s c ca cb cc c
λ L M M i
λ M L M i
λ M M L i
(2.7)
where Laa, Lbb, Lcc and Mab, Mbc, Mca are three-phase self inductances and mutual
inductances, respectively. By neglecting the stator leakage inductance, self and mutual
inductances can be expressed in term of the electrical rotor angle as the following
equations. For the stator self-inductance [23],
0 2 cos2aa rL L L θ (2.8)
0 2
2cos 2
3bb r
πL L L θ
(2.9)
0 2
2cos 2
3cc r
πL L L θ
(2.10)
For the stator-to-stator mutual inductances [23],
02
2cos 2
2 3ab ba r
L πM M L θ
(2.11)
02 cos 2
2bc cb r
LM M L θ (2.12)
02
2cos 2
2 3ac ca r
L πM M L θ
(2.13)
where L0 is the stator zero-harmonics inductance, L2 is the stator second-harmonics
inductance. From (2.5), thus the total stator winding flux linkage can be rearranged as:
sin
2sin
3
2sin
3
r
a aa ab ac a
b ba bb bc b m r
c ca cb cc c
r
θλ L M M i
πλ M L M i λ θ
λ M M L iπ
θ
(2.14)
10
It can be seen that the total stator winding flux linkages are functions of the rotor
position angle and thus the rotor speed. Therefore, the coefficient of the stator winding
voltage equations in (2.4) are time varying except that when the motor is at standing
still. For avoiding the calculation complexity and facilitating the motor controller
design, the classical direct and quadrature (d-q) theory can be used to model and
analyze AC electrical machines by transforming mathematical equations from the
stationary a-b-c reference frame to the synchronous rotating d-q reference frame where
the stator winding voltage equations are no longer in functions of the rotor position. The
transformation consists of the two steps: (1) Clark's transformation, which transforms
stationary a-b-c reference frame into stationary α-β reference frame; (2) Park's
transformation, which transforms stationary α-β reference into the synchronous rotating
d-q reference frame.
2.2.2 Rotating d-q (Clark's and Park's) transformation
For the rotating d-q transformation, let us define that the q-axis is set to leading
the d-axis in 90 electrical degrees. Thus, according to the Clark's transformation theory,
the three-phase variables in the stationary a-b-c reference frame can be transformed into
the stationary α-β reference frame by using the following equation as [26]:
0
1 11
2 2
2 3 30
3 2 2
1 1 1
2 2 2
α a
β b
c
f f
f f
f f
(2.15)
where the term of matrix element of f can represent with voltages, currents, or the flux
linkages, fα, fβ, f0 are the α-axis, the β-axis, zero sequence component quantities,
respectively, fa, fb, fc are the three-phase a, b, and c phase quantities, respectively. The
inverse Clark's transformation can be expressed as [26]:
0
1 0 1
1 31
2 2
1 31
2 2
a α
b β
c
f f
f f
f f
(2.16)
For Park's transformation, the three-phase variables in the stationary α-β
reference frame can be transformed into the synchronous rotating d-q reference frame
by using the following equation as [26]:
0 0
cos sin 0
sin cos 0
0 0 1
q r r α
d r r β
f θ θ f
f θ θ f
f f
(2.17)
where fd, fq are the d-axis and the q-axis quantities, respectively. The inverse Park's
transformation can be expressed as [26]:
11
0 0
cos sin 0
sin cos 0
0 0 1
α r r q
β r r d
f θ θ f
f θ θ f
f f
(2.18)
By substituting (2.15) into (2.17), the direct transformation from the three-phase
variables in the stationary a-b-c reference frame into the synchronous rotating d-q
reference frame can be derived as [20],[26]:
0
2 2cos cos cos
3 3
2 2 2sin sin sin
3 3 3
1 1 1
2 2 2
r r r
q a
d r r r b
c
π πθ θ θ
f fπ π
f θ θ θ f
f f
(2.19)
Similarly, by substituting (2.18) into (2.16), the direct inverse transformation can be
expressed as [20],[26]:
0
cos sin 1
2 2cos sin 1
3 3
2 2cos sin 1
3 3
r r
a q
b r r d
c
r r
θ θf f
π πf θ θ f
f fπ π
θ θ
(2.20)
2.2.3 The d-q model of PMSM motor
For simplicity of PMSM motor modeling by using the d-q axes theory, the
following assumptions have been made [19],[20]: (1) The magnetic flux density
distribution and MMF in the air gap of the machine is assumed in sinusoidal function
and the space harmonics in the air gap are neglected (the three-phase stator windings are
displaced in 120 electrical degrees with respect to each other with sinusoidal distributed
winding); (2) The eddy current and hysteresis losses are neglected; (3) The magnetic
core saturation and the effect of magnetic saliency are not considered; (4) There is no
dynamic field current; (5) It is assumed that the three-phase voltage and the stator
current supplied to the motor are symmetrical and balanced. Therefore, by substituting
(2.14) into (2.19) the three-phase total stator winding flux linkage in the rotating d-q
reference frame can be derived as:
12
0
2 2cos cos cos
3 3
2 2 2sin sin sin
3 3 3
1 1 1
2 2 2
sin
2sin
3
2sin
r r r
q
d r r r
r
aa ab ac a
ba bb bc b m r
ca cb cc c
r
π πθ θ θ
λπ π
λ θ θ θ
λ
θL M M i
πM L M i λ θ
M M L iπ
θ
3
(2.21)
By using (2.19) and substituting (2.8) to (2.13) into (2.21), three-phase total stator
winding flux linkage in the d-q axes can be obtained as:
0 2
0 2
0 0
30 0
2 03
0 0 12
00 0 0
q q
d d m
L L
λ i
λ L L i λ
λ i
(2.22)
By neglecting the stator leakage inductance, the direct-axis synchronous
inductance (Ld) and the quadrature-axis synchronous inductance (Ld) can be
approximately equal to the d-axis and the q-axis magnetizing inductances. From (2.22),
the d-axis and the q-axis synchronous inductances can be expressed as [23]:
0 2
3
2dL L L (2.23)
0 2
3
2qL L L (2.24)
It can be seen that there are no longer inductances in the d-q axes which are a
function of the rotor position. Therefore, from (2.22) to (2.24), the total stator winding
flux linkage equations along with the d-axis and the q-axis can be written as follows
[19],[20]:
d d d mλ L i λ (2.25)
q q qλ L i (2.26)
Similarly, the stator winding voltage equations in (2.4) can be transformed into the
orthogonal components in the rotating d-q reference frame by using (2.19) as:
13
0
2 2cos cos cos
3 30 0
2 2 2sin sin sin 0 0
3 3 30 0
1 1 1
2 2 2
r r r
q a a a
d r r r b b b
c c c
π πθ θ θ
v R i λπ π d
v θ θ θ R i λdt
v R i λ
(2.27)
By transforming and rearranging the three-phase stator current and three-phase total
stator winding flux linkage into the rotating d-q reference frame, the stator winding
voltage equation of PMSM motor can be obtained as:
0 0 0
0 0
0 0
0 0
q s q q
d
d s d r d
q
s
v R i λλ d
v R i ω λλ dt
v R i λ
(2.28)
where ωr is an electrical rotor speed, and Rs = Ra = Rb = Rc is the stator winding phase
resistance. The stator winding voltage equations in the rotating d-q reference frame can
be expressed as [19],[20]:
d s d r q d
dv R i ω λ λ
dt (2.29)
q s q r d q
dv R i ω λ λ
dt (2.30)
0 0 0s
dv R i λ
dt (2.31)
From the model assumption, it is assumed that the motor is supplied with three-phase
balanced and symmetrical voltage and current. Therefore, the zero sequence stator
current can be set to zero. By substituting (2.25) and (2.26) into (2.29) and (2.30),
respectively, the stator voltage equations of PMSM motor can be rearranged as [23]:
d s d d d r q q
dv R i L i ω L i
dt (2.32)
q s q q q r d d r m
dv R i L i ω L i ω λ
dt (2.33)
Based on the mathematical equations of (2.32) and (2.33), the PMSM motor can be
represented along with the d-q axes with the equivalent circuit diagram as shown in
Figure 2.4.
vd
idRs Ld
ωr Lq iq
vq
iqRs Lq
ωr Ld id
ωr λm
(a) (b)
Figure 2.4: PMSM motor d-q axes equivalent circuit: (a) The d-axis;
(b) The q-axis [23]
14
For a general three-phase AC machine, the expression of electromagnetic torque
developed by the motor can be determined from the input power supplied to the motor
that is transferred across the air gap. The three-phase input power supplied to the motor
(Pin) can be expressed as [19],[20],[23]:
in a a b b c cP v i v i v i (2.34)
By using (2.19), the stator phase voltage and the stator current can be transformed into
the rotating d-q axes transformation. Thus, the input power can be rewritten as [23]:
0 0
32
2in q q d dP v i v i v i
(2.35)
Substituting (2.29) to (2.31) into (2.35),
2 2 2
0 0
32
2in s q d q q d d r d q q d
d dP r i i i λ i λ ω λ i λ i i r
dt dt
(2.36)
It can be seen that the input power consists of the stator resistive loss term, the rate of
change of the stored magnetic energy term, the air gap power term which associated
with the rotor speed, and the zero sequence component term. Thus, the air gap power
(Pe), which is defined as a product of the electromagnetic torque and the mechanical
rotor speed, can be expressed as:
3
2e r d q q dP ω λ i λ i
(2.37)
For multi-pole PMSM motors, the relation between the electrical rotor speed (ωr) and
the mechanical rotor speed (ωm) can be written as:
r mω pω (2.38)
where p is the number of pole pairs of the machine, thus (2.37) becomes,
3
2e m d q q dP p ω λ i λ i
(2.39)
As a result, the air gap electromagnetic torque of PMSM motor can be determined by
dividing the air gap power with the mechanical speed of the rotor as:
3
2
ee d q q d
m
PT p λ i λ i
ω (2.40)
By substituting (2.25) and (2.26) into (2.40), the electromagnetic torque can be written
as [23]:
3
)2
e m q d q d qT p λ i L L i i
(2.41)
It can be seen that the electromagnetic torque consists of two components: (1)
The magnetic torque due to the rotor permanent magnet flux is proportional directly to
only the q-axis stator current and independent to the d-axis stator current; (2) The
reluctance torque due to the interact between the d-axis and the q-axis inductances, is
proportional to the product of id and iq. The factor 3/2 in the equation is a result from the
power equivalent transformation between the three-phase machine into the two-phase
15
machine. It can be noted that in case of surface mounted permanent magnet type motor,
the additional reluctance torque cannot be fully utilized since the rotor saliency is
negligible (Ld = Lq). For interior permanent magnet type machine, the q-axis inductance
is always larger than the d-axis inductance. Thus, by controlling the d-axis current with
a negative value, the reluctance torque component of the interior rotor type machine
becomes positive quantity and can be fully utilized for high performance motor control
applications.
For a dynamic model of PMSM motor, the mechanical equation of the motor can
be expressed as [23]:
me m L
dωJ T Bω T
dt (2.42)
where J is the total moment of inertia of the machine and load combined, B is the
viscous friction coefficient, TL is the load torque, m is the mechanical angular speed.
2.3 Vector control of PMSM motor drive system
Vector control is one of the most popular control method for high performance
motor drive systems. The concept of vector control is to convert the three-phase time
and speed dependent system into a two-axis coordination (d-q axes) time invariant
system so that both the d-axis current (flux-producing current) and the q-axis current
(torque-producing current) can be decoupled and controlled independently [23]. The
three-phase stationary quantities are transformed into two constant components in
rotating reference frame, the d-axis current axis aligned with the directing of the rotor
flux phasor, and the q-axis current axis aligned in perpendicular to the rotor flux phasor.
The objective of the vector control is to maintain the amplitude of the rotor flux linkage
at a constant value, except for the operating condition in field-weakening region, and to
command the torque-producing current in order to control the motor electromagnetic
torque. In other words, by keeping the flux-producing current component at a fixed
value, the electromagnetic torque is linearly proportional to the torque-producing
current component. As a result, the AC motor behaves as if it is a separately excited
field DC motor. The zero direct-axis current control strategy is the most widely used
control strategy for PMSM motor drive due to the linear relationship between the torque
and current [23]. From (2.40), when the d-axis current is controlled to be zero, then the
electromagnetic torque is expressed as [23]:
3
2e m qT p λ i (2.43)
since the flux linkage of permanent magnet (m) is constant in the d-q axes, the
electromagnetic torque is linearly proportional to the q-axis current. As the result, the
electromagnetic torque can be controlled easily by controlling the q-axis current.
The schematic diagram of the SVPWM-based vector control with zero
direct-axis current control strategy for PMSM motor drive system is shown in
Figure 2.5. In this control scheme [29], the two speed and current control loops are
implemented for the speed control motor drive system whereas the inner loop is used for
the motor current control and the outer loop is used for motor speed control. The motor
reference values are denoted with the asterisk (*). The actual mechanical speed (m)
obtained from the position sensor of an incremental encoder is compared with the
16
reference speed (m*). The error between mechanical speed is regulated by the
proportional integral (PI) speed controller in order to generate the reference torque
signal (Te*). The reference torque is then converted by torque gain constant into the
q-axis reference current (iq*). The actual d-q axes currents (id and iq) converted by
Park’s transformation are then compared with the d-q axes reference current. With zero
direct-axis current control strategy, the d-axis reference current is set to zero (id* = 0).
For decoupling feed-forward compensation, the errors from the d-q axes PI current
controller are summed and formed the d-q axes command voltages (vd, vq). The
command voltages are then converted by the inverse Park’s transformation for
implementing the SVPWM algorithm in order to produce PWM control signals. The
generated PWM signals command the switching duty cycle for six power transistors of
the three-phase inverter in order to supply the output voltage with the controlled
amplitude and the frequency to the PMSM motor. From (2.32) and (2.33), it can be seen
that the d-q axes voltages contain the inherent cross coupling effect in the speed voltage
terms, A decoupling feed-forward compensation can be implemented in the current
feedback loop in order to cancel the cross coupling effect in steady-state [30]. Figure 2.6
and Figure 2.7 show a diagram of decoupling feed-forward d-q axes current controller,
and a diagram of the d-q axes current controller and the motor model, respectively.
Controller
-
~~~
Inverter
ωm*
ωm
+_
id*= 0
θe Position and speed
calculation
algorithm
Enc_A
Enc_B
Clark
transform
ia
ib
Encoder
iαiβ
d-axis
current
controller
q-axis
current
controller
Speed
controller
ωm
id
iq
PMSM
SVPWM
iq*
Vdc
∑
Park
transform
vα
vβ
vd
vq
θe
θe
Inverse
Park
transformPMSM
Current feedback
Position feedback
Figure 2.5: Schematic diagram of the SVPWM-based vector control with zero
direct-axis current control strategy
d-axis
PI controller-
id*
iq
vq = ωeLdid+ωeλm
∑
id
+∑
++
-iq
*
∑+
vd = -ωeLqiq
q-axis
PI controller
ωr
+∑
+
vd*
vq*
Figure 2.6: Block diagram of the decoupling feed-forward d-q axes current
controller
17
id
iq
d-axis current
PI controller∑
+-
∑+
-
id*
iq*
∑
∑ ∑++
vd*
∑++ -
+
ωeLdid
ωeLqiq
+
ωeLqiq
vq*
∑+-
-
1______Ra+Lds
ωeLdid
+
MotorThe d-q axes current controller
ωeλm
id
iq
ωeλm
1______Ra+Lqs
q-axis current
PI controller
Figure 2.7: Block diagram of the d-q axes current controller and the motor model
2.4 Space Vector Pulse Width Modulation (SVPWM) technique
The classification of Pulse Width Modulation (PWM) techniques can be grouped
as [31]: Sinusoidal PWM (SPWM), Selected Harmonic Elimination PWM (SHEPWM),
Random PWM, Hysteresis band current control PWM, and Space Vector PWM
(SVPWM). Since the three-phase power inverter contains a group of six power
electronic switches, it is possible to optimally control the output voltage with the
minimum of total harmonic distortions by using the advance PWM switching technique.
For high performance variable frequency drive applications, SVPWM technique is an
advanced and computational intensive PWM method for generating a fundamental sine
wave that provides higher inverter output voltage to the load, less total harmonic
distortion, greater linear operation range, and lower switching losses when comparing
with SPWM method [32],[33],[34]. The SVPWM method is also well-suited for
implementing the vector control scheme for an AC motor by using the same theory of
rotating reference frame and transformation. Figure 2.8 shows a typical circuit of
three-phase Voltage Source Inverter (VSI). The six switching devices of S1 to S6 are
controlled by the switching variables of a, b, and c. There are eight possible
combinations of on and off patterns for the three upper switches. The combination of
three-phase inverter output voltages from eight space vectors (V0 to V7) is divided into
two types as: six nonzero space vectors (V1 to V6) forming a hexagon with centered at
origin: and two zero space vectors (V0 and V7) located at the origin [33]. The hexagon is
the maximum boundary of the space vector whereas the circle is the maximum
trajectory of the regular sinusoidal outputs in linear modulation.
va
VDC PMSMvb
vc
S1 S3 S5
S4 S6 S2
a b c
a b c
Figure 2.8: Typical circuit of three-phase Voltage Source Inverter (VSI)
18
The relationship between the switching variable vectors [a, b, c]T and the
line-to-line voltage vectors [Vab, Vbc, Vca]T can be expressed as [33]:
1 1 0
0 1 1
1 0 1
ab
bc DC
ca
V a
V V b
V c
(2.44)
and the relationship between the switching variable vectors [a, b, c]T and the phase
voltage vectors [Van, Vbn, Vcn] can be derived as:
1 1 0
0 1 13
1 0 1
an
DCbn
cn
V aV
V b
V c
(2.45)
where VDC is the DC bus voltage of the inverter. By converting into two-phase
orthogonal coordinate system of α-β axes using Clark's transformation, the three-phase
stator voltage can be rearranged as [32],[33]:
1 11
2 2 2
3 3 30
2 2
an
α
bn
β
cn
VV
VV
V
(2.46)
Since there are only eight possible combinations of the power switches, the
values of Vα and Vβ is also limited with a finite number according to the status of
transistor command signals (a, b, c). Table 2.2 shows a summary of switching vectors,
phase voltage, and line-to-line output voltage [33].
Table 2.2: Summary of switching vectors, phase voltage, and line-to-line output
voltage
Vector
Voltages
Switching vectors Line-to-neutral
voltage
Line-to-line
voltage
Vα
Vβ a b c Van Vbn Vcn Vab Vbc Vca
V0 0 0 0 0 0 0 0 0 0 0 0
V1 1 0 0 2/3 -1/3 -1/3 1 0 -1 2/3 0
V2 1 1 0 1/3 1/3 -2/3 0 1 -1 1/3 3/1
V3 0 1 0 -1/3 2/3 -1/3 -1 1 0 -1/3 3/1
V4 0 1 1 -2/3 1/3 1/3 -1 0 1 -2/3 0
V5 0 0 1 -1/3 -1/3 2/3 0 -1 1 1/3 3/1
V6 1 0 1 1/3 -2/3 1/3 1 -1 0 1/3 3/1
V7 1 1 1 0 0 0 0 0 0 0 0
The concept of SVPWM method is to determine the reference voltage vector
(Vref) from the eight switching patterns by generating the average output of the inverter
in a small period as same as the period of the reference voltage vector. For
implementing the SVPWM method, there are three major steps as follows.
19
(1) Determine the value of Vα , Vβ , Vref and the angle (α) of reference voltage
vector. The three-phase stator voltages in a-b-c reference frame are transformed into the
two-axis stationary α-β reference frame by using Clark's transformation as shown in
Figure 2.9. The mathematical voltage equations in stationary α-β reference frame can be
expressed as [33]:
cos cos3 3
1 1
2 2
α an bn cn
an bn cn
π πV V V V
V V V
(2.47)
0 cos cos6 6
3 3
2 2
β bn cn
bn cn
π πV V V
V V
(2.48)
and
2 2
ref α βV V V (2.49)
1tan 2β
α
Vα ωt πtf
V
(2.50)
β
α0 a
c
b
α
Vα
VrefVβ
Figure 2.9: Voltage space vector in the two-axis stationary α-β reference frame
(2) Determine the time duration T1, T2, and T0. The T1 and T2 are the respective
time of the basic space vector V1 and V2 ,which applied within the time period of TZ
whereas the T0 is the course time which the zero vector V0 and V7 are applied. The
relationship between the reference voltage during the time period of Tz and the
summation of two adjacent active vectors (selected from six active vectors V1-V6) and a
zero vector (V7, V8) must be constant. From Figure 2.10, the switching time duration of
sector 1 can be calculated as [33],[34]:
1 1 2
1 1 2
1 2 0
0 0
Z ZT T T T T
ref
T T T
V dt V dt V dt V dt
(2.51)
Thus,
1 1 2 2Z refT V T V T V (2.52)
and
20
1 2
coscos 1 32 2
sin 03 3sin
3
Z ref DC DC
π
αT V T V T V
α π
(2.53)
where 03
πα . As a result, the switching time duration of the basic space vector of
T1, T2, and T0 can be derived as [33],[34]:
1
sin3
sin3
Z
πα
T T aπ
(2.54)
2
sin( )
sin3
Z
αT T a
π
(2.55)
0 1 2ZT T T T (2.56)
where Z
Zf
T1
and
DC
ref
V
Va
3
2 . For switching time duration at any sector, the
equations of switching time at sector n can be written as [33]:
3 1sin
3 3
3sin
3
3sin cos cos sin
3 3
Z ref
n
DC
Z ref
DC
Z ref
DC
T V π nT α π
V
T V nπ α
V
T V n nπ α π α
V
(2.57)
1
3 1sin
3
3 1 1cos sin sin cos
3 3
Z ref
n
DC
Z ref
DC
T V nT α π
V
T V n nα π α π
V
(2.58)
and
0 1Z n nT T T T (2.59)
where n =1 to 6 of any sections, and VDC is the common DC bus voltage, which is
supplied to the three-phase VSI of the system.
21
β
αV1
Vref
V2
V2T2
T1
__
V1T1
T2
__
α
Figure 2.10: Reference vector with two adjacent vectors of sector 1
(3) Determine the switching time of each power transistor switch (S1 to S6).
Assuming that space vector switching patterns are symmetrical at each sector with
sampling time of Ts = 2Tz, thus the switching time calculation of each switching device
(S1 to S6) at any sectors can be determined as indicated in Table 2.3. Figure 2.11 shows
switching patterns of SVPWM at each sector.
Table 2.3: Switching time calculation for each switching device [33]
Sector Upper switches (S1,S3,S5) Lower switches (S4,S6,S2)
1
S1 = T1+T2+T0/2
S3 = T2+T0/2
S5 = T0/2
S4 = T0/2
S6 = T1+T0/2
S2 = T1+T2+T0/2
2
S1 = T1+T0/2
S3 = T1+T2+T0/2
S5 = T0/2
S4 = T2+T0/2
S6 = T0/2
S2 = T1+T2+T0/2
3
S1 = T0/2
S3 = T1+T2+T0/2
S5 = T2+T0/2
S4 = T1+T2+T0/2
S6 = T0/2
S2 = T1+T0/2
4
S1 = T0/2
S3 = T1+T0/2
S5 = T1+T2+T0/2
S4 = T1+T2+T0/2
S6 = T2+T0/2
S2 = T0/2
5
S1 = T2+T0/2
S3 = T0/2
S5 = T1+T2+T0/2
S4 = T1+T0/2
S6 = T1+T2+T0/2
S2 = T0/2
6
S1 = T1+T2+T0/2
S3 = T0/2
S5 = T1+T0/2
S4 = T0/2
S6 = T1+T2+T0/2
S2 = T2+T0/2
22
Upper
T0/2 T1 T2 T0/2 T0/2 T2 T1 T0/2
TZ TZ
Lower
S1
S3
S5
S4
S6
S2
V0 V1 V2 V7 V7 V2 V1 V0
Sector 1
Upper
T0/2 T2 T1 T0/2 T0/2 T1 T2 T0/2
TZ TZ
Lower
S1
S3
S5
S4
S6
S2
V0 V3 V2 V7 V7 V2 V3 V0
Sector 2
Upper
T0/2 T1 T2 T0/2 T0/2 T2 T1 T0/2
TZ TZ
Lower
S1
S3
S5
S4
S6
S2
V0 V3 V4 V7 V7 V4 V3 V0
Sector 3
Upper
T0/2 T2 T1 T0/2 T0/2 T1 T2 T0/2
TZ TZ
Lower
S1
S3
S5
S4
S6
S2
V0 V5 V4 V7 V7 V4 V5 V0
Sector 4
Upper
T0/2 T1 T2 T0/2 T0/2 T2 T1 T0/2
TZ TZ
Lower
S1
S3
S5
S4
S6
S2
V0 V5 V6 V7 V7 V6 V5 V0
Sector 5
Upper
T0/2 T2 T1 T0/2 T0/2 T1 T2 T0/2
TZ TZ
Lower
S1
S3
S5
S4
S6
S2
V0 V1 V6 V7 V7 V6 V1 V0
Sector 6
Figure 2.11: Switching patterns of SVPWM at each sector [33]
2.5 Review of controller platform for multi-motor control system
For controlling of single-unit motor control systems, during the past few decades
a MCU controller platform can be used and fulfilled the control requirements with large
enough bandwidth for low-to-medium performance applications. Zheng et al. presented
a MCU-based speed controller for SVPWM Field-Oriented Control (FOC) control
23
PMSM motor drive system. The Infineon 8-bit XC886 MCU was utilized for
implementing the control algorithm. The total execution time of algorithm is relatively
large to 160 μs, approximately 80% of CPU operation load [35]. In [36], a fully digital
MCU-based PMSM motor drive was presented. The control algorithm have been tested
on an experimental 2.8 kW salient pole PMSM motor. A single board power electronics
control computer is based on an Intel 16-bit 80C196KC MCU. In [37], Liu et al.
presented a cost effective MCU-based SVPWM FOC control PMSM motor drive
system. An experimental PMSM motor of 750 W, 3000 rpm was tested with the
implementation of a low-cost 16-bit MCU dsPIC30F4011 by Microchip Technology. A
sensorless SVPWM vector control scheme of PMSM motor drive system based on
MCU platform for compressor application was developed in [38]. An 8-bit high
performance XC866 microcontroller was used for implementing the control algorithm.
For DSP controller platform, in the past the use of dual DSP controllers are
necessary for high performance fully digital control of AC motor. Nowadays, several
research works on controlling a single-unit motor drive system using a DSP controller
have been widely presented. Recently, a new class of DSP controllers integrates a
variety of sophisticated peripheral on chip and provides the computational capability of
a DSP core, which can be utilized for implementing either multiple functions for one
drive system or multiple drives using only a single DSP controller. In [39], Tzou et al.
proposed a fully digital SVPWM vector control scheme for a high performance
induction servo drives implementing with dual DSP-based controller of TMS320C14
and TMS30C50 platforms. The dual DSP controller platform were linked via a
dual-port Random Access Memory (RAM). The proposed dual DSP-based control
scheme was carried out on a three-phase, 4 pole, 220 V, 1 Horsepower (HP),
squirrel-cage induction motor equipped with 2000 pulses per revolution (PPR) encoder.
The sampling frequency of current loop and speed loop are set to 10 kHz and 2 kHz,
respectively whereas the switching frequency of the PWM inverter is set at 20 kHz.
Arefeen et al. presented a complete implementation of a open-loop SVPWM
Volt/Hz control for three-phase AC induction motor drive with power factor correction
and serial communication using a low-cost DSP controller [40]. The high bandwidth of
16-bit fixed-point TMS320F240 DSP controller enables the designer to integrate
multiple control functions, such as motor control algorithm, power factor correction
scheme, and communication protocol, using a single chip controller. The selected DSP
has features of 20 Million Instructions Per Second (MIPs), 16-bit fixed-point DSP core
with integrated power electronic peripherals including, 12-PWM channels, three 16-bit
timers, 16-channel 10-bit Analog-to-Digital Converter (ADC), four capture pin. The
experimental system consists of a 4 poles, 1/3 HP induction motor, 250 W experimental
power inverter board, and TMS320F240 DSP controller. The software was written in
assembly and was less than 4 kW of program space. The total software loading was
19.3 μs, approximately 59.4 % of DSP bandwidth utilization.
In [41], the vector control PMSM motor drive system using a resolver sensor
was presented. The overall vector control PMSM motor drive system was implemented
on a 32-bit fixed point Texas Instruments (TI) TMS320F2812 DSP digital controller.
Sun et al. presented a design of SVPWM-based vector control PMSM motor drive
system based on TMS320F2812 DSP controller [42]. The six PWM signals were
generated to control the intelligent power module with the SVPWM algorithm. The
incremental encoder equipped with a PMSM motor has 2500 PPR. The control period of
24
current loop was designed of 120 μs while the control period of speed loop is 1 ms. The
execution time of each vector control algorithm is 9.6 μs.
In [43], the implementation of FOC control for PMSM drive based on a 32-bit
fixed point TMS320F2808 controller was presented. The TMS320F2808 DSP has
features of 100 MIPS with 100 MHz clock and combines a number of peripherals, such
as 128 kB of flash memory, 16-channel 12-bit ADC, 16 independent PWM channels,
two Quadrature Encoder Pulse (QEP). The experimental setup was carried out with a
three-phase 8 poles, 2000-line encoder, 100 W PMSM, a DMC-550 power inverter
module, and a TMS320F2808 DSP controller. Seok et al. presented a sensorless speed
control of PMSM drive system using a DSP TMS320VC33 120 MHz controller [44].
The proposed sensorless algorithm is verified on a 0.6 kW PMSM motor coupled with a
0.75 W DC motor and controlled with a PWM IGBT-based VSI of 20 kHz switching
frequency. The sampling periods of the current and speed control loops are 50 μs and
1 ms, respectively.
For FPGA controller platform, in industrial AC motor control applications
nowadays powerful controller platform based on FPGA devices become an attractive
solution to implement digital controller, especially for high performance, high speed,
and multi module applications. The FPGA platform does not only offer high speed and
parallel processing because of its hardware realization, but also offers a freedom to
customize the resolution and binary format of each individual signals. Idkhajine et al.
presented a fully integrated solution for a PMSM motor drive system [4]. The current
control algorithm was implemented on System on Chip (SoC) mixed signal Actel
Fusion FPGA platform integrated processor cores of CoreMP7, Core 8051, and
CortexM1, which enables a higher integration capacity by using the combination of
both software/hardware-based solutions. The AFS600 Fusion FPGA, containing
1384 FPGA tiles, 1 ADC, 40 analog I/Os, 4 Mb flash memory, 108 Kb RAM memory,
was selected as a controller platform for controlling of a 0.8 kW PMSM motor equipped
with a resolver sensor. The whole necessary motor control treatments are integrated in
the same device (resolver processing unit, current control closed loop, analog-to-digital
conversion, and flash memory implementation) in order to ensure that all required
performances were met in term of control quality and time/area performances. The
sampling period was set to 50 μs. A comparison on the effect of execution time between
a hardware-based control delay of 6.5 μs and a software-based control delay of 50 μs on
control quality was presented. It can be seen that current ripples are significantly larger
from 8% Total Harmonic Distortion (THD) to 21% THD when the execution time
become higher and equals to a sampling period of 50 μs.
Alecsa et al. presented the implementation of FPGA-based PMSM motor speed
controller by using the Xilinx System Generator (XSG) design tool [9]. The 100 W
PMSM motor is fed by three-phase VSI with the SVPWM algorithm. The controller
was implemented in a low-cost XC3S500E Spartan-3E Xilinx FPGA. The carrier
frequency was selected of 20 kHz (a sampling period of 50 μs). The whole execution
takes 110 clock cycles (26 clock cycles for control algorithm, 10 clock cycles for
SVPWM algorithm, 74 clock cycles for current acquisition with ADC device), meaning
2.2 μs at 50 MHz clock rate. The embedded multipliers were occupied with 10 of 20,
36 % of the logic resource, and 1 RAM block. In this study, the continuous-time model
is translated into discrete-time model by using the system generator block, which is
directly synthesizable into a low-cost FPGA. The advantage of the holistic approach is
25
to offer the possibility to design the whole system at a high-level of abstraction (the
controller and the control system) and also offer a high degree of correct operation of
the circuit at first time design.
For controlling multi-unit motor control systems, in this thesis literature reviews
are classified based on the controller platform and grouped into three categories as
follows: (1) Software-based MCU/DSP controller; (2) Hardware-based FPGA
controller; and (3) Multi-unit software/hardware-based controller.
2.5.1 Software-based MCU/DSP controller
For MCU/DSP controller platform, the optimized control strategy both energy
efficient and fault tolerant of dual PMSM motors for propulsion system application by
using a single DSP TI TMS320LF2407A controller has been presented in [45]. The
power rating of two PMSM motors is relatively large up to 260 kW (2x130 kW)
implemented in 17 tons weight electric vehicle with 380 VDC.
In [46], the implementation of a dual field-oriented control PMSM motor drive
using a single DSP controller has been presented. A high performance 32-bit DSP-based
controller installed on a development board (TMS320F2808eZDSP) was implemented
with a DMC-550 three-phase VSI with the PWM switching frequency of 20 kHz The
selected DSP controller has a 100 MIPS, 32-bit fixed point DSP core. The integrated
PWM module has 16 PWM outputs while the dual drive system utilized 12 PWM
outputs. The SVPWM-based vector control algorithm was written in C language and
developed using the on-chip memory of the DSP. The two three-phase 100 W PMSM
motors equipped with 2000-line encoders were carried on the laboratory. The
implementation of dual algorithms utilized about 4 kW of program space and 0.5 kW of
data space out of total 64 kW available of flash and 18 kW of RAM of TMS320F2808
controller platform.
In [47], the proposed control scheme using only a single controller to drive a
dual inverter for two separate motors with FOC control technique has been presented.
The control algorithms were implemented by software program on a TMS320LF2407
DSP controller, which contains a 40 MIPs, 16-bit fixed-point DSP core with 12 PWM
output channels. The switching frequency was set to 20 kHz with sampling time of
100 μs.
Shireen et al. presented a controlling multiple motors utilizing a single DSP
controller for Heating Ventilating and Air Conditioning (HVAC) application [48]. The
experimental setup was tested with two AC induction motors by using a single low cost
TMS320F240 DSP controller with the SVPWM V/Hz control algorithm. The
TMS320F40 has a 20 MIPs 16-bit fixed point DSP core with 12 PWM channels. The
six PWM channels control the first inverter whereas the only three more PWM channels
utilizing external MOSFET IR2104 IC driver with programmable deadband is used to
control the second inverter. The total execution time for independently controlling two
motors was 23.70 μs, approximately 47.40 % of DSP bandwidth utilization at 20 kHz
switching frequency. The software was written in assembly to optimize the control
performance and requires less than 4 kW program space and 0.5 kW data space.
Table 2.4 summarizes a review of the software-based MCU/DSP controller for
multi-unit motor drive system.
26
Table 2.4: Review of the software-based MCU/DSP controller
Reference
(year) Motor
Motor
Size/speed
Control algorithm
strategy/Position sensor
Inverter
topology/ Switch
Controller Applications
Zhang [45] (2011)
2 x
PMSM
motor
2 x 65
kW/1800
rpm
-/- VSI/IGBT 1 x DSP
TMS320LF2407A Electric vehicle
Mohammed
[46] (2006)
2 x
PMSM motor
2 x 0.1 kW/
3000 rpm
SVPWM FOC
Control/ Encoder VSI/IGBT
1 x DSP
TMS320F2808 -
Phan [47] (2006)
2 x
induction
motor
-/- SVPWM FOC
Control/ Encoder VSI/IGBT
1 x DSP TMS320LF2407
Electric vehicle
Shireen [48]
(2003)
2 x induction
motor
-/- SVPWM V/Hz
Control /- VSI/MOSFET
1 x DSP
TMS320F240
HVAC
system
2.5.2 Hardware-based FPGA controller
For FPGA controller platform, an electric wheelchair with two DC motors
controlled by System on a Programmable Chip (SoPC) of FPGA with one Nios II
processor has been presented in [49]. The Altera Cyclone II EP2C35 chip, which
possesses 35 embedded multipliers, and a Nios II multi-core processor that equipped
with several 32-bit CPU core, was selected to implement two fuzzy logic-based speed
controllers. The FPGA resource utilization of the proposed motion control algorithm
was approximately 23.3% of total resources, while the memory consumed about 15.6%
of total resources. The power rating of two DC motors is 240 W whereas the motors
have 24 VDC, 16Am 3000 rpm and equipped with 1024 PPR rotary optical encoders.
Castro et al. presented the use of a FPGA-based controller for controlling of two
three-phase induction motors (2x2.2 kW, 26 V, 63 A, 1410 rpm) simultaneously with
the FOC scheme and the SVPWM technique for electric vehicle applications [11],[13].
The main Intellectual Property (IP) cores of two motor controllers are designed
independently and coded in Verilog, one for the left motor and the other for the right
motor. The Xilinx Spartan 3 XC3S1000 FPGA chip was implemented for two motor
control algorithms for controlling of two electric motors installed in the electric vehicle
prototype. The data-bit calculation in all modules was designed with 13-bit
fixed-pointed resolution. A multiplier sharing strategy was proposed to solve the
limitation of embedded multipliers that are available in low-cost FPGAs.
A motion control system for a X-Y table with two PMSM motors has been
presented in [12]. The proposed motion control system has two modules. One module
was designed and implemented in software using a Nios II embedded processor for the
motion trajectory and two position/speed controllers for the X-Y table. The other
module was designed and implemented in hardware using a FPGA for two current
vector controllers of PMSM drives. In this study, the design of two motor controller IP
cores are coded in two modules independently, which leads to a large amount of
occupied resources.
In [14], the concept of a single chip resource-shared current vector controller for
a set of AC machines based on system-level pipelined operation has been presented.
The whole control algorithm was entirely executed for each motor in succession one by
one. The centralized control scheme using resource sharing has been implemented in a
27
modular architecture for four AC machines. Table 2.5 summarizes a review of the
hardware-based FPGA controller for multi-unit motor drive system.
Table 2.5: Review of the hardware-based FPGA controller
Reference
(Year) Motor
Motor
Size/speed
Control algorithm
strategy/Position sensor
Inverter
topology/ Switch
Controller Applications
Kung [49] (2011)
2 x DC motor
2 x 0.24
kW/ 3000
rpm
-/ Optical encoder H-bridge inverter
1x FPGA Altera
CycloneII with
Nios II Processor
Electric wheelchair
Castro
[11],[13] (2009)
2 x
induction motor
2 x 2.2 kW/
1410 rpm
SVPWM FOC Control
/Encoder VSI/MOSFET
1 x FPGA Xilinx
Spartan 3 XC3S1000
Electric
vehicle
Kung [12] (2009)
2 x
PMSM
motor
2 x 200 W/ 3000 rpm
SVPWM FOC Control /Encoder
VSI/IGBT 1x FPGA Altera
Stratix II X-Y table
Tazi [14]
(1999)
4 x
induction
motor
-
SVPWM Current
Control
/Encoder
VSI 1 x FPGA Xilinx
4010E -
2.5.3 Multi-unit software/hardware-based controller
For multi-unit software/hardware-based controller platform, a new
synchronizing two PMSM motors drive system based on a dual core architecture of
DSP and Complex Programmable Logic Device (CPLD) controllers was presented in
[50]. The control unit consists of a DSP floating point TMS320F28335 operating at
150 MHz and a Altera CPLD EPM7128STC100 platform, which mainly used for
system protection. The communication between DSP and CPLD was interfaced by
Serial Peripheral Interface (SPI) protocol. Two 2.2 kW, 4 poles PMSM motors with
3000 rpm using parallel synchronous control method with compensation were tested in
the laboratory
Zhai et al. presented a four in-wheel motor independent drive vehicle with
electronic differential speed controller by using four TI DSPTMS320LF2812 controllers
[51]. The control strategy of speed and torque based on neural network PID electronic
differential is proposed in order to distribute torque to four in-wheel motors with 2 kW,
20 Nm, 1000 rpm.
In [52], an anti-lock braking system for four-wheel drive of electric vehicle has
been presented. The four-unit 700 W in-wheel BLDC motors were controlled with the
multi-unit controller of one Microchip PIC18F6621, two units of CPLD Altera
EPM7064SLC44-10 and four units of CPLD Altera EPM7128STC100.
Zhao et al. presented an implementation of four-unit FPGAs for independent
four PMSM motors drive system using Controller Area Network (CAN) bus
communication interface [53]. A 12-phase, 11 kW, 1500 rpm PMSM motor was studied
and considered as four units of parallel of 3-phase star connected stator windings. The
four units of Xilinx XC3S400 FPGAs are integrated all control algorithms including
SVPWM, PID controller, coordinate transform, current loop, speed loop. The control
algorithms were packaged as IP cores and written in Verilog HDL. In order to control
all drive units with the same torque current, CAN bus is used to construct the four-units
parallel drive system. One of the motor was selected as a master unit whereas the other
three motors were set as slave units. The CAN controller of MCP2515 was used to
manage the whole communication. The device resource utilization of each FPGA
28
controller shown that the control algorithm required 62% of 18x18 multipliers (10 of
16), 41% of slice flip flops (3008 of 7168), 97% of slices (3482 of 3584).
Al-Ayasrah et al. presented a multi-task and multi-motor control system using an
external Xilinx Virtex-E and a XC4003E FPGA buffering interfaced with a
mixed-signal ADSP-21992 DSP controller [54]. The two-wheel mobile robot with two
cross coupled independently brushless DC motors are used as an example. Due to the
limitation of the ADSP 21992 board containing only a single PWM generation unit,
only a single three-phase motor can be controlled. Thus, a dedicated FPGA buffering
circuit is used for switching between both motors by interfacing with the DSP PWM
generation unit. Table 2.6 summarizes a review of the multi-unit
software/hardware-based controller for multi-unit motor drive system.
Table 2.6: Review of the multi-unit software/hardware-based controller
Reference
(year) Motor
Motor
Size/speed
Control algorithm strategy/Position
sensor
Inverter topology/
Switch
Controller Applications
Yifei [50] (2011)
2 x
PMSM
motor
2 x 2.2kW/ 3000 rpm
SPWM FOC Control VSI/IGBT
1 x DSP
TMS320F28335
1 x CPLD EPM7128
-
Zhai [51]
(2011)
4 x PMSM
motor
4 x 2kW/
1000 rpm Direct torque Control -/-
4 x DSP
TMS320LF2812
Electric
vehicle
Yong [52]
(2009)
4 x BLDC
motor
4 x 0.7kW/
800 rpm Close loop control -/-
1 x PIC18F6621
2 x EPM7128 4 x EPM7064
Electric
vehicle
Zhao [53]
(2008)
4 x PMSM
motor
4 x 11 kW/- SVPWM FOC
Control/ Resolver VSI/IGBT
4 x FPGA Xilinx
XC3S400
Electric
vehicle
Al-Ayasrah
[54]
(2005)
2 x BLDC
motor -/-
Six step
commutation/hall
sensor
VSI/-
1 x ADSP-21992
DSP
1 x Xilinx Virtex-E
FPGA
-
According to the literature, it can be concluded that the use of a single chip
MCU/DSP controller has some practical limitations when operating with more than two
motor drive systems. These major issues include the interrupt service routine overhead
and the worst case reaction time for fault-detection and fault-handling. In addition, the
fixed internal hardware architecture limits the number of the dedicated PWM peripheral
modules and I/O pin interface, and also leads to fully serialization of the operation in
sequential processing, which influences on the control quality and control bandwidth of
motor drive systems. Thus, for multi-motor control system the traditional DSP-based
solution is to employ the controller distribution approach with multiple units of DSPs.
The multi-unit controller structure can be arranged as either one controller-unit per
motor or one controller-unit per two motors. However, the use of multi-unit controller
solution, such a multi-unit MCUs, multi-unit DSPs, and hybrid DSPs/FPGAs boards,
does not only increase the system cost and installation space but also incurs in
additional cost of hardware and software interconnections. For FPGA controller
platform, considering a system with a large number of motor units, a massive amount of
FPGA resources and embedded multipliers are required for hardware realization, which
often exceeds the capacity of available resources of a FPGA device. Therefore, this
thesis presents a fully integrated single chip FPGA solution for controlling of a
multi-unit PMSM motor drive system. The concept of an area-efficient design method
based on system-level time-division multiplexing scheme is proposed in order to
minimize resource requirements for control algorithms, which often exceed the resource
29
availability of a single chip FPGA. Thus, the proposed solution with system-level
time-division multiplexing can simplify the entire system into a single hardware
module, which can either independently or synchronously operate a group of multiple
motors with large number of units while maintaining the aspect of system integration
and cost effectiveness.
2.6 FPGA and design flow overview
This subsection introduces the features of Xilinx Spartan-3E FPGA family. A
comparison of features, including system gates, slices, logic cells. CLB flip-flops,
multipliers, among different Xilinx Spartan-3E FPGA platform is also provided. The
design flow of FPGA-based DSP algorithm using the Xilinx System Generator (XSG)
tool is also discussed.
2.6.1 Features of Xilinx Spartan-3E FPGA family
The Spartan-3E FPGA family offers a low-cost platform solution featuring with
advanced 90 nm process technology. The state-of-the-art of cost efficient Spartan-3E
device delivers up to 1.6 million system gates, up to 376 I/Os, which enables efficiently
the integration of various functional modules into a single FPGA. The features of
Spartan-3E, which considered as the lowest cost per logic of any FPGA families in the
industry, are optimized and well suited for cost-efficient applications. Table 2.7 shows
the features of the Spartan-3E FPGA families [55].
Table 2.7: Features of the Spartan-3E FPGA family [55]
Spartan-3E FPGA family
Features XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
Logic Resources
System Gates 100K 250K 500K 1200K 1600K
Slices 960 2448 4656 8672 14752
Logic cells 2160 5508 10476 19512 33192
CLB Flip-Flops 1920 4896 9312 17344 29504
Memory Resources
Distributed RAM 15 38 73 136 231
Block RAM
Block
4 12 73 136 231
Total Block
RAM
72 216 360 504 648
I/O Resources
Single ended I/O 108 172 190 304 376
Differential I/O 40 68 77 124 156
Embedded Hard IP Resources
DSP48A Slices - - - - -
Multipliers 4 12 20 28 36
2.6.2 Xilinx System Generator (XSG) design flow
The Xilinx system generator (XSG) is a high-level graphical blocksets design
tool for implementing high performance DSP systems in FPGA devices with the
30
model-based MATLAB Simulink environment. The XSG offers accelerated simulation
through hardware co-simulation during the design stage for model algorithm
verification, and can automatically convert into the HDL code for real-time
implementing with FPGAs. For the development of motor control system, initially the
control algorithm is designed and simulated based on the mathematical model at the
system level in continuous time domain with MALTAB Simulink environment. For
FPGA hardware design, the XSG blocksets are replaced and verified in the simulation
model for HDL code generation. The Xilinx ISE Design Suite 12.4 development
software is used to automatically synthesize, place and route, and generate the generated
HDL code into a bit stream file. The final bit stream file is then configured and
downloaded to the FPGA board for real-time hardware implementation and testing.
Figure 2.12 shows the XSG design flow for motor control system.
XSG Design Flow
2. Develop algorithm and system model in continuous-time
domain
5. Automatic HDL code generation
3. Develop algorithm and system model using XSG
blocksets in discrete-time domain
8. Configure and Download to FPGA hardware
1. Design requirement and system specification
6. RTL Synthesis
7. Place and Route process
RTL HDL code
Bit stream file (.bit)
Synthesis
HDL design
Design Stage DSP development
Physical design
Implementation
Tools
9. Hardware-in-the-Loop testing and Experimental
validation
Testing and
Verification
Netlist file
JTAG USB port
Simulink MDL
4. Simulate and Verify system model function in Simulink
System design
Figure 2.12: XSG design flow for motor control system
31
CHAPTER 3
METHODOLOGY
3.1 Proposed method of system-level time-division multiplexing
This section presents the concept of system-level time-division multiplexing
applicable for multi-motor control systems proposed in this thesis work. A review of
design strategies for multi-motor control system is discussed. The detailed description
of the system-level time-division multiplexing scheme is introduced. The concept of
delay balancing technique is also described in details.
3.1.1 Review of design strategies for multi-motor control system
For multi-motor control systems, the demand of numerous resources and
embedded multipliers for control algorithms limits the number of controlled machines
within a single chip FPGA. This is especially true since the complexity of a
SVPWM-based vector control scheme requires several arithmetic operations, including
multipliers, divider, square root, and trigonometric functions (sin, cos, arctan). These
arithmetic operations increase dramatically and inevitably exceed available resources
when the system contains a large number of motor units. According to the literature,
several resource sharing strategies were proposed to overcome these resource
limitations, including multiplier sharing strategy [11],[13], Finite-State Machine (FSM)
method [7],[8], factorization method [6],[9], system-level pipelining operation [14].
From the control point of view, the time interval of inverter switching period is the
maximum boundary for total computation time of the system. Often, the computation
time required for one motor is much lower than such a switching period. This condition
implies that several control algorithms can be allocated by serialized treatment in a
sequential manner. The system-level pipelining approach exploits the advantage of fast
computation time by running several control algorithms sequentially on the same
hardware structure. Nevertheless, this approach is suitable for only the multi-motor
system containing the same machine size and the same motor specification.
This thesis presents a system-level time-division multiplexing approach as
shown in Figure 3.1. In this scheme, several time slots are managed into frames and
each frame consists of a group of time slots dedicated to each input channel. The
number of frames is usually fixed and equivalent to the maximum cycle latency
required for the complete operation of control algorithms. As a result, for a given value
of inverter switching frequency, the maximum number of motor units (the number of
slots for each frame) is directly dependent on the sampling rate of time-division
multiplexing (a time interval for each slot). The higher such a sampling rate reduces the
time interval for each frame and hence decreases significantly the total computation
time allowing the possibility to increase the number of motor units. The lower such a
sampling rate raises the time interval for each frame and hence tremendously increases
the total computation time, which can reach to the boundary of the inverter switching
period. By comparing with the system-level pipelining approach whereas the data
transmission among different motors can be achieved only after finishing the whole
execution of each control algorithm, the proposed method can enhance the control
performance for the optimal operation among several motors by allowing processing
data of each motor to transfer to others during the algorithm execution at the clock
32
speed. In addition, since the system executes several tasks of computation blocks in a
series of cycles on the same hardware structure, the total computational time of the
system is much lower than the switching period of the inverter. This implies that the
time-division multiplexing method allows the system to extend the operation at the
higher maximum inverter switching frequency comparing with the system-level
pipelining approach, which is applicable for high speed motor control applications. The
proposed approach also enables the system to operate a group of controlled motors with
different machine sizes by customizing the data bit-length according to the largest
controlled machine (i.e., a worst case condition). In general, most industrial control
applications often utilize the same control scheme for all motors in the system (e.g.,
either direct torque control or vector control schemes), such as robotics and
automobiles. For the system with different control complexity, the proposed method
allows a single hardware structure to share some common functional-equivalent
modules at the circuit-level by operating with appropriate timing organization.
Time
Tsw=TPWM
Motor
1Motor
2Motor
3Motor
4Motor
1Motor
2Motor
3Motor
4
Motor 1 - 4
Motor
1Motor
2
Frames Slots
Ttotal
Ttotal
(TCLK = 2x10-8
s)
(a)
(b)
Time
Motor 1 - 4 Motor 1 - 4
Figure 3.1: Comparison of the system timing diagram: (a) System-level pipelining
method; (b) System-level time-division multiplexing method
3.1.2 Description of the system-level time-division multiplexing scheme
A block diagram of an overview of the control system hardware implementation
with system-level time-division multiplexing is shown in Figure 3.2. The analog
multiplexer is employed in order to reduce the number of FPGA interface pins and the
required ADCs. The multiple input signals are multiplexed in analog domain at a fixed
sampling frequency. In this thesis, the motor currents are multiplexed at a sampling
period of 1x10-5
s (100 kHz). The selected sampling frequency is much higher than the
maximum frequency of the motor current (200 Hz running at the rated speed of
3,000 rpm), and is an integer multiple slower than the system clock of 50 MHz to
achieve good accuracy and avoid jitter. In the digital domain, a single chip FPGA is
employed for hardware realization of the entire system, including ADC interface, DSP
system, and Digital-to-Analog Converter (DAC) interfaces. In the DSP block, the input
signal obtained from the analog multiplexer is demultiplexed into original separated
signals. For the time-division multiplexing scheme, the multiplexer unit is used to select
the input from one among multiple input channels, and transfer into a single control
algorithm with different time segments. In this thesis, the sampling rate of time-division
multiplexing is set at the maximum clock speed of 2x10-8
s (50 MHz) in order to
minimize the total computation time of control algorithms. A demultiplexing unit and a
Zero-Order Hold (ZOH) are used to separate and reconstruct post processing signals.
For debugging purposes, the DACs perform the data conversion of digital formats into
analog waveforms.
33
CH_1
CH_2
CH_3
CH_4
D/A
Ts = 2x10-8
s
Ts = 1x10-5
s
Analog domain Analog domainDigital domain
D/AD/A
D/AA/D
ZOH
ZOH
ZOH
ZOH
Dem
ux
System-level time-division multiplexing
DSPM
ux
Dem
ux
DSP
A/D
Driver
D/A
Driver
FPGAHardware implementation
4 41 1
Control
algorithm
CH_1
CH_2
CH_3
CH_4
An
alo
g M
ux
FPGA
Figure 3.2: Block diagram of an overview of the control system hardware
implementation with system-level time-division multiplexing
The internal hardware architecture with the delay latency of the SVPWM-based
vector control algorithm is shown in Figure 3.3. The operation of the proposed method
can be described as follows: (1) A count-limited counter running at the clock rate is
used to generate a common control signal to all multiplexer units. This generated
control signal is counted in the increasing order from zero to three, corresponding to the
selection for one of these four controlled motors. (2) All multiplexer units are executed
simultaneously at the same time for transferring control parameters of the same motor
into a single hardware module. (3) The execution of the vector control algorithm is
operated continuously at the sampling rate of the clock speed, with different time
segments beginning from the first motor to the fourth motor. (4) The steps (1) to (3) are
repeated sequentially for all computational operations starting from the abc-dq
transformation module, speed and current controller modules, the dq-αβ transformation
module, and the SVPWM generator module. For timing synchronization, the delay
balancing technique must be employed in order to avoid the numerical and functional
violation of the control algorithm. (5) After finishing the execution of entire control
algorithm, the control module generates three sets of output PWMs. (6) Demultiplexing
modules separate each of these generated output PWMs into four separate channels for
controlling four sets of controlled machines. It can be noted that the concept proposed in
this thesis is similar to the concept of microprocessor system with cycle-interleaved
thread scheduling and pipeline support in which one thread is in charge of one PMSM
motor control. The system is designed to support a fixed number of PMSM motors. In
each cycle, the system will switch to handle the next PMSM motor with zero latency
switching overhead. However, comparing with microprocessor system with thread
scheduling, the proposed system in this thesis is simpler as there is no control flow
complexity and no interrupt support.
34
ia
ib
θe
ωm
ωref
iα
iβ
dq-αβ transformation
CORDIC
SinCos
sinθe
cosθe
Park-1
(dq-αβ)
z-1
z-1
z-16
z-16
z-3
z-3
SVPWM
generator
PWM_A
PWM_B
PWM_C
vα*
vβ*
SVPWM
z-32
Iα
Iβ
abc-dq transformation
CORDIC
SinCos
sinθe
cosθe
Clark
(abc-αβ)Park
(αβ-dq)
z-1
z-1
z-15
z-15
z-3
z-3 id
*
θe
ia
ib
MU
XM
UX
MU
XM
UX
MU
X
iq*
vd*
vq*
ωm
PI current
regulatorz
-4+-0
k1z
-4
z-20
PI speed
regulator k2PI current
regulator
z-4z
-4
k3
k4
z-4
z-20
ωref
controllerSpeed & current
CNT
DE
MU
XD
EM
UX
DE
MU
X
z-15
z-1
z-1
z-4
+-
z-4
z-4
z-4
z-4
z-20
z-96
z-4
z-4
z-4
z-12
z-20
z-1
z-15
z-4
z-4
z-4
Legend
Inserted delay
with N latency
z-d
z-N
Delay with d latency
introduced by
computational blocks
+-
++
+-
++
Figure 3.3: Internal hardware architecture with the delay latency of the
vector control algorithm
3.1.3 Delay balancing technique
Since the time-division multiplexing executes in sequential manner with
different time segments at clock cycles, additional delay latency introduced by
computational blocks on only certain paths can seriously cause the variation of
functional behaviors. In order to prevent the unmatched timing across all cut-sets, delay
blocks (tapped delays or unit delays) must be properly inserted into the circuit design.
The number of inserted delay length (N) for each path depends on the summation of
delay latency introduced by each computational block from previous stages. For the
determination of the number of N, the two following conditions must be satisfied. For
the first condition, all parallel paths across the cut-set must have the same number of
cycle latency in order to avoid the timing mismatch. Thus, the balancing delay must be
inserted into the path containing lower number of cycle latency. This can be determined
by the difference of cycle latency between parallel paths across the cut-set. For the
second condition, the summation of delay latencies of parallel paths across the cut-set
must be the lowest integer multiple of the number of motor units in order to minimize
the computation time and to ensure the correctness of the algorithm calculation by
beginning the operation with the same motor unit.
For mathematical analysis, let us denote that dH and dL are the total delay latency
from previous stages of the higher latency path and the lower latency path, respectively.
Thus, for balancing the delay in higher latency paths, the number of inserted delay
latency (N) can be determined as:
dHN n dHn
(3.1)
35
For balancing the delays in lower latency paths, the number of inserted delay
latency (N) can be determined as:
dHN = d - d n dH L Hn
(3.2)
where n is the number of controlled motors and is the ceiling function operator.
Thus, according to Figure 3.3 the abc-dq transformation module containing a
Coordinate Rotation Digital Computer (CORDIC) sin/cos block, which requires
15 cycle latencies for the complete operation. Thus, the path containing the CORDIC
sin/cos block must be explicitly inserted with a balancing delay of N = 1, whereas the
parallel path along this computation block, which previously contains 1 cycle latency
introduced by other computational blocks, must be inserted with a balancing delay of
N = 15. Figure 3.4 shows an example of the design with and without the balancing
delay. In this scheme, since the current and speed PI regulators require a unit-delay
feedback loop for the integrator operation, which limits the operation of time-division
multiplexing, in this thesis the feedback loop is modified by multiplying the feedback
unit-delay and the integral PI gain with the number of motor units. Moreover, all
balancing delays are manually selected and inserted into the entire design for ensuring
the functional integrity with the minimum of the total computation time. Considering
the proposed method with the delay balancing procedure, the entire control module can
be fully integrated and configured into a low-cost FPGA with minimum resource usage.
AddSub
+
-
+
+
Combitional logic
z-4
Balancing Delay
z-4
þ
(a)
AddSub
+
-
+
+
Combitional logic
z-4
þ
(b)
Figure 3.4: Example of the design: (a) With the balancing delay; (b) Without the
balancing delay
36
3.2 FPGA-based controller design using XSG
This subsection discusses the design of FPGA-based controller using the XSG
tool. The circuit design based on mathematical models of the FPGA-based DSP of the
SVPWM-based vector control algorithm, including position and speed calculation
module, speed and current PI regulators module, three-phase SVPWM generator
module, rotating coordinate transformation module, and time multiplexing and
demultiplexing module, is presented in details.
3.2.1 Position and speed calculation module
In this thesis, the speed calculation algorithm for high accuracy and wide speed
range is presented. With the aid of Figure 3.5, the operation of the proposed hardware
circuit can be described as follows. For the electrical position measurement, the encoder
digital pulse is filtered and counted with the edge detector circuit. Instead of using a unit
delay for the edge detection, a tapped delay is utilized in this thesis in order to filter the
encoder digital noise that has the time period shorter than the length of the tapped delay.
A clock-pulse counting counter (CNT1) running at the clock rate is used to generate a
pulse train within a time period of the tapped delay. The output pulse train is compared
with a constant producing a Boolean-type reset signal to the counterʼs input. At the
same time, the output pulse train is fed to a single up/down counter (CNT2) for
generating a sawtooth waveform. Since the CNT2 executes at the speed of clock
frequency, a reset signal is used to reduce the update time of the output signal by a
factor of constant value in order to decrease the size of bit-length of the CNT2. A
constant gain is used to scale down the amplitude range into an appropriate value of the
electrical position. For the speed measurement, the operation of a free-running counter
(CNT4) is controlled by an enable signal obtained from the CNT1. An update time
interval counter (CNT3) is used to assign the value of the update period by generating a
reset signal sent to the CNT4. In every update period, the CNT4 performs a counting up
operation for the speed calculation until the reset signal is trigged. A two-input
multiplexer connecting with a feedback unit delay is used to restore the speed
calculation value at every update period. Finally, the speed calculation is obtained by
multiplying with a constant gain for scaling into the actual speed.
By comparing with a classical pulse counting method (M method) whereas the
update time of a pulse-counting counter is very long at low speed operation since the
encoder pulses are not frequently generated and detected in some sampling periods. For
the proposed method, the system does not only count the number of encoder pulse (edge
detector circuit) but also counts the number of clock pulse (CNT1) in fixed counting
period (equivalent to period counting method) so that it combines the advantages of the
pulse counting and period counting methods. Thus, the proposed simple hardware
circuit, containing only standard counters and basic logic elements, is able to achieve
high accuracy in wide speed range with less consumption of hardware resources.
37
1z
-nNOT
AND1
ENC_Arst
enCNT1
rst
enCNT2 K1
c1a>=b
c2
rst CNT3
1
0
sel
K2
z-1
rst
enCNT4
1
2
a>=b
a>=b
Position and Speed Calculation Module
Filtering & Edge Detector Circuit
Update Time Interval Circuit
Free Running
Counter
Mechanical Speed Calculation Circuit
Up/Down
Counter
Electrical Position Calculation Circuit
A
Incremental
Encoder
Electrical
Position (θe)
Mechanical
Speed (ωm)
Clock Pulse Counting Circuit
Figure 3.5: Block diagram of the proposed hardware circuit of position and speed
calculation module
3.2.2 Speed and current PI regulators module
The speed and two current PI regulators used in the control loop are designed
based on a parallel form. By using the backward Euler integration method for the
integral term, the corresponding discrete-time controller transfer function in z-domain is
given as follows:
1 )(
z
zTKKzU sIP (3.3)
Taking the inverse z-transform, the expression of difference equation of the PI regulator
in a parallel form for implementation in a digital controller can be derived as [9]:
] 1 [ ) ] 1 [ ] [ ( ] [ ] [ kukekeTKkeKku IsIP (3.4)
where KP and KI are the proportional gain and the integral gain, respectively, Ts is the
sampling time. The control variables are denoted with the control signal (u), error signal
(e), and the output of the integral part (uI). Figure 3.6 shows block diagram of the digital
PI controller.
KI
KP
∑+-
zTs___z-1
∑+
+er
y
u∑
Digital PI controller
uP
uI
∑
+z
-1+
Ts
Figure 3.6: Block diagram of the digital PI controller
38
3.2.3 Three-phase SVPWM generator module
The hardware circuit design of three-phase SVPWM generator module is
developed based on the mathematical equations of (2.46) to (2.58). In contrast to the
lookup table-based hardware design for computing sin/cos functions [11],[12],[13], this
thesis utilizes the sin/cos function based on CORDIC algorithm provided by the XSG
library. This module does not only provide minimal hardware utilization by using
simple add/sub and shift operations, but also allows the algorithm to execute at high
speed rates and high resolution. Figure 3.7 shows block diagram of the three-phase
SVPWM generator module.
VDC
vα
vβ
PWM_A
PWM_B
PWM_C
SVPWM Generator Module
Triangular
Generator
PWM
Generator
Time Phase
Calculation
(TA,TB,TC)
Time Sequence
Calculation
(T0,T1,T2)
n
TA
TB
TC
TTri
T0
T1
Switching
Time
Amplitude
Calculation (a)
Vector Sector
Calculation (n)
vref
α
Vector
Amplitude
(vref) and
Angle (α)
Calculation
a
T2
1
n
a
ba b
Relational9
a
ba > b
Relational8
a
ba b
Relational7
a
ba > b
Relational6
a
ba b
Relational5
a
ba > b
Relational4
a
ba b
Relational3
a
ba > b
Relational2
a
ba b
Relational11
a
ba > b
Relational10
a
ba b
Relational1
a
ba > b
Relational
and
Logical5
and
Logical4
and
Logical3
and
Logical2
and
Logical1
and
Logical
cast
Convert6
cast
Convert5
cast
Convert4
cast
Convert3
cast
Convert2
cast
Convert1
cast
Convert
-60
Constant9
-120
Constant8
0
Constant7
-120
Constant6
-180
Constant5
180
Constant4
120
Constant3
120
Constant2
60
Constant13
0
Constant11
-60
Constant10
60
Constant1
z-1
x 6
CMult6
z-1
x 5
CMult5
z-1
x 4
CMult4
z-1
x 3
CMult3
z-1
x 2
CMult2
z-1
x 1
CMult1
a
ba + b
AddSub5
a
ba + b
AddSub4
a
ba + b
AddSub3
a
ba + b
AddSub2
a
ba + b
AddSub1
1
alpha
3
Tc
2
Tb
1
Ta
seld0d1d2d3d4d5d6d7
Mux3
seld0d1d2d3d4d5d6d7
Mux2
seld0d1d2d3d4d5d6d7
Mux1
0
Constant1
a
ba + b
AddSub5
a
ba + b
AddSub2a
ba + b
AddSub1
4
n
3
T2
2
T1
1
T0
Figure 3.7: Block diagram of the three-phase SVPWM generator module
3.2.4 Rotating coordinate transformation module
The classical direct and quadrature (d-q) theory is widely used to model and
analyze AC electrical machines characteristic since both steady-state and dynamic
behaviors can be calculated and examined with simplified expressions. With
mathematical transformation, three-phase stationary quantities can be simply converted
into the two rotating d-q axes components. The direct rotating transformation (Clarkʼs
and Parkʼs transformation) from the three-phase variables in the stationary a-b-c
reference frame into the synchronous rotating d-q reference frame is given as:
39
0
2 2cos cos( ) cos( )
3 3
2 2 2sin sin( ) sin( )
3 3 3
1 1 1
2 2 2
q a
d b
c
π πθ θ θ
f fπ π
f θ θ θ f
f f
(3.5)
The inverse direct rotating transformation can be derived as:
0
cos sin 1
2 2 2cos( ) sin( ) 1
3 3 3
2 2cos( ) sin( ) 1
3 3
a q
b d
c
θ θf f
π πf θ θ f
f fπ π
θ θ
(3.6)
where the term of variable f can represent with voltages, currents, or the flux linkages.
From (3.5) and (3.6), it can be seen that the direct and inverse direct rotating
transformations can be easily implemented based on the mathematical equations with
adder and multiplier blocks together with the CORDIC algorithm module.
3.2.5 Time multiplexing and demultiplexing module
For time-division multiplexing scheme, the multiplexer unit is used to
manipulate the time slot of several identical algorithms. In this thesis, the digital
multiplexer, which is controlled by a count-limited counter for system timing, is
employed to switch between different input channels. For a four-unit motor system, two
input signals of motor currents (ia and ib) acquired from the external ADC are
reconstructed to the original separated signals by a cascade of tapped delays and
down-samplers. It should be noted that the number of tapped delay length and down
sampling rate depends on the relationship between the analog multiplexer sampling time
and the number of motor units. For example, since the analog multiplexer sampling
frequency is equal to 100 kHz, thus the delay length (n) of tapped delays must be
selected with n = 500 for the 50 MHz clock speed. As a consequence, the down
sampling rate (m) must be equal to 2,000 for the four-unit motor system as shown in
Figure 3.8. The two signal conditioning circuits are used to eliminate the DC offset and
scale to appropriate signal amplitudes. At the same time, the rotor position and the
measured speed are obtained from the position and speed calculation module. For
time-division multiplexing operation, these motor input signals are connected directly to
the time multiplexing module, which consists of a set of multiplexer units and a
count-limited counter. The entire algorithm of SVPWM-based vector control is fully
implemented on a single hardware module and executed at the maximum clock speed of
2x10-8
s. Conversely, the demultiplexing module, which consists of delay blocks,
down-samplers, and up-samplers, is used to select one of output PWMs for each time
segment of 2x10-8
s, and separate into four output PWM channels for controlling four
sets of controlled motors.
For mathematical analysis of the demultiplexing module for motor currents, let
us denote that fs,analog is the analog multiplexer sampling frequency, MCLK is the main
system clock of FPGA, N is the number of motor units in the system, n is the delay
40
length of tapped delays, and m is the down sampling rate. Thus, the delay length of
tapped delays (n) can be simply determined as:
, log
s ana
MCLKn
f (3.7)
Thus, the down sampling rate (m) can be calculated as:
m N n (3.8)
In this thesis, since the number of motor units is equal to 4, the value of delay length (n)
of tapped delays must be equal to 500. Thus, the demultiplexing module for four
separate channels of motor currents should be inserted with the delay length of 1500,
1000, 500, and 0, respectively. As a consequent, the down sampling rate must be set to
2000 for these four separate channels.
Similarly, for mathematical analysis of the time multiplexing module, the
maximum counting value (CNTmax) of the up-counter for controlling the digital
multiplexer (i.e., the up-counter counts from 0, 1, 2, ..., CNTmax), which execute at the
FPGA clock frequency of 2x10-8
s can be determined as follows:
max 1CNT N (3.9)
where N is the number of motor units in the system. For mathematical analysis of the
time demultiplexing module, since the operation of time-division multiplexing is set at
the maximum clock speed of 2x10-8
s (50 MHz) in order to minimize the total
computation time of control algorithms, the down-samplers and the up-samplers of time
demultiplexing unit can be simply set to equal the number of motor units (N) in the
system. Figure 3.9 and Figure 3.10 show the time diagram of the demultiplexing module
for motor currents and the execution diagram of the time multiplexing and
demultiplexing modules, respectively.
DemuxSignal
Conditioning
DemuxSignal
Conditioning
4
4
1
1
4
4
Counter
1
1
z-3n ↓4n
↓4n
↓4n
↓4n
Mu
xM
ux
Time Multiplexing Module
1
1
Demux4
Demux4
z-3 ↓4
↓4
↓4
↓4
z-2
z-1
↑4
↑4
↑4
↑4
1Demux
4PWM_A (1-4)
Time Demultiplexing Module
4
4
1
1
Mu
xM
ux
4 1
Mu
x
θe
Xilinx XC3S1600E FPGA
ωm
ωref
ia
ib
SVPWM
based
Vector Control
Algorithm
PWM_A
PWM_B
PWM_C
(n = 500)
z-2n
z-n
PWM_B (1-4)
PWM_C (1-4)
Figure 3.8: Block diagram of the time multiplexing and demultiplexing modules
41
ia
Ts = 10 μs ( fs,analog =100 kHz)
ia,1
ia,2
ia,3
ia,4
PMSM1
PMSM2
PMSM3
PMSM4
PMSM1
PMSM2
PMSM3
PMSM4
Ts = 40 μs
Figure 3.9: Timing diagram of the demultiplexing module for motor currents
ia
ib
θe
ωm
ωref
dq-αβ
transformation
PWM_A
PWM_B
PWM_C
SVPWM
abc-dq
transformationM
UX
MU
XM
UX
MU
XM
UX
CNT
DE
MU
XD
EM
UX
DE
MU
X
SVPWM-baesd vector control algorithm
Speed and
current
controllers
with decoupling
feed-forward
compensator
Motor 1 to 4 TCLK = 2x10-8
s
TCLK = 2x10-8
s
TCLK = 2x10-8
s
Figure 3.10: Simplified execution diagram of the time multiplexing and
demultiplexing modules
42
3.3 Application of a single chip FPGA multi-motor control system
This subsection presents an example application of a single chip FPGA
multi-motor control system for a steel rolling mill process. The description of
cross-coupling multi-motor control system in this thesis work is discussed in details.
The concept of cross-coupling control for speed synchronization aiming to minimize the
speed synchronization error among several multiple motors in the system is also
provided.
3.3.1 Description of cross-coupling multi-motor control system
There are several applications and industries that demand the motor drive system
to smoothly synchronize a group of two or multiple motors simultaneously during the
production process, including press machine, offset printing, manufacturing assembly,
and steel rolling mill. The poor speed synchronization of multi-motor systems may
cause varying catastrophic effects from the dimensional accuracy to unstable process
and production reliability. In steel industry, the rolling mill process is the operation
which metal strip is successively passed through a number of rolling pairs in order to
reduce the steel thickness uniformly. In general, the line production consists of several
process stages and rolling stands. Figure 3.11 shows a typical rolling mill with two
stands as an example, where two electric motors mechanically coupled to the
backup-roll through the pinion gearbox. The backup-rolls with larger diameter size are
mounted at above and below connecting to two parallel work-rolls. These work-rolls
squeeze from side to side the metal strip flowing between the rolls to produce the
desired thickness and dimension. In order to achieve the uniform metal stripe without
irregular deformation and to prevent the catastrophic tension on the mechanical parts, it
is essential to smoothly synchronize a group of multiple motors at the same speed
[56],[57].
Strip
Work-roll
Backup-roll
Tension meter
Stand 1 Stand 2
AC
Motor
AC
Motor
Pinion
Figure 3.11: Arrangement of two rolling stands and motor drive systems
43
For optimal and harmonious operation of multi-motor control system, it is
necessary to share feedback information from one drive to other drives. In this thesis, a
cross-coupling control for speed synchronization is presented aiming to minimize the
speed synchronization error caused by motor torque variation during the production
process. From the view point of controller implementation, the use of multi-controller
structure degrades system integration and requires data communication among chips.
The purpose of this thesis is to present a fully integrated single chip solution for a
cross-coupling multi-motor control system applicable for steel rolling mills. The
cross-coupling multi-motor speed controller with time-division multiplexing scheme has
been fully realized on a single chip FPGA, which offers the possibility to transmit
processing data among controller modules within the same device. The entire system is
developed on a four-unit PMSM drive system with SVPWM-based vector control
scheme. Figure 3.12 shows the structure of a single-chip FPGA-based controller for four
rolling mill drives.
FPGA
controller
Three-phase IGBT-based
voltage source inverter
Position and current feedback signalsDig
ital
I/O
pin
s
Stand1 Stand2 Stand3 Stand4
Figure 3.12: Structure of a single chip FPGA-based controller for four rolling mill
drives
3.3.2 Cross-coupling control for speed synchronization
Over the past decade, several studies on multi-motor speed synchronization
techniques have been presented [58],[59],[60],[61]. The cross-coupling technique
coordinates feedback information of the relative speed errors among control loops of
different motor axes in order to reduce the speed synchronization error. This control
technique provides a good degree of synchronization and disturbance rejection with a
simple control structure. In this thesis, the synchronization control strategy is based on
the concept of relative-coupling control introduced in [62], with modifications in term
of control architecture and implementation. The major differences between our
44
cross-coupling control system and the relative-coupling method are as follows: (1) The
architecture has been extended from three to four-motor control system; (2) The
controller unit has been reduced to only a single controller; (3) The PMSM motors have
been implemented instead of the servo motors; (4) The control algorithm has been
implemented with more complexity of the SVPWM-based vector control with
time-division multiplexing scheme. The proposed multi-motor control system is
implemented with the relative-coupling method for a four-unit PMSM motor drive
system, as shown in Fig. 3.13, and is referred to as “cross-coupling control” whereas an
independent control multi-motor system is referred to as “conventional control”
throughout this thesis. The main idea of relative coupling control is to subtract the
feedback speed of each motor from other remaining motors, and the sum of speed
difference is used as a compensation signal to the speed control loop. In this way, the
speed variation on one motor caused by load disturbances can be compensated
simultaneously. The speed response of all motors in the system can be equally
maintained during the transient operation. The internal structure of a SVPWM-based
vector control scheme with relative-coupling control for one drive system is shown in
Figure 3.14. The operation of the proposed control scheme can be described as follows.
For the first motor, the speed PI controller regulates the error between the actual speed
and the command speed, and produces the reference torque. In the meanwhile, the
relative speed block is used to generate an additional relative speed error signal by using
information of all motors in the system, and added as a cross-coupling term to the speed
error command signal. The constant gains are used to compensate the difference of
moment of inertia between motors. The same control structure with a relative speed
block is applied for other motor drives in the system.
In this control strategy, in order to design the relative speed feedback block, the
values of some control parameters must be determined and known, including the
moment of inertia (J), and friction (B) related to each motor, the natural frequency (ωn).
and the damping coefficient (ξ) of the overall system. It should be noted that the last
two parameters of the natural frequency and the damping coefficient are selected for
tuning the PI controller in each closed loop system and also determine the system
transient behavior under step speed commands as well as load disturbances [62].
+-
Controller∑ Motor1+-
∑
Relative
Speed1
ωm1
+-
Controller∑ Motor2+-
∑
Relative
Speed2
ωm2
+-
Controller∑ Motor3+-
∑
Relative
Speed3
ωm3
+-
Controller∑ Motor4+-
∑
Relative
Speed4
ωm4
ωm1
ωm2
ωm3
ωm4
ωm*
Figure 3.13: Block diagram of the relative-coupling control structure for a
four-unit motor drive system
45
ωm*
ωm
+-
id*= 0
θe Position
and speed
calculation
Enc_A
Enc_B
Clark
transform
ia
ib
Park
transform
iαiβ
d-axis
current
controller
q-axis
current
controller
Speed
controller
vα
vβ
ωm
id
iq
vd
vq
θe
θe
SVPWM
Te*
1_KT
iq*
Drive 1Vdc
+-∑
Relative
Speed
Block
∑
From
Drive
2 to 4
Inverse
Park
transform
PWM_A
PWM_B
PWM_C
Figure 3.14: Internal structure of the SVPWM-based vector control scheme with
relative-coupling control for one rolling mill drive
The details of relative speed block are shown in Figure 3.15. The aim of this
block is to generate an additional relative speed error signal by subtracting the measured
speed from all the motors to each analyzed reference drive. Since the motor speed from
each drive has a different reflection or relative speed impact to the drive under analysis,
the speed motor under analysis is thus considered positive whereas the speeds of other
motors are used to subtract to the analyzed drive. The relative speed feedback gain (kr12,
kr13, ..., kr1n), where n is the motor number in the system, are used to compensate the
difference of the moment of inertia between the analyzed drive and the others, and also
different between each relative speed feedback block. Thus, these relative speed
feedback gains can be simply determined by considering each motor inertia coefficient
and the analyzed motor inertia coefficient. Nevertheless, in this thesis since the motor
specification of four identical low power PMSM motors (PMSM1 to PMSM4) has the
same value of moments of inertia as shown in Appendix A, the values of the relative
speed feedback gain implementing in the relative speed block are simply set as follows:
kr12 = 1, kr13 = 1, and kr14 = 1. In this thesis, the four-unit motor system with the inherent
characteristics of each part of the overall system can be considered as a single closed
loop system according with the design procedure presented in [62]. Thus, the PI
controller parameters can be expressed as follows:
2P nK ξω J B (3.10)
2
nI
p
ω JK
K (3.11)
where Kp and KI are the proportional gain and the integral coefficient of PI controller,
which corresponds to high frequency errors and low frequency errors of the system,
respectively.
46
∑
∑∑
∑
+-
Relative Speed Block
+-
+-
kr12
kr13
kr14
ωm1
ωm2
Δωr
ωm3
ωm4
+
++
Figure 3.15: Block diagram of the relative speed block
3.4 System development and implementation
This subsection describes the system development and implementation of the
proposed four-unit PMSM motor system with time-division multiplexing scheme using a
single chip FPGA based on the SVPWM-based vector control algorithm. The simulation
model developed in MALTAB Simulink environment is presented. The development of
FPGA-based motor speed controller is discussed. The implementations of the dead time
generator circuit as well as the hardware solution using analog multiplexer are described
in details. The experimental setup in the laboratory is also presented.
3.4.1 Simulation model of SVPWM-based vector control PMSM motor drive
system
For a classical AC drive, control of high performance PMSM motor drive can be
accomplished by using either two most modern advanced control strategies, namely the
direct torque control and the vector control scheme [63]. In this thesis, vector control
method is employed due to the fact that this control scheme provides excellent
performance characteristics in term of fast speed dynamic response and accurate steady
state operation with less torque and current ripple comparing with direct torque control
strategy [63]. For the development of motor control algorithm, initially the control
algorithm is designed and simulated based on mathematical model at the system level in
continuous time domain with Simulink environment for algorithm verification.
Figure 3.16 to Figure 3.19 show simulation models of the SVPWM-based vector control
PMSM motor drive system, the SVPWM-based vector control subsystem, the PMSM
motor subsystem, the abc-dq transformation subsystem, and the dq-αβ transformation
subsystem, in MATLAB Simulink environment, respectively. Figure 3.20 to
Figure 3.25 show simulation results of the mechanical speed and electromagnetic
torque, the three-phase line-to-line voltage and stator currents, the d-q axes current, the
d-q axes command voltage, the filtered PWM, and the vector sector, respectively.
Discrete,
Ts = 2e-006 s.
powergui
Vdc
Torque
stepTorque
(N.m)
Speed
Scope3
Scope2
wref
wm
ia
ib
theta_e
S1
S2
S3
S4
S5
S6
SVPWM-based vector control
Tm iabc
Te
theta_e
ws_m
va
vb
vc
PMSM modelg CE
IGBT/Diode6
g CE
IGBT/Diode5
g CE
IGBT/Diode4
g CE
IGBT/Diode3
g CE
IGBT/Diode2
g CE
IGBT/Diode1
[s6]
Goto8
[s4]
Goto7
[s3]
Goto6
[s2]
Goto5
[wm]
Goto4
[theta_e]
Goto3
[ib]
Goto2
[s5]
Goto10
[ia]
Goto1 [s1]
Goto
[s4]
From9
[s3]
From8
[s2]
From5
[wm]
From4
[wm]
From3
[wm]
From2
[s6]
From13
[s5]
From12 [wm]
From1
[s1]
From
i+-
i+-
i+-
0
Constant
torque
Figure 3.16: Simulation model of the SVPWM-based vector control PMSM motor
drive system
47
6S6
5S5
4S4
3S3
2S2
1S1
1/kT
rad/sec8
K3
K2
K1
-K-
rad/sec1
PI
PIPI
d
q
theta
alpha
beta
dq0 to abc
a
b
theta
d
q
abc to dq
alpha
beta
S1
S2
S3
S4
S5
S6
SVPWM generator
Product1
Product
[vq]
Goto5
[theta]
Goto4
[vd]
Goto3
[id]
Goto2
[iq]
Goto1[theta]
From4
[id]
From3
[vq]
From2
[iq]
From10
[vd]
From1
0
Constant
5theta_e
4ib
3ia
2wm
1wref
iq
id
Figure 3.17: Simulation model of the SVPWM-based vector control subsystem
4ws_m
3theta_e
2Te
1iabc
3
vc
2
vb
1
va
theta_e
ws_memf
back EMF
ia
ib
ic
L
PM_flux
flux_a
flux_b
flux_c
Total flux linkage calculation
flux_a
flux_b
flux_c
ia
ib
ic
theta_e
p
Te
Torque calcution
vab
vbc
ia
ib
emf
Rs
flux_ab
flux_bc
Stator flux linkage calculation
Te
Tm
ws_e
the_e
the_m
ws_m
Mechnical motor calculation
vab
vbc
va
vb
vc
Line voltage block
theta_e L
Inductance
theta_e PM_flux
Flux linkage PM
flux_ab
flux_bc
L
ia
ib
ic
Current calculation
(-90)*pi/180
Constant3
Rs
Constant2
p/2
Constant
Add3
1Tm
Figure 3.18: Simulation model of the PMSM motor subsystem
2q
1d-K-
rad/sec9
-K-
rad/sec1
sin
cos
Product7
Product3
Product2
Product1
3theta
2b
1a
2beta
1alpha
sin
cos
Product7
Product3
Product2
Product1
3theta
2q
1d
(a) (b)
Figure 3.19: Simulation model of: (a) The abc-dq transformation subsystem;
(b) The dq-αβ transformation subsystem
48
0
500
1000
1500
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.2
0
0.2
0.4
Figure 3.20: Simulation results showing: (a) Mechanical speed;
(b) Electromagnetic torque
-40
-20
0
20
40
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-5
0
5
Figure 3.21: Simulation results showing: (a) Line-to-line terminal voltage;
(b) Three-phase stator current
To
rqu
e (N
m)
Time (s)
Sp
eed
(rp
m)
(a)
(b)
Sta
tor
curr
ent
(A)
Time (s)
Lin
e v
olt
age
(V)
(a)
(b)
49
-0.2
0
0.2
id
-4
0
4
8iq
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-4
0
4
8
Figure 3.22: Simulation results showing: (a) The d-axis current;
(b) The q-axis current; (c) The d-q axes current
-10
0
10id
0
20
40iq
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-20
0
20
40
Figure 3.23: Simulation results showing: (a) The d-axis command voltage;
(b) The q-axis command voltage; (c) The d-q axes command voltage
q-a
xis
cu
rren
t (A
)
Time (s)
d-q
ax
es c
urr
ent
(A)
(a)
(b)
(c)
d-a
xis
cu
rren
t (A
) q
-ax
is v
olt
age
(V)
Time (s)
d-q
ax
es v
olt
age
(V)
(a)
(b)
(c)
d-a
xis
vo
ltag
e (V
)
50
0
0.2
0.4
0.6
0.8
1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50
2
4
6
Figure 3.24: Simulation results showing: (a) Filtered PWM; (b) Vector sector
0.35
0.4
0.45
0.5
0.55
0.6
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
2
4
6
Figure 3.25: Simulation results showing: (a) Zoom-in view of filtered PWM;
(b) Zoom-in view of vector sector
3.4.2 FPGA-based controller development
In this thesis, the control algorithm was designed at high-level design flows with
graphical block diagrams of XSG tool for HDL code generation. For the
implementation of the SVPWM-based vector control scheme, several basic XSG
blocksets are utilized in the DSP subsystem block The black box of Xilinx library,
which allows the user to develop a user-defined function block, is coded with standard
VHDL in order to execute for specific purposes such as, external ADC/DAC interface,
data conversion, global timing control, and serial communication interface. The entire
motor controller module is fully integrated and realized on one-chip Xilinx XC3S1600E
FPGA. The custom ADC and DAC interface modules for a low-cost FPGA are
developed for external hardware communication. The red dashed line shows the custom
function blocks, which are implemented with Xilinx black block library. Figure 3.26
and Figure 3.27 show the simplified overall system and the overall system of the
Vec
tor
sect
or
Time (s)
Fil
tere
d P
WM
(V
)
(a)
(b)
Vec
tor
sect
or
Time (s)
Fil
tere
d P
WM
(V
)
(a)
(b)
51
XSG-based FPGA controller in MATLAB Simulink environment, which includes DSP
block for vector control algorithm, ADC interface, DAC interface, serial port
communication of Universal Asynchronous Receiver/Transmitter (UART) and Liquid
Crystal Display (LCD) interface, and global time control unit. Figure 3.28 and
Figure 3.29 show the internal structure of a FPGA-based speed controller with
SVPWM-based vector control scheme and the top-level block diagram of the overall
motor control system, respectively.
DSP for SVPWM
based
Vector Control
Algorithm
(using XSG block
library)
DAC
Interface
4
PWM1 (A/B/C)
PWM2 (A/B/C)
PWM3 (A/B/C)
PWM4 (A/B/C)
Serial
Com.
Interface
Unit
9
Analog
Multiplexer
Interface
In
Out
Out
Out
Out
6Out
Out
In
Gateway In
Gateway Out
Sub system
Black block
Legend
Number of signals
4 4Data
Conversion
ADC
Interface
4 Data
Conversion
4
DAC
(CH1-4)ADC
(CH1-4)
3
3
3
3
5
Global
Timing
Control
UnitOut
4 SCLK (1-4)
RESET
3 A/B/EN
reset
Out
UV_FAULT
Out
TX
In1
Out1
Out2
Out3
Subsystem
Out
SYNC2
Out
SYNC1
Out
SCLK4
Out
SCLK3
Out
SCLK2
Out
SCLK1
RX1
In
RX
In
RESET
In
PWM4_OC
Out
PWM4_C
Out
PWM4_B
Out
PWM4_A
In
PWM3_OC
Out
PWM3_C
Out
PWM3_B
Out
PWM3_A
In
PWM2_OC
Out
PWM2_C
Out
PWM2_B
Out
PWM2_A
PWM1_OCX
In
PWM1_OC
Out
PWM1_C
Out
PWM1_B
Out
PWM1_A
and
Logical7
Input
IGBT_FAULT1
In
IGBT_FAULT
Out
EN_MUX
ENC_B4
ENC_B3
ENC_B2
ENC_B1
ENC_A4
ENC_A3
ENC_A2
ENC_A1
ENABLE1
In
ENABLE
Ia
Ib
vdc
idc
Nrr1
Nrr2
Nrr3
Nrr4
a1_enc
b1_enc
a2_enc
b2_enc
a3_enc
b3_enc
a4_enc
b4_enc
sw_enable
IGBT_fault
enable
reset
PWM1_OC
PWM2_OC
PWM3_OC
PWM4_OC
dac1
dac2
dac3
dac4
pwm1_a
pwm1_b
pwm1_c
pwm2_a
pwm2_b
pwm2_c
pwm3_a
pwm3_b
pwm3_c
pwm4_a
pwm4_b
pwm4_c
UV_fault
Nr1
Nr2
Nr3
Nr4
Te1
Te2
Te3
Te4
Vdc
DSP
Out
DATAOUT2D
Out
DATAOUT2C
Out
DATAOUT2B
Out
DATAOUT2A
In
DATAIN1D
In
DATAIN1C
In
DATAIN1B
In
DATAIN1A
cast
Convert9
cast
Convert8
cast
Convert7
cast
Convert6
cast
Convert5
cast
Convert4
cast
Convert3
cast
Convert2
cast
Convert14
cast
Convert13
cast
Convert12
cast
Convert11
cast
Convert10
cast
Convert1
CS_FAULTX
In
CS_FAULT
Out
CS2
Out
CS1
z-1
x 2
CMult4
z-1
x 2
CMult3
z-1
x 2
CMult2
z-1
x 2
CMult1
SCLK1
RESET
DATAIN2A
DATAIN2B
DATAIN2C
DATAIN2D
cntout
DATAOUT2A
DATAOUT2B
DATAOUT2C
DATAOUT2D
SYNC1
SYNC2
Black Box6
SCLK1
DIN1
DIN2
DIN3
DIN4
cntout
DOUT1
DOUT2
DOUT3
DOUT4
Black Box5
SCLK1
DIN1
DIN2
DIN3
DIN4
cntout
DOUT1
DOUT2
DOUT3
DOUT4
Black Box4
RESET
cntout
SCLK1
SCLK2
SCLK3
SCLK4
Black Box3
RESET
nr1
nr2
nr3
nr4
Te1
Te2
Te3
Te4
vdc
rx
nrrx1
nrrx2
nrrx3
nrrx4
sw_enable
tx
Black Box1
SCLK1
RESET
DATAIN1A
DATAIN1B
DATAIN1C
DATAIN1D
cntout
CS1
CS2
DATAOUT1A
DATAOUT1B
DATAOUT1C
DATAOUT1D
Black Box
Out
B_MUX
In
B4_ENC
In
B3_ENC
In
B2_ENC
In
B1_ENC
Out
A_MUX
In
A4_ENC
In
A3_ENC
In
A2_ENC
In
A1_ENC
System
GeneratorIn
4
ENC_A (1-4)
ENC_B (1-4)
In8
FAULT
FAULT_INDICATOR
Out
In
RX
Out
TX
COUNT
Figure 3.26: Simplified overall system of the XSG-based FPGA controller
52
reset
Out
UV_FAULT
Out
TX
In1
Out1
Out2
Out3
Subsystem
Out
SYNC2
Out
SYNC1
Out
SCLK4
Out
SCLK3
Out
SCLK2
Out
SCLK1
RX1
In
RX
In
RESET
PWM4_OCX
In
PWM4_OC
Out
PWM4_C
Out
PWM4_B
Out
PWM4_A
PWM3_OCX
In
PWM3_OC
Out
PWM3_C
Out
PWM3_B
Out
PWM3_A
PWM2_OCX
In
PWM2_OC
Out
PWM2_C
Out
PWM2_B
Out
PWM2_A
PWM1_OCX
In
PWM1_OC
Out
PWM1_C
Out
PWM1_B
Out
PWM1_A
and
Logical7
Input
IGBT_FAULT1
In
IGBT_FAULT
Out
EN_MUX
ENC_B4
ENC_B3
ENC_B2
ENC_B1
ENC_A4
ENC_A3
ENC_A2
ENC_A1
ENABLE1
In
ENABLE
Ia1Ib1vdcidcNrr1Nrr2Nrr3Nrr4a1_encb1_enca2_encb2_enca3_encb3_enca4_encb4_encIGBT_faultenableresetkpdkidkpqkiqkpskisPWM1_OCPWM2_OCPWM3_OCPWM4_OCsw_enablesw_enable1sw_enable2sw_enable3sw_enable4
dac1
dac2
dac3
dac4
pwm1_a
pwm1_b
pwm1_c
pwm2_a
pwm2_b
pwm2_c
pwm3_a
pwm3_b
pwm3_c
pwm4_a
pwm4_b
pwm4_c
UV_fault
Nr1
Nr2
Nr3
Nr4
Te1
Te2
Te3
Te4
Vdc
DSP
Out
DATAOUT2D
Out
DATAOUT2C
Out
DATAOUT2B
Out
DATAOUT2A
In
DATAIN1D
In
DATAIN1C
In
DATAIN1B
In
DATAIN1A
cast
Convert9
cast
Convert8
cast
Convert7
cast
Convert6cast
Convert5
cast
Convert4
cast
Convert3
cast
Convert2
cast
Convert18
cast
Convert17
cast
Convert16
cast
Convert15
cast
Convert14
cast
Convert13
cast
Convert12
cast
Convert11
cast
Convert10
cast
Convert1
CS_FAULTX
In
CS_FAULT
Out
CS2
Out
CS1
z-1
x 2
CMult4
z-1
x 2
CMult3
z-1
x 2
CMult2
z-1
x 2
CMult1
SCLK1
RESET
DATAIN2A
DATAIN2B
DATAIN2C
DATAIN2D
cntout
DATAOUT2A
DATAOUT2B
DATAOUT2C
DATAOUT2D
SYNC1
SYNC2
Black Box6
SCLK1
DIN1
DIN2
DIN3
DIN4
cntout
DOUT1
DOUT2
DOUT3
DOUT4
Black Box5
SCLK1
DIN1
DIN2
DIN3
DIN4
cntout
DOUT1
DOUT2
DOUT3
DOUT4
Black Box3
SCLK1
RESET
DATAIN1A
DATAIN1B
DATAIN1C
DATAIN1D
cntout
CS1
CS2
DATAOUT1A
DATAOUT1B
DATAOUT1C
DATAOUT1D
Black Box2
RESET
nr1
nr2
nr3
nr4
Te1
Te2
Te3
Te4
vdc
rx
nrrx1
nrrx2
nrrx3
nrrx4
kpd
kid
kpq
kiq
kps
kis
sw_enable
sw_enable1
sw_enable2
sw_enable3
sw_enable4
tx
Black Box1
RESET
cntout
SCLK1
SCLK2
SCLK3
SCLK4
Black Box
Out
B_MUX
In
B4_ENC
In
B3_ENC
In
B2_ENC
In
B1_ENC
Out
A_MUX
In
A4_ENC
In
A3_ENC
In
A2_ENC
In
A1_ENC
SystemGenerator
vdc
Figure 3.27: Overall system of the XSG-based FPGA controller
53
Xilinx XC3S1600E FPGA
d-axis current
PI controllerADC
interface
module
DAC interface module
UART
interface
SVPWM
generator
q-axis current
PI controller
Clark
transformation
Fault trip interlock circuit
Park
transformation
Speed and Position Calculation
Speed PI
controller
Inverse Park
transformation
Global Timing Control Unit
LCD
interface
DSP for SVPWM based Vector Control Algorithm
Time multiplexing and demultiplexing
Analog
Multiplexer
interface
Figure 3.28: Internal structure of a FPGA-based speed controller with
SVPWM-based vector control scheme
A1_ENC
A2_ENC
A3_ENC
A4_ENC
B1_ENC
B2_ENC
B3_ENC
B4_ENC
CLK
CS_FAULT
DATAIN1A
DATAIN1B
DATAIN1C
DATAIN1D
ENABLE
IGBT_FAULT
PWM1_OC
PWM2_OC
PWM3_OC
PWM4_OC
RESET
RX
top_module_entity
A_MUX
B_MUX
CS1
CS2
DATAOUT2A
DATAOUT2B
DATAOUT2C
DATAOUT2D
EN_MUX
PWM1_A
PWM1_B
PWM1_C
PWM2_A
PWM2_B
PWM2_C
PWM3_A
PWM3_B
PWM3_C
PWM4_A
PWM4_B
PWM4_C
SCLK1
SCLK2
SCLK3
SCLK4
SYNC1
SYNC2
TX
UV_FAULT
top_module_entity
Figure 3.29: Top-level block diagram of the overall motor control system
54
Implementation of global timing control module
The global timing control module was implemented with the XSG black box and
written by the VHDL code. This module is used to generate appropriate timing control
signals from the clock divider circuit for synchronization clock signals (SCLK1 to
SCLK4) as required from the external ADCs and DACs for SPI communication. The
cntout variable at the output port is used to count the number of SCLK for proper timing
operation and synchronization of the ADC and DAC data conversion modules.
Figure 3.30 to Figure 3.32 show the top-level block diagram, flowchart diagram, and
timing diagram of the global time control module, respectively.
CLK
RESET
clock_gen
cntout(5:0)
SCLK1
SCLK2
SCLK3
SCLK4
comp_clock_gen
Figure 3.30: Top-level block diagram of the global timing control module
YesNo
Yes
Yes
No
reset = 1?
clkdiv2 = 0;cntint = 0;delay = 0;
clkdivider = 0;
No
CLK'event & CLK = '1'?
Delay = 2?
delay = 0;clkdivider = 1;
delay = delay+1;clkdivider = 0;
clkdiv2 = 2?
clkdiv2 = clkdiv2+1;
cntint = 17?
cntint = 0;cntint = cntint+1;
cntout = cntint;SCLK1 <= clkdivider;SCLK2 <= clkdivider;SCLK3 <= clkdivider;SCLK4 <= clkdivider;
clock_divider:process(clk,reset)
end process clock_divider
Yes
clkdiv2 = 0;
No
No Yes
Figure 3.31: Flowchart diagram of the global timing control module
55
0
5
10
15
0 0.5 1 1.5 2 2.5
x 10-6
0
0.2
0.4
0.6
0.8
1
SCLK1
Figure 3.32: Timing diagram of the global timing control module
Implementation of ADC interface module
The Pmod-AD1 module with two channels 12-bit ADC Analog Devices
AD7476 chip was selected [64],[65]. This module is used to generate appropriate
control signals of CS and DATAOUT by using a finite-state machine circuit for SPI
communication of the external ADC. Figure 3.33 shows the top-level block diagram of
ADC interface module. Figure 3.34 and Figure 3.35 show the pin interface and
functional diagram, and the serial interface time diagram of AD7476, respectively.
Figure 3.36 and Figure 3.37 show the state machine diagram and the timing diagram of
the ADC interface module, respectively.
cntout(5:0)
DATAIN1A
adc
CS1
CS2
DATAOUT1A
DATAOUT1B
DATAOUT1C
comp_adc
DATAIN1B
DATAIN1C
DATAIN1D
RESET
SCLK1
DATAOUT1D
Figure 3.33: Top-level block diagram of the ADC interface module
Figure 3.34: Pin interface and functional diagram of AD7476 [65]
cntout
SCLK1 to SCLK4
Time (s)
56
Figure 3.35: AD7476 serial interface timing diagram [65]
CS1=1
CS2=1
cnt = cntoutcnt < 3
Reset=0
CS1=0
CS2=0
DATAOUT=0
cnt = 3
CS1=0
CS2=0
DATAOUT=0
cnt > 3 & cnt < 16CS1=0
CS2=0
DATAOUT=DATAIN
cnt = 16
CS1=0
CS2=0
DATAOUT=0
CS1=1
CS2=1
DATAOUT=0
cnt > 16
Figure 3.36: State machine diagram of the ADC interface module
0
5
10
15
0
0.5
1
0 0.5 1 1.5 2 2.5
x 10-6
0
0.5
1
CS1
Figure 3.37: Timing diagram of the ADC interface module
cntout
SCLK1
Time (s)
CS1
57
Implementation of serial-to-parallel converter module
The serial-to-parallel converter module was implemented with the XSG black
box and written by the VHDL code. This module is used to convert the processing data
from serial to parallel format by taking four sets of 12-bit input data (DIN1 to DIN4) in
bit-by-bit and send these output data in parallel through the shift-register circuit. The
serial-to-parallel converter module is prerequisite for transferring the processing data
from the external ADC to the XSG-based DSP algorithm. Figure 3.38 to Figure 3.40
show the top-level block diagram, flowchart diagram, and time diagram of the
serial-to-parallel converter module, respectively.
cntout(5:0)
DIN1
ser2par
DOUT1(11:0)
DOUT2(11:0)
DOUT3(11:0)
comp_ser2par
DIN2
DIN3
DIN4
SCLK1
DOUT4(11:0)
Figure 3.38: Top-level block diagram of the serial-to-parallel converter module
YesNo
Yes
NoSCLK1'event & SCLK = 1?
cnt > 3 & cnt < 17?
temp1A = DIN1 & temp1A(11 downto 1);temp1B = DIN2 & temp1B(11 downto 1);temp1C = DIN3 & temp1C(11 downto 1);temp1D = DIN4 & temp1D(11 downto 1);
cnt = 17?
cnt = cntout;
main: process(SCLK1)
end process main
YesNo
temp2A(0 to 11) = temp1A(11 downto 0);temp2B(0 to 11) = temp1B(11 downto 0);temp2C(0 to 11) = temp1C(11 downto 0);temp2D(0 to 11) = temp1D(11 downto 0);
DOUT1 = temp2A;DOUT2 = temp2B;DOUT3 = temp2C;DOUT4 = temp2D;
Figure 3.39: Flowchart diagram of the serial-to-parallel converter module
58
0
5
10
15
0
0.5
1
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10-6
0
2000
4000
Figure 3.40: Timing diagram of the serial-to-parallel converter module
Implementation of parallel-to-serial converter module
Similar to the serial-to-parallel converter module, the parallel-to-serial converter
module was implemented with the XSG black box and written by the VHDL code. This
module is used to convert the processing data from parallel to serial format through the
shift-register circuit. In this thesis, the parallel-to-serial converter module is necessary
for interfacing the processing data from the XSG-based DSP algorithm to the external
DAC. Figure 3.41 to Figure 3.43 show the top-level block diagram, flowchart diagram,
and time diagram of the parallel-to-serial converter module, respectively.
cntout(5:0)
DIN1(11:0)
par2ser
DOUT1
DOUT2
DOUT3
comp_par2ser
DIN2(11:0)
DIN3(11:0)
DIN4(11:0)
SCLK1
DOUT4
Figure 3.41: Top-level block diagram of the parallel-to-serial converter module
cntout
DIN1
Time (s)
DOUT1
59
YesNo
Yes
NoSCLK1'event & SCLK = 0?
temp1A = DIN1;temp1B = DIN2;temp1C = DIN3;temp1D = DIN4;
temp2A(0 to 11) = temp1A(11 downto 1);temp2B(0 to 11) = temp1B(11 downto 1);temp2C(0 to 11) = temp1C(11 downto 1);temp2D(0 to 11) = temp1D(11 downto 1);
cnt > 3?
cnt = cntout;
main: process(SCLK1)
end process main
YesNo
temp2A(10 downto 0) = temp2A(11 downto 1);temp2B(10 downto 0) = temp2B(11 downto 1);temp2C(10 downto 0) = temp2C(11 downto 1);temp2D(10 downto 0) = temp2D(11 downto 1);
temp1 = temp2A(0);temp2 = temp2B(0);temp3 = temp2C(0);temp4 = temp2D(0);
DOUT1 = temp1;DOUT2 = temp2;DOUT3 = temp3;DOUT4 = temp4;
cnt = 2?
Figure 3.42: Flowchart diagram of the parallel-to-serial converter module
0
5
10
15
0
2000
4000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10-6
0
0.5
1
Figure 3.43: Timing diagram of the parallel-to-serial converter module
cntout
DIN1
Time (s)
DOUT1
60
Implementation of DAC interface module
The Pmod-DA2 module with two channels 12-bit DAC with the National
Semiconductor DAC121S101 chip was selected in this thesis [66],[67]. The DAC
interface module was implemented with the XSG black box and written by the VHDL
code. This module is used to generate appropriate control signals of SYNC and
DATAOUT by using a finite-state machine circuit for the SPI communication of the
external DAC. Figure 3.44 shows the top-level block diagram of the DAC interface
module. Figure 3.45 and Figure 3.46 show the pin interface and functional diagram and
the serial interface time diagram of AD7476, respectively. Figure 3.47 and Figure 3.48
show the state machine diagram and the timing diagram of the DAC interface module,
respectively.
cntout(5:0)
DATAIN2A
dac
SYNC1
SYNC2
DATAOUT2A
DATAOUT2B
DATAOUT2C
comp_dac
DATAIN2B
DATAIN2C
DATAIN2D
RESET
SCLK1
DATAOUT2D
Figure 3.44: Top-level block diagram of the DAC interface module
Figure 3.45: Pin interface and functional diagram of DAC121S101 [67]
Figure 3.46: DAC121S101 serial interface timing diagram [67]
61
cnt = cntout cnt < 2
Reset=0
SYNC1=0
SYNC2=0
DATAOUT=0
cnt > 1 & cnt < 5
SYNC1=0
SYNC2=0
DATAOUT=0
cnt > 4 & cnt < 17
SYNC1=1
SYNC2=1
DATAOUT=0
cnt > 16 SYNC1=0
SYNC2=0
DATAOUT=DATAIN
Figure 3.47: State machine diagram of the DAC interface module
0
5
10
15
0
0.5
1
0 0.5 1 1.5 2 2.5
x 10-6
0
0.5
1
LDAC
Figure 3.48: Timing diagram of the DAC interface module
Implementation of UART interface module
The UART interface module consists of a transmitter subsystem, a receiver
subsystem, and a baud rate generator circuit. This module was implemented with the
XSG black box and written by the VHDL code. The UART interface module is used to
manage the data exchange with serial communication between the motor controller
platform and the Personal Computer (PC) via a RS-232 port with the standard nine-pin
connector. A real-time Graphical User Interface (GUI) was developed in MATLAB
GUI environment, which allows the user to perform direct online parameters setup and
real-time monitoring of the control system. Figure 3.49 shows the top-level block
diagram of the UART interface module. Figure 3.50 to Figure 3.54 show block
diagrams and state machine diagrams of a complete UART module, the UART
transmitter, and the UART receiver, respectively. Figure 3.55 and Figure 3.56 show the
connection diagram and the state machine diagram of the LCD interface module.
Table 3.1 summarizes the LCD character display command set.
cntout
SCLK1
Time (s)
SYNC1
62
nr1(11:0)
nr2(11:0)
nr3(11:0)
nr4(11:0)
Te1(11:0)
Te2(11:0)
Te3(11:0)
Te4(11:0)
vdc(11:0)
CLK
RESET
RX
rotary_lcd_uart
kid(11:0)
kiq(11:0)
kis(11:0)
kpd(11:0)
kpq(11:0)
kps(11:0)
nrrx1(11:0)
nrrx2(11:0)
nrrx3(11:0)
nrrx4(11:0)
sw_enable
sw_enable1
sw_enable2
sw_enable3
sw_enable4
TX
rotary_lcd_uart
Figure 3.49: Top-level block diagram of the UART interface module
CLK
RX
TX din
TX_start
Transmitter
TX
Baud rategenerator
tick
s_tick
dout
RX_done
Reciever
RX
s_tick
FPGA
Figure 3.50: Block diagram of a complete UART module
63
CLK
FPGA8
Serializer
TXdin
TX_start1
1
Async Transmitter
FSM
Shiftregister
load
shif
t
Figure 3.51: Simplified block diagram of the UART transmitter
Reset=1
Wait_for_strobetx = 0
Send_start_bit
Send_bits
Send_stop_bit
tx = 1
bit_counter_tx=bit_counter_tx-1
bit_counter_tx=0
tx = shift_register_tx(0)tx = 1 bit_counter_tx=7
Figure 3.52: State machine diagram of the UART transmitter
CLK
FPGA
8
Deserializer
dout
RX_done 1
1
Async Receiver
RX
FSM
det
ect
shif
t
Shiftregister
Figure 3.53: Simplified block diagram of the UART receiver
64
Reset = 1
Wait_for_rx_start
rx = 0
Wait_half_bit
Receive_bits
Wait_for_stop_bit
rx=1
bit_counter_rx=bit_counter_rx-1
bit_counter_rx=0 bit_counter_rx=7
shift_register_rx <= rx & shift_register_rx(7 downto 1)
Figure 3.54: State machine diagram of the UART receiver
Figure 3.55: Connection diagram for the character LDC interface [68]
65
InitFinish LCD
initialization
sequenceFunction_set
LCD_RS=0
CMD=0x28
Entry_setLCD_RS=0
CMD=0x06
Set_displayLCD_RS=0
CMD=0x0CClear_displayLCD_RS=0
CMD=0x01
Pause
82000cycles
Set_ADDRLCD_RS=0
CMD=0x80
UpdateLCD_RS=1
Update
parameters
Figure 3.56: State machine diagram of the LCD interface module
Table 3.1: LCD character display command set [68]
Function
LC
D_R
S
LC
D_R
W Upper Nibble Lower Nibble
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear Display 0 0 0 0 0 0 0 0 0 1
Return Cursor Home 0 0 0 0 0 0 0 0 1 -
Entry Mode Set 0 0 0 0 0 0 0 1 I/D S
Display On/Off 0 0 0 0 0 0 1 D C B
Cursor and Display Shift 0 0 0 0 0 1 S/C R/L - -
Function Set 0 0 0 0 1 0 1 0 - -
Set CGRAM Address 0 0 0 1 A5 A4 A3 A2 A1 A0
Set DDRAM Address 0 0 1 A6 A5 A4 A3 A2 A1 A0
Read Busy Flag and Address 0 1 BF A6 A5 A4 A3 A2 A1 A0
Write Data to CG RAM or DDRAM 1 0 D7 D6 D4 D4 D3 D2 D1 D0
Read Data CG RAM or DDRAM 1 1 D7 D6 D4 D4 D3 D2 D1 D0
Implementation of analog multiplexer interface module
The analog multiplexer interface module was implemented with the XSG
blocksets for interfacing with a four-channel analog multiplexers IC MAX4618 [69].
This module is used to generate control signals of A, B, and EN for the analog
multiplexer chip with switching time of 1x10-5
s (100 kHz). Figure 3.57 to Figure 3.59
show the top-level block diagram, the XSG circuit, the time diagram of the analog
multiplexer interface module, respectively.
66
CLK
analog_mux
EN_MUX
B_MUX
A_MUX
comp_analog
RESET
Figure 3.57: Top-level block diagram of the analog multiplexer interface module
3
Out3
2
Out2
1
Out1
a
b
a < b
Relational9
a
b
a > b
Relational8
a
b
a < b
Relational7
a
b
a > b
Relational6
a
b
a > b
Relational5
or
Logical5
and
Logical4
and
Logical3
rst ++
Counter2
500
Constant9
1
Constant8
-500
Constant7
0
Constant6
1001
Constant10
1
In1
EN
AA
B
Figure 3.58: XSG circuit of the analog multiplexer interface module
0
0.5
1
0
0.5
1
0 0.5 1 1.5
x 10-4
0
0.5
1
Figure 3.59: Timing diagram of the analog multiplexer interface module
Implementation of DSP for SVPWM-based vector control algorithm
The DSP subsystem consists of the time multiplexing and demultiplexing
module, the position and speed calculation module, the SVPWM-based vector control
algorithm, and the fault trip and interlock circuit. Figure 3.60 and Figure 3.61 show the
top-level block diagram and the XSG circuit of DSP for the SVPWM-based vector
control algorithm, respectively.
EN
A
Time (s)
B
67
Ia(11:0)
Ib(11:0)
Idc(11:0)
nrr1(15:0)
nrr2(15:0)
nrr3(15:0)
nrr4(15:0)
vdc(11:0)
A1_ENC
A2_ENC
A3_ENC
A4_ENC
B1_ENC
B2_ENC
B3_ENC
B4_ENC
CLK
ENABLE
IGBT_fault
PWM1_OC
PWM2_OC
PWM3_OC
dsp
dac1(11:0)
dac2(11:0)
dac3(11:0)
dac4(11:0)
nr1(11:0)
nr2(11:0)
nr3(11:0)
nr4(11:0)
Te1(11:0)
Te2(11:0)
Te3(11:0)
Te4(11:0)
vdc_dis(11:0)
PWM1_A
PWM1_B
PWM1_C
PWM2_A
PWM2_B
PWM2_C
PWM3_A
PWM3_B
PWM3_B
PWM3_C
PWM4_A
PWM4_B
PWM4_C
UV_FAULT
comp_dsp
PWM4_OC
RESET
sw_enable
sw_enable1
sw_enable2
sw_enable3
sw_enable4
Figure 3.60: Top-level block diagram of DSP for the SVPWM-based vector control
algorithm
68
idc
26
Vdc
25
Te4
24
Te3
23
Te2
22
Te1
21
Nr4
20
Nr3
19
Nr2
18
Nr1
17
UV_fault
16
pwm4_c
15
pwm4_b
14
pwm4_a
13
pwm3_c
12
pwm3_b
11
pwm3_a
10
pwm2_c
9
pwm2_b
8
pwm2_a
7
pwm1_c
6
pwm1_b
5
pwm1_a
4
dac4
3
dac3
2
dac2
1
dac1
In1 Out1
VDC1
In1
In2
In3
In4
In5
Out1
Subsystem9
In1
In2
In3
In4
In5
Out1
Subsystem5r
In1
In2
In3
In4
In5
Out1
Subsystem3
Ia
Ib
theta_e1
wm
Nrr
vdc
Kpd
Kid
Kpq
Kiq
Kps
Kis
pwm_a
pwm_b
pwm_c
Te
theta_e
vector_sector
wm1
Subsystem2
In1
In2
In3
In4
In5
Out1
Subsystem11
In1
In2
In3
In4
In5
Out1
Subsystem10
In1
In2
Out1
Out2
Out3
Out4
Speed4
In1
In2
Out1
Out2
Out3
Out4
Speed3
In1
In2
Out1
Out2
Out3
Out4
Speed2
In1
In2
Out1
Out2
Out3
Out4
Speed1
In1
Out1
Out2
Out3
Out4
Serial-Par7
In1
Out1
Out2
Out3
Out4
Serial-Par6
In1
Out1
Out2
Out3
Out4
Serial-Par5
In1
Out1
Out2
Out3
Out4
Serial-Par4
In1
Out1
Out2
Out3
Out4
Serial-Par3
In1
Out1
Out2
Out3
Out4
Serial-Par2
In1
Out1
Out2
Out3
Out4
Serial-Par1
reinterpret
Reinterpret8
reinterpret
Reinterpret6
reinterpret
Reinterpret5
reinterpret
Reinterpret4
reinterpret
Reinterpret3
reinterpret
Reinterpret2
reinterpret
Reinterpret13
reinterpret
Reinterpret1
and
Logical9
and
Logical8
and
Logical7
and
Logical6
and
Logical5
and
Logical4
and
Logical3
and
Logical2
and
Logical13
and
Logical12
and
Logical11
and
Logical10
and
Logical1
not
Inverter2
In1
In2
In3
Out1
FAULT & INTERLOCK1
In1
Out1
Out2
Out3
Out4
Demux2
In1
Out1
Out2
Out3
Out4
Demux1
z-1
Delay3
z-1
Delay10
z-1
Delay1
++
Counter2
cast
Convert9
cast
Convert8
cast
Convert7
cast
Convert6
cast
Convert5
cast
Convert4
cast
Convert3
cast
Convert20
cast
Convert2
cast
Convert11
cast
Convert10
cast
Convert1
cast
Convert
1
Constant4
z-1
x 0.5
CMult9
z-1
x 0.5
CMult8
z-1
x 9.551
CMult7
z-1
x 9.551
CMult6
z-1
x 1.365
CMult5
z-1
x 0.5
CMult4
z-1
x 0.0128
CMult3
z-1
x 0.5
CMult2
z-1
x 1.365
CMult13
z-1
x 1.365
CMult12
z-1
x 9.551
CMult11
z-1
x 9.551
CMult10
z-1
x 1.365
CMult1
In1
In2
In3
In4
Out1
Out2
Out3
Out4
Block2
In1
In2
In3
In4
Out1
Out2
Out3
Out4
Block1
34
sw_enable4
33
sw_enable3
32
sw_enable2
31
sw_enable1
30
sw_enable
29
PWM4_OC
28
PWM3_OC
27
PWM2_OC
26
PWM1_OC
25
kis
24
kps
23
kiq
22
kpq
21
kid
20
kpd
19
reset
18
enable
17
IGBT_fault
16
b4_enc
15
a4_enc
14
b3_enc
13
a3_enc
12
b2_enc
11
a2_enc
10
b1_enc
9
a1_enc
8
Nrr4
7
Nrr3
6
Nrr2
5
Nrr1
4
idc
3
vdc
2
Ib1
1
Ia1Ia
Ib
RESET
ENABLE
vdcvdc
Vdc
UV_fault
sw_enablesw_enable
IaIa
IbIb
Figure 3.61: DSP for the SVPWM-based vector control algorithm
69
Implementation of time multiplexing and time demultiplexing module
Since the two input signals of motor currents (ia and ib) of four motor-unit
system are acquired from the external ADC via the analog multiplexer, it is necessary to
reconstruct the multiplexed signal into four original separated signals by using a digital
demultiplexer circuit, which consists of tapped delays and down sample blocksets as
shown Figure 3.62. The signal conditioning circuit of two motor stator currents is used
to eliminate the DC offset and scale to appropriate signal amplitudes. For the time
multiplexing module, a set of multiplexer units and a common count-limited counter are
implemented as shown in Figure 3.63(a). For the time demultiplexing module, the XSG
circuit consists of delay blocks, down-samplers, and up-samplers as shown in
Figure 3.63(b). Figure 3.64 shows the RTL schematic of the digital demultiplexer,
signal conditioning circuit, and time multiplexer module.
4
Out4
3
Out3
2
Out2
1
Out1
z-1
2000
Down Sample4
z-1
2000
Down Sample3
z-1
2000
Down Sample2
z-1
2000
Down Sample1
z-500
Delay3
z-1000
Delay2
z-1500
Delay1
1
In1
Figure 3.62: XSG circuit of the digital demultiplexer circuit
1
Out1
sel
d0
d1
d2
d3
Mux1
5
In5
4
In4
3
In3
2
In2
1
In1
4
Out4
3
Out3
2
Out2
1
Out1
4
Up Sample3
4
Up Sample2
4
Up Sample1
4
Up Sample
z-1
4
Down Sample4
z-1
4
Down Sample3
z-1
4
Down Sample2
z-1
4
Down Sample1
z-1
Delay3
z-2
Delay2
z-3
Delay1
1
In1
(a) (b)
Figure 3.63: XSG circuit: (a) Time multiplexer module; (b) Time demultiplexing
module
70
Figure 3.64: RTL schematic of the digital demultiplexer, signal conditioning
circuit, and time multiplexer module
Implementation of position and speed calculation module
In general, optical incremental encoder generates three output channels (A, B,
and Z). Two sequences of digital pulse trains (A and B) with 90 degree phase shift are
called quadrature encoder pulses, which can be translated into the direction and speed
information. The direction of the rotation can be determined by monitoring the relative
phase of two output channels of A and B whereas the speed is commonly determined by
using two main methods: the pulse counting method (M method) and the period
counting method (T method). In this thesis, the position and speed calculation algorithm
for high accuracy and wide range speed operation is presented. The detail of the
hardware circuit topology is depicted in Figure 3.65. The operation of the circuit can be
described as follows. The encoder digital pulse is filtered and counted with the edge
detector circuit in order to generate digital pulse trains. The electrical position
measurement is achieved by using only a single up/down binary counter whereas the
speed measurement is determined by using both update time interval and free-running
counters. The direction of motor rotation is detected by using the direction detector
circuit. The status of two input encoder signals is transformed into four states through
the state detector and state assignment circuits. The signal detector and signal
assignment circuits determine and indicate the transition of the direction of motor
rotation. Figure 3.66 shows the top-level block diagram of the position and speed
calculation module.
71
Electrical
Position (θe)
Mechanical
Speed (ωm)
Direction
Detector
Direction
Pulse TrainsA
BForward/Reverse
(FW/RW)
Incremental
Encoder
Chattering Filter
&
Edge Detector
Electrical
Position
Calculation
Up/Down
Counter
Position and Speed Calculation Module
Update Time
Interval
CounterReset
Mechanical
Speed
Calculation
Free
Running
Counter
Mu
x
Z-1
Direction DetectorA
B
State
Detector
(00,01,10,11)
Mu
x
Z-1
Z-1
+
_FW/RW
Signal
Assignment
(0,1)
Signal
Detector
(±1,±3)
State
Assignment
(1,2,3,4)
sub
Zero
Detector
10
1100
01
10
1100
01
Clockwise (FW) Counterclockwise (RW)State
00
10
11
01
Value
1
2
3
4
Figure 3.65: Block diagram of the position and speed calculation module
CLK
speed_calculation
theta_e(17:0)
wm(15:0)
nr(15:0)
comp_speed_cal1
B1_ENC
A1_ENC
DR
Figure 3.66: Top-level block diagram of the position and speed calculation module
Implementation of fault trip and interlock circuit
The XSG circuit is used to detect the fault trip signal sending from the
three-phase IGBT-based intelligent power inverter module Mitsubishi PM30CSJ060
[70] in order to protect the power module and the control circuit from the high current
short circuit. A D flip-flop register is implement for storing the value of the external
fault trip signal, which can be manually reset by pressing a push button to reset the
system. For safety operation, the enable signal is used to control the output generated
PWM for controlling the four-unit PMSM motors by using a sliding switch. The
under-voltage fault detection is used to detect and measure the value of DC bus voltage
obtained from the voltage sensor of a TI INA169 chip (AttoPilot 90A/50V) [71] through
the external ADC module. Since the rated voltage of the PMSM motor is 36 V, the XSG
circuit of under-voltage fault detection is designed to operate between the range of 34 to
38 VDC. Figure 3.67 shows the XSG circuit of the fault trip and interlock circuit.
72
1
Out1
d
rst
en
qz-1
Registerand
Logical9
and
Logical3
not
Inverter2
not
Inverter1
3
In3
2
In2
1
In1
Figure 3.67: XSG circuit of the fault trip and interlock circuit
Implementation of SVPWM-based vector control algorithm
The SVPWM-based vector control algorithm comprises of the following
subsystems: the abc-dq transformation (Clarkʼs and Parkʼs), the q-axis current PI
regulator, the d-axis current PI regulator, the speed PI regulator, the dq-αβ
transformation (inverse Parkʼs), and the SVPWM generator module. Figure 3.68 and
Figure 3.69 show the top-level block diagram and the RTL schematic of the
SVPWM-based vector control algorithm, respectively. In this thesis, all balancing
delays are manually selected and inserted into the entire design across all cut-sets for
ensuring the functional integrity with the minimum of the total computation time.
Figure 3.70 shows the XSG circuit of the SVPWM-based vector control algorithm with
balancing delays.
Ia(11:0)
vector_control
Te4x(15:0)
theta_e4x(17:0)
vector4x(2:0)
comp_vector_control
nrr(15:0)
Ib(11:0)
PWM_A4x
PWM_B4x
PWM_C4x
vdc(11:0)
theta_e(17:0)
wm(15:0)
RESET
CLK
Figure 3.68: Top-level block diagram of the SVPWM-based vector control
algorithm
73
Figure 3.69: RTL schematic of the SVPWM-based vector control algorithm
74
7
wm1
6
vector_sector
5
theta_e
4
Te
3
pwm_c
2
pwm_b
1
pwm_a
In1
In2Out1
sub3
In1
In2Out1
sub2
In2 Out1
sub1
In1
In2Out1
sub
In1 Out1
pi/30
d
q
theta
alpha
beta
dq-abc
In1
In2Out1
add2
In1
In2Out1
add1
a1
b1
theta1
d1
q1
abc-dq
In1
In2
vdc
Out1
Out2
Out3
vector sector
SVPWM_gnerator
In1
In2
In3
Out1
PI_speed
In1
In2
In3
Out1
PI_Iq
In1
In2
In3
Out1
PI_Id
In1
In2Out1
Mult2
In1
In2Out1
Mult1
In1 Out1
K4
In1 Out1
K3
In1 Out1
K1
z-1
Delay9
z-32
Delay8
z-8
Delay7
z-20
Delay6
z-4
Delay5
z-4
Delay4
z-4
Delay3
z-8
Delay2
z-16
Delay1 In1 Out1
1/kT112
Kis
11
Kps
10
Kiq
9
Kpq
8
Kid
7
Kpd
6
vdc
5
Nrr
4
wm
3
theta_e1
2
Ib
1
Ia
iqvd
Te
iqref
vq
Figure 3.70: XSG circuit of the SVPWM-based vector control algorithm with balancing delays
75
Implementation of abc-dq transformation (Clarkʼs and Parkʼs)
For the abc-dq transformation (Clark's and Park's), the XSG circuit is designed
based on the mathematical equations of (2.15) and (2.17). Figure 3.71 to Figure 3.73
show the top-level block diagram, the RTL schematic, and the XSG circuit of the
abc-dq transformation, respectively. The Xilinx CORDIC SINCOS blocksets with
parallel implementation was selected for calculating Sine and Cosine of the input angle
(z). The operation of CORDIC algorithm can be divided into three stages as follows:
(1) Coarse angle rotation; (2) Fine angle rotation; (3) Angle correction.
Ia(11:0)
abd2dq
Id(15:0)
Iq(15:0)
comp_abc2dq
theta_e(17:0)
Ib(11:0)
CLK
Figure 3.71: Top-level block diagram of the abc-dq transformation
Figure 3.72: RTL schematic of the abc-dq transformation
76
2
q1
1
d1
a
ba b
z-1
Mult6
a
ba b
z-1
Mult5
a
ba b
z-1
Mult4
a
ba b
z-1
Mult1
z-3
Delay7
z-3
Delay6
z-1
Delay5
z-2
Delay4
z-14
Delay3
z-1
Delay26
z-14
Delay2
z-1
Delay1
z-15z
cos
sin
CORDIC SINCOS1
z-1
x 1.155
CMult5
z-1
x 0.5774
CMult4 a
b
a + b
AddSub4
a
b
a + b
AddSub3
a
b
a - b
AddSub2
3
theta1
2
b1
1
a1
Clark’s transformation Park’s transformation
Figure 3.73: XSG circuit of the abc-dq transformation
Implementation of speed and current PI regulators
For the speed and current PI regulator modules, the XSG circuit is designed in a
parallel form based on the mathematical equation of (3.4). The output of PI regulators is
limited by the saturation limiter for safety reason at the limited amplitude of -50 and
+50. The controller gains of KP and KI can be tuned with on-line parameter setting via
serial communication of the UART module in MATLAB GUI on a host PC. Figure 3.74
and Figure 3.75 show the top-level block diagram and the XSG circuit of the speed PI
regulator, respectively.
In1(15:0)
PI_speed
Out1(15:0)
comp_PI_speed
CLK
Figure 3.74: Top-level block diagram of the speed PI regulator
1
Out1
a
b
a b
Relational2 a
b
a b
Relational1
sel
d0
d1
Mux1
sel
d0
d1
Mux
a
ba b
z-1
Mult2
a
ba b
z-1
Mult
z-2
Delay3
z-3
Delay2
z-4
Delay1
50
Constant4
-50
Constant1
z-1
x 0.01
CMult5
z-1
x 0.01
CMult2z-1
x 2.002e-008
CMult1
a
b
a + b
AddSub3
a
b
a + b
AddSub
3
In3
2
In2
1
In1
speed PI regurator
Saturation limiterKP
KI
Figure 3.75: XSG circuit of the speed PI regulator
77
Implementation of dq-αβ transformation (inverse Parkʼs)
Similarly, the XSG circuit of the dq-αβ transformation (inverse Parkʼs) is
designed based on the mathematical equation of (2.18). Figure 3.76 to Figure 3.78 show
the top-level block diagram, the RTL schematic, and the XSG circuit of the dq-αβ
transformation, respectively.
theta_ex(17:0)
dq2alphabeta
valpha(15:0)
vbeta(15:0)
comp_dq2alphabeta
vq(15:0)
vd(15:0)
CLK
Figure 3.76: Top-level block diagram of the dq-αβ transformation
Figure 3.77: RTL schematic of the dq-αβ transformation
78
Inverse Park’s transformation
2
beta
1
alpha
a
ba b
z-1
Mult3
a
ba b
z-1
Mult2
a
ba b
z-1
Mult1
a
ba b
z-1
Mult
z-3
Delay6
z-3
Delay5
z-16
Delay4
z-16
Delay3
z-1
Delay2
z-1
Delay1z-15z
cos
sin
CORDIC SINCOS2
a
b
a + b
AddSub1
a
b
a - b
AddSub
3
theta
2
q
1
d
Figure 3.78: XSG circuit of the dq-αβ transformation
Implementation of three-phase SVPWM generator module
The three-phase SVPWM generator module is designed based on the
mathematical equations of (2.46) to (2.58), which consists of several subsystems,
including vector amplitude and angle calculation subsystem, switching time amplitude
calculation subsystem, vector sector calculation subsystem, time sequence calculation
subsystem, time phase calculation subsystem, triangular generator subsystem, and PWM
generator subsystem. Due to the sophisticated algorithm of the SVPWM generator
module, several complex arithmetic operations are required, including adders,
subtractors, multipliers, divider, square root, and trigonometric functions (sin, cos,
arctan). In this thesis, the Xilinx CORDIC blocksets have been used for all
trigonometric functions, including sin-cos and arctan (coarse angle rotation module, fine
angle rotation modules, angle correction module), square root and divider (co-ordination
rotation and correction modules, linear rotation module, and hyperbolic module).
Figure 3.79 and Figure 3.80 show the top-level block diagram and the XSG circuit of
the three-phase SVPWM generator module, respectively. Figure 3.81 to Figure 3.84
show the top-level block diagram and the XSG blockset of the CORDIC algorithms for
sin-cos, arctan, divider, square root, respectively.
valpha(15:0)
svpwm
vector(2:0)
PWM_C
comp_svpwm
vdc(11:0)
vbeta(15:0)
CLK
PWM_B
PWM_A
Figure 3.79: Top-level block diagram of the three-phase SVPWM generator
module
79
Vector amplitude and angle calculation
4
vector sector
3
Out3
2
Out2
1
Out1
In1 Out1
Vector Sector
Out1
Tri Generator1In1
In2
In3
In4
Out1
Out2
Out3
Time sequence Calculation
In1
In2
In3
In4
Out1
Out2
Out3
Time phase Calculation
va
t1
vb
t2
vc
t3
s1
s2
s3
PWM Generator1
a
ba b
z-1
Mult4
a
ba b
z-1
Mult2
z-24
Delay8
z-3
Delay5
z-28
Delay4
z-2
Delay3
z-20
Delay2
z-2
Delay1
z-32
Delay
cast
Convert6
6.2480568885803223e-005
Constant1
z-29x sqrt x
CORDIC SQRT
z-11
x
y
mag
atan
CORDIC ATAN
z-1
x 0.5
CMult5
z-1
x 0.02173
CMult2
z-1
x 0.02173
CMult1
In1
In2
In3
Out1
Amplitude Calculation
a
b
a - b
AddSub16
a
b
a - b
AddSub15
a
b
a + b
AddSub14
a
b
a - b
AddSub10
3
vdc
2
In2
1
In1
Switching time amplitude calculation
Vector sector calculation
Time sequence calculation Time phase calculation Triangular generator
PWM generator
Figure 3.80: XSG circuit of the three-phase SVWPM generator module
In1_z(11:0)
CORDIC_SINCOS5
Out1_cos(11:0)
comp_CORDIC_SINCOS5
CLK Out2_sin(11:0)
1
Out1
a
ba b
z-1
Mult6
a
ba b
z-1
Mult51.732421875
Constant12
z-15z
cos
sin
CORDIC SINCOS5
x
y
divz-24
x
y
y/x
CORDIC DIVIDER1
3
In3
2
In2
1
In1
(a) (b)
Figure 3.81: CORDIC sin-cos: (a) Top-level block diagram; (b) XSG blocksets
In1_x(11:0)
CORDIC_ATAN1
Out1_mag(11:0)
comp_CORDIC_ATAN1
CLK Out2_atan(11:0)
In1_y(11:0)
1
Out1
a
ba b
z-1
Mult6
a
ba b
z-1
Mult51.732421875
Constant12
x
y
divz-24
x
y
y/x
CORDIC DIVIDER1
z-11
x
y
mag
atan
CORDIC ATAN1
3
In3
2
In2
1
In1
(a) (b)
Figure 3.82: CORDIC arctan: (a) Top-level block diagram; (b) XSG blocksets
In1_x(11:0)
CORDIC_DIVIDER1
Out1_yx(27:0)
comp_CORDIC_DIVIDER1
CLK
In1_y(11:0)
4
vector sector
3
Out3
2
Out2
1
Out1
In1 Out1
Vector Sector
Out1
Tri Generator1In1
In2
In3
In4
Out1
Out2
Out3
Time sequence Calculation
In1
In2
In3
In4
Out1
Out2
Out3
Time phase Calculation
va
t1
vb
t2
vc
t3
s1
s2
s3
PWM Generator1
a
ba b
z-1
Mult4
a
ba b
z-1
Mult2
z-24
Delay8
z-3
Delay5
z-28
Delay4
z-2
Delay3
z-20
Delay2
z-2
Delay1
z-32
Delay
cast
Convert6
6.2480568885803223e-005
Constant1
z-29x sqrt x
CORDIC SQRT
x
y
divz-24
x
y
y/x
CORDIC DIVIDER1
z-11
x
y
mag
atan
CORDIC ATAN
z-1
x 0.5
CMult5
z-1
x 0.02173
CMult2
z-1
x 0.02173
CMult1
In1
In2
In3
Out1
Amplitude Calculation
a
b
a - b
AddSub16
a
b
a - b
AddSub15
a
b
a + b
AddSub14
a
b
a - b
AddSub10
3
vdc
2
In2
1
In1
(a) (b)
Figure 3.83: CORDIC divider: (a) Top-level block diagram; (b) XSG blocksets
In1_x(13:0)
CORDIC_SQRT1
Out1_sqrtx(31:0)
comp_CORDIC_SQRT1
CLK
1
Out1
a
ba b
z-1
Mult6
a
ba b
z-1
Mult51.732421875
Constant12
z-29x sqrt x
CORDIC SQRT1
x
y
divz-24
x
y
y/x
CORDIC DIVIDER1
3
In3
2
In2
1
In1
(a) (b)
Figure 3.84: CORDIC square root: (a) Top-level block diagram; (b) XSG blocksets
80
Implementation of vector sector calculation subsystem
The input signal of this subsystem is the reference voltage vector angle (α),
which is obtained from the Xilinx CORDIC ATAN (ranging between -π to π). The
constant gain (CMult) of XSG blocksets is used to convert this vector angle from
radians into degrees between -180 to 180. The vector sector calculation circuit using
XSG blocksets, including relational, logical (AND), constant, CMult, and addsub, are
used to determine the value of vector sector between 1 and 6. Figure 3.85 and
Figure 3.86 show the top-level block diagram and the XSG circuit of the vector sector
calculation subsystem, respectively.
In1_(11:0)
vector_sector
Out1(2:0)
comp_vector_sector
CLK
Figure 3.85: Top-level block diagram of the vector sector calculation subsystem
1
Out1
a
b
a b
Relational9
a
b
a > b
Relational8
a
b
a b
Relational7
a
b
a > b
Relational6
a
b
a b
Relational5
a
b
a > b
Relational4
a
b
a b
Relational3
a
b
a > b
Relational2
a
b
a b
Relational11
a
b
a > b
Relational10
a
b
a b
Relational1
a
b
a > b
Relational
and
Logical5
and
Logical4
and
Logical3
and
Logical2
and
Logical1
and
Logical
z-2
Delay8
cast
Convert6
cast
Convert5
cast
Convert4
cast
Convert3
cast
Convert2
cast
Convert1
cast
Convert
-120
Constant9
-120
Constant8
0
Constant7
-180
Constant6
180
Constant5
120
Constant4
120
Constant3
60
Constant2
0
Constant12
-60
Constant11
-60
Constant10
60
Constant1
z-1
x 57.3
CMult7
z-1
x 6
CMult6
z-1
x 5
CMult5
z-1
x 4
CMult4
z-1
x 3
CMult3
z-1
x 2
CMult2
z-1
x 1
CMult1
a
b
a + b
AddSub5
a
b
a + b
AddSub4
a
b
a + b
AddSub3
a
b
a + b
AddSub2
a
b
a + b
AddSub1
1
In1
Figure 3.86: XSG circuit of the vector sector calculation subsystem
81
Implementation of time phase calculation subsystem
The time phase calculation subsystem is used to determine the switching time of
each power transistor switch (S1 to S6) at any vector sectors, which is designed based on
Table 2.3 for switching patterns of SVPWM at each sector. Figure 3.87 to Figure 3.89
show the top-level block diagram, the RTL schematic, and the XSG circuit of the time
phase calculation subsystem, respectively.
Out1(29:0)
time_phase_calculation
In1(29:0)
In2(29:0)
In3(29:0)
comp_time_phase_calculation
Out3(29:0)
Out2(29:0)
In4(2:0)
Figure 3.87: Top-level block diagram of the time phase calculation subsystem
Figure 3.88: RTL schematic of the time phase calculation subsystem
82
3
Out3
2
Out2
1
Out1
sel
d0
d1
d2
d3
d4
d5
d6
d7
Mux3
sel
d0
d1
d2
d3
d4
d5
d6
d7
Mux2
sel
d0
d1
d2
d3
d4
d5
d6
d7
Mux1
0
Constant12
a
b
a + b
AddSub5
a
b
a + b
AddSub2
a
b
a + b
AddSub1
4
In4
3
In3
2
In2
1
In1
Figure 3.89: XSG circuit of the time phase calculation subsystem
Implementation of triangular generator subsystem
The triangular generator subsystem is implemented by using four sets of
count-limited counters. The counter9 is set to the direction of count up and compare the
output value with a constant in order to generate the control signal to enable three
count-limited counters in boolean format. The counter7 and counter8 are set to the
direction of count up and count down, respectively, in order to generate the triangular
waveform whereas the counter6 is used to select the output waveform between these
two counters (counter7 and counter8) at half of switching period. In this thesis, the
triangular generator is set to generate the triangular carrier waveform with switching
frequency for the three-phase inverter at 16 kHz. The output CMult blocks is used to
adjust the triangular waveform to appropriate amplitude level. Figure 3.90 and
Figure 3.91 show the top-level block diagram and the XSG circuit of the triangular
generator subsystem, respectively.
tri_generator
Out1(31:0)
comp_tri_generator
CLK
Figure 3.90: Top-level block diagram of the triangular generator subsystem
83
1
Out1
a
b
a = b
Relational3
a
b
a < b
Relational2
sel
d0
d1
Mux3
sel
d0
d1
Mux2
not
Inverter1
z-3
Delay6
++
Counter9
en --
Counter8
en++
Counter7
en++
Counter6
3
Constant8 0
Constant7
0
Constant6
0
Constant5
z-1
x 2.98e-007
CMult2
a
b
a + b
AddSub1
Figure 3.91: XSG circuit of the triangular generator subsystem
Implementation of PWM generator subsystem
The PWM generator consists of the XSG blocksets of addsub, relational, and
constant. The output PWM signals are generated by comparing a triangular carrier
waveform with switching frequency of 16 kHz to three-phase reference modulating
signals. When the reference modulation signal is greater than the triangular carrier, the
PWM signal is set to high state. When the reference modulation signal is lower than the
triangular carrier, the PWM signal is set to low state. Figure 3.92 to Figure 3.94 show
the top-level block diagram, the RTL schematic, and the XSG circuit of the PWM
generator subsystem, respectively.
In1(29:0)
PWM_generator
comp_PWM_generator
In3(29:0)
In2(31:0)
Out1
Out2
Out3
In5(29:0)
In4(31:0)
In6(31:0)
Figure 3.92: Top-level block diagram of the PWM generator subsystem
84
Figure 3.93: RTL schematic of the PWM generator subsystem
3
s3
2
s2
1
s1
a
b
a b
Relational3
a
b
a b
Relational2
a
b
a b
Relational1
0
Constant4
0
Constant3
0
Constant1
a
b
a - b
AddSub2
a
b
a - b
AddSub1
a
b
a - b
AddSub
6
t3
5
vc
4
t2
3
vb
2
t1
1
va
Figure 3.94: XSG circuit of the PWM generator subsystem
3.4.3 Dead time generator circuit
In order to minimize digital I/O pins, the external circuit using hex schmitt
trigger CD40106BC [72] for PWM dead time generator has been implemented instead
of using on-chip FPGA digital hardware design. For generation of the delay with dead
time of 3 μs, the value of resistors and capacitors has been selected to 33 kΩ and
100 pF, respectively. This design allows a significant digital I/O pins reduction by half
of pin counts, especially when motor drive system operates with a large number of
motor units. Figure 3.95 and Figure 3.96 show the circuit diagram and the timing
diagram of the dead time generator circuit, respectively. Figure 3.97 shows
experimental results of PWM_in at 16 kHz, PWM_out and PWM_outbar with dead
time of 3 μs and 3.5 μs, respectively.
85
In
Out
Out___
R
R
C
C
Figure 3.95: Circuit diagram of the dead time generator circuit
Time (s)
Time (s)
Time (s)
In
Out
Time (s)
PWM PeriodTri
Ref
___Out
Figure 3.96: Timing diagram of the dead time generator circuit
(a) (b)
(c) (d)
Figure 3.97: Experimental results: (a) PWM_in (Yellow) with frequency of 16 kHz
at x-axis = 25 μs/div; (b) PWM_in (Yellow) with frequency of 16 kHz at x-axis =
10 μs/div; (c) PWM_out (Pink) with dead time of 3 μs at x-axis = 1 μs/div;
(d) PWM_outbar (Green) with dead time of 3.5 μs at x-axis = 1 μs/div
3 μs 3.5 μs
PWM_in (Yellow)
PWM_out (Pink)
PWM_outbar (Green)
PWM_in (Yellow)
PWM_out (Pink)
PWM_outbar (Green)
PWM_in (Yellow)
PWM_out (Pink)
PWM_outbar (Green)
PWM_in (Yellow)
PWM_out (Pink)
PWM_outbar (Green) x-axis: 1 μs/div
y-axis: 1 V/div
x-axis: 25 μs/div
y-axis: 1 V/div
x-axis: 10 μs/div
y-axis: 1 V/div
x-axis: 1 μs/div
y-axis: 1 V/div
86
3.4.4 Hardware solution using analog multiplexer
Due to the fact that the number of controlled motors is physically limited by the
number of FPGA board I/O pins. In order to minimize the required digital interface I/O
pins, an analog multiplexer is employed to measure the motor phase current from
four-unit motors. Figure 3.98 shows the connection diagram of the hardware solution
using an analog multiplexer measuring current phase-A. With this approach, the same
phase current of different motors can be managed by using only single common ADC,
which can effectively reduce the system cost as well as the number of digital I/O pins.
The measured output sensor signals are connected directly to the analog multiplexer of
IC MAX4618 [69]. The desired output channel of analog multiplexer can be selected
through the channel selector, which manipulated by a FPGA chip. The current sensors
with appropriate output voltage range can be chosen to match the input voltage level of
the ADC in order to avoid the use of additional amplifier gain circuit. The switching
time from one channel to another channel of analog multiplexer is selected to 1x10-5
s
(100 kHz). Since the motor windings are arranged with common star-connected without
neutral access point, measuring only two phase motor currents is sufficient enough by
using only two common analog multiplexers and two ADCs. Figure 3.99 and
Figure 3.100 show the timing diagram of the analog multiplexer interface module and
the pin configuration of MAX4618, respectively. Table 3.2 shows truth table of the
analog multiplexer IC MAX4618. Figure 3.101 shows experimental results of the
analog multiplexer with fs,analog = 50 kHz.
1
Channel selector (A,B)
FPGA
Controller
Mu
x A/D2
3
4
Enable (E)
1 1
From four sets of three-phase inverter
Hall-effect
current sensor
ABC ABC ABC ABC
Figure 3.98: Connection diagram of the hardware solution using an analog
multiplexer (measuring current phase-A)
87
EN
A
B
Ts = 50 kHz
Ts = 100 kHz
Figure 3.99: Timing diagram of the analog multiplexer interface module
Figure 3.100: Pin configuration and functional diagram of MAX4618 [69]
Table 3.2: Truth table of the analog multiplexer IC MAX4618 [69]
Enable
Input
Select Inputs On Switches
B A MAX4618
H X X All switches open
L L L X-X0
Y-Y0
L L H X-X1
Y-Y1
L H L X-X2
Y-Y2
L H H X-X3
Y-Y3
88
(a) (b)
(c) (d)
(e) (f)
Figure 3.101: Experimental results showing the analog multiplexer with fs,analog =
50 kHz: (a) Input analog signals of X0(Yellow), X1(Blue), X2(Pink), X3(Green) at
x-axis = 5 ms/div; (b) Control digital signals of EN(Yellow), A(Blue), B(Pink) and
output analog signal of X(Green) at x-axis = 2.5 ms/div; (c) Zoom-in view at x-axis
= 500 μs/div; (d) Zoom-in view at x-axis = 50 μs/div; (e) Zoom-in view showing the
frequency of A and B of 25 kHz and 50 kHz at x-axis = 10 μs/div; (f) Zoom-in view
showing the analog output signal of X(Green) consists of different multiplexed
input analog signals (X0-X3) at each control digital signal period at x-axis =
5 μs/div
EN
A
B
X(outuput)
X0 (100 Hz)
X1 (125 Hz)
X3 (200 Hz)
X2 (150 Hz)
EN (Logic Low , "0")
A (Ts = 25 kHz)
B (Ts = 50 kHz)
X(outuput)
EN
A
B
X(outuput)
EN (Logic Low , "0")
A (Ts = 25 kHz)
B (Ts = 50 kHz)
X(outuput)
X0
X1
X2 X3
20 μs
40 μs
EN
A
B
X(outuput)
X0
X1
X2 X3
x-axis: 5 ms/div
y-axis: 1 V/div
x-axis: 2.5 ms/div
y-axis: 1 V/div
x-axis: 500 μs/div
y-axis: 1 V/div
x-axis: 50 μs/div
y-axis: 1 V/div
x-axis: 10 μs/div
y-axis: 1 V/div
x-axis: 5 μs/div
y-axis: 1 V/div
89
3.4.5 Experimental setup
The motor specification and parameters of four identical low power PMSM
motors (PMSM1 to PMSM4) are summarized in Appendix A. The experimental system
has been set up to demonstrate the validation of the proposed effective time
multiplexing scheme as well as the proposed simple speed calculation hardware circuit
design. The experimental system consists of four sets of PMSM motors, four units of
three-phase IGBT-based voltage source inverters, an Spartan-3E 1600E development
board, which contains a Xilinx XC3S1600E FPGA chip and an on-board 50 MHz clock
oscillator; 2-channal, 12-bit ADC and DAC modules, analog multiplexers, and dead
time generator circuits as shown in Figure 3.102 (see Appendix B). The common
voltage of DC bus is set to 36 V and the switching frequency of PWM inverter is set to
16 kHz. The motor optical encoder has a resolution of 2500 PPR. To minimize digital
I/O pins, four external circuits using schmitt trigger inverters for PWM dead time
generator have been implemented instead of using on-chip FPGA dead time circuit.
This design allows a significant digital I/O pins reduction by half of pin counts.
Figure 3.103 shows the connection diagram of the FPGA pin interface for implementing
the four-unit PMSM motor drive system. The complete hardware prototype and
experimental setup is shown in Figure 3.104. A real-time GUI was developed in
MATLAB GUI environment, which allows the user to perform direct online parameters
setup and real-time monitoring of the control system on a host PC as shown in
Figure 3.105. Figure 3.106 shows four low-power PMSM motors used in the laboratory.
Figure 3.107 shows the PMSM motor coupling with a 250W DC motor on the motor
mounting base for experimental testing during the load test. Figure 3.108 shows the
experimental setup of the SVPWM-based vector control PMSM motor drive system
during the load test by using resistive-load lamps.
Current feedback
Position feedback
Xilinx XC3S1600E FPGA
ADC
interface
LCD
display
LCD
display
interface
Speed
command
MATLAB
GUI
DAC
interface
Inverter
Enc_A
Enc_B
ia
ib
Encoder
ADC
1
1
4
4
4
-
~~~
-
~~~
-
~~~
-
~~~
3
3
3
Dead band
1
1Mux
Mux
3 6
6
6
6
PMSMPMSMPMSMPMSM
SVPWM
based
Vector
Control
Algorithm
Mux
Demux
Demux
4
RS-232
interface
PC user
interface
ωref
VDC IDC
Clock
generator
Motor
protection
2
Mux
DAC2
Digital
Oscilloscope
2
DAC2 2
ADC 2
Figure 3.102: Schematic diagram of the complete system of the SVPWM-based
vector control four-unit PMSM motor drive
90
LCD
ADC
module
Current_A_PMSM1
Current_A_PMSM2
Current_A_PMSM3
Current_A_PMSM4
Analog
Mulitplexer
Current_B_PMSM1
Current_B_PMSM2
Current_B_PMSM3
Current_B_PMSM4
Current_A
Current_B
VDC_bus
IDC_bus
ADC
module
DAC module
Dead time
generator PWM_PMSM13 6
Dead time
generator PWM_PMSM23 6
Dead time
generator PWM_PMSM33 6
Dead time
generator PWM_PMSM43 6
DAC module
Analog
Mulitplexer
To Three-phase Inverters
To Digital Oscilloscope
From Hall-effect
Current Sensors
From DC voltage
& DC current sensors
1
1
1
1
8
A
B
LCD
Motor encoder
LCD DisplayHost PC
RS-232
2
2
GUI
Xilinx
XC3S1600E
FPGA
Figure 3.103: Connection diagram of the FPGA pin interface for implementing the
four-unit PMSM motor drive system
Figure 3.104: Completed hardware prototype and experimental setup
Figure 3.105: MATLAB GUI for on-line parameter setting and real-time
monitoring of the four-unit motor drive system
91
Figure 3.106: Four low-power PMSM motors
Figure 3.107: PMSM motor coupling with a 250W DC motor on the motor
mounting base
Figure 3.108: Experimental setup of the SVPWM-based vector control PMSM
motor drive system during the load-test by using resistive-load lamps
92
CHAPTER 4
RESULTS AND DISCUSSION
4.1 Position and speed calculation module
In this section, two experiments have been performed to validate the proposed
speed calculation module. For the first experiment, the rotational motor speed is
controlled up to the rated motor speed at 3,000 rpm. Comparative experiments among
four-unit PMSM motors with incremental encoders mounting on the motor shaft have
been investigated. The experimental result shown in Figure 4.1 reveals that good
accuracy in speed measurement can be achieved for the entire motor speed range with a
relative error less than 0.75% for four PMSM motors. The larger error at lower speed is
due to the fact that the prime mover motor (DC motor) coupling with the PMSM motor
cannot maintain constant speed when a very small constant DC voltage is applied. For
the second experiment, in order to verify speed accuracy at very high rotational speed,
the most straightforward way is to feed digital pulse signals generated from a function
generator to the FPGA chip directly. A function generator is utilized to simulate the
emulated encoder signals in an extremely wide range of frequencies. The result reveals
that in an ideal case the proposed algorithm can operate at very high speed theoretically
up to 60,000 rpm for the 2,500 PPR encoder, with good accuracy of 0.05 % relative
error as shown in Figure 4.2. This performance achievement confirms that the proposed
speed calculation algorithm can provide a wide-range speed evaluation with good
accuracy, which makes it suitable for applications of very high speed motor control
systems.
0 500 1000 1500 2000 2500 30000
0.25
0.5
0.75
1
PMSM1
PMSM2
PMSM3
PMSM4
Figure 4.1: Experimental results of the speed calculation module verified with the
motor shaft encoder
101
102
103
104
105
-0.01
0
0.01
0.02
0.03
0.04
0.05
Figure 4.2: Experimental results of the speed calculation module verified with a
function generator
Rel
ativ
e er
ror
(%)
Speed (rpm)
Speed (rpm)
Rel
ativ
e er
ror
(%)
93
4.2 Single-unit PMSM motor drive system with SVPWM-based vector control
scheme
The detail of resource utilization for controlling single-unit PMSM motor drive
system is summarized in Table 4.1. It can be clearly observed that due to sophisticated
algorithm of the SVPWM-based vector control scheme, two major modules of the
SVPWM generator and the coordinate transformation consume large amounts of FPGA
resources for the hardware implementation of the CORDIC sin/cos function, square
root, and divider. In addition, due to the limitation of hardware resources and on-chip
embedded multipliers available in low-cost FPGAs, it is not possible to fit a large
number of identical controller modules into a single chip FPGA for applications of
multi-motor control system. In order to verify the correctness of SVPWM generator
module, Figure 4.3 shows experimental results of three-phase filtered PWM waveforms,
the vector sector, and the electrical position when PMSM1 is running at 1200 rpm. The
experimental results prove that the SVPWM generator module can perform correctly
with the saddle waveform, which agrees with the theoretical analysis. In addition, it can
confirm that the FPGA-based controller design using XSG tool for a single-unit PMSM
motor drive system can operate correctly with a constant speed of the motor at
1200 rpm.
Table 4.1: Detail of resource utilization for controlling of a single-unit of PMSM
motor drive system on Xilinx XC3S1600E FPGA
Module
Circuit
Sub-module
Circuit
Occupied
Slices
CLB
Flip Flops
4 input
LUTs
MULT18X18
ISOs
Motor
controller
Encoder position and
speed calculation 176 133 325 0
Speed and current PI
regulators 815 244 1452 0
Feed-forward
compensation
scheme
280 104 454 2
SVPWM generator 2786 3620 4816 19
Rotating coordinate
transformation 915 1403 1630 8
Global timing control unit 11 15 19 0
ADC and DAC interface 14 20 15 0
Data transmission converter 112 206 110 0
Serial communication for GUI
interface 739 341 1200 0
Protection unit and auxiliary
module 20 107 72 0
Total
Used 5868 6193 10093 29
Available 14752 29504 29504 36
% 39 20 34 80
94
0 0.01 0.02 0.03 0.04 0.050.65
1.65
2.65
0 0.01 0.02 0.03 0.04 0.050
2
4
6
0 0.01 0.02 0.03 0.04 0.05
-180
0
180
Figure 4.3: Experimental results showing: (a) Filtered PWM waveforms; (b)
Vector sector; (c) Electrical position when PMSM1 is running at 1200 rpm
4.3 Multi-unit PMSM motor drive system with SVPWM-based vector control
scheme
In order to validate the proposed method of system-level time-division
multiplexing, three experimental conditions were demonstrated. For the first condition,
experimental results were obtained with two PMSM motors (PMSM1 and PMSM2)
running with different rotational speed and PMSM1 is applied with a step speed
command. For the second condition, experimental results were obtained with two
PMSM motors starting with a no-load torque condition and PMSM1 is applied with a
step load change. Figure 4.4 and Figure 4.5 show the dynamic responses of speed and
stator current of two PMSM motors during a step speed command, and a step load
change applied to PMSM1, respectively. It can be concluded that the drive system using
the proposed method can operate two controlled motors independently for a sudden
change of speed references and load disturbances. The speed and torque command
applied to one motor has no influence on the other motor. For control performance
evaluation, a comparison of the speed transient response between a conventional design
method (two identical control modules) and the proposed time-division multiplexing
method is shown in Figure 4.6. It can be seen that the motor drive system using the
proposed method can operate effectively without speed performance degradation when
comparing with a conventional approach. Finally, for the third condition, experimental
results were obtained with four PMSM motors (PMSM1 to PMSM4) running with
different rotational speeds. Figure 4.7 shows dynamic speed responses of four PMSM
motors during a step speed command applied to PMSM1. Figure 4.8 shows stator
currents of four PMSM motors during a step load change applied to PMSM1. The
experimental results prove the effectiveness that the multi-motor drive system using a
low-cost FPGA based on the proposed time-division multiplexing can operate a group
of four motors simultaneously and independently under different operating conditions.
Time (s)
Va Vb Vc
Vo
ltag
e (V
) S
ecto
r P
osi
tio
n (
Deg
ree)
(a)
(b)
(c)
95
0 1 2 3 4 50
1000
2000
3000
0 1 2 3 4 5-15
0
15
0 1 2 3 4 5-15
0
15
Figure 4.4: Experimental results showing the dynamic responses of speed and
stator current of two motors during a step speed command applied to the motor
PMSM1
0 1 2 3 4 50
1000
2000
3000
0 1 2 3 4 5-15
0
15
0 1 2 3 4 5-15
0
15
Figure 4.5: Experimental results showing the dynamic responses of speed and
stator current of two motors during a step load change applied to the motor
PMSM1
PMSM1
PMSM1
PMSM2
PMSM2
Sp
eed
(rp
m)
Cu
rren
t (A
)
Time (s)
Cu
rren
t (A
)
PMSM2
Time (s)
PMSM2
PMSM1 Sp
eed
(rp
m)
Cu
rren
t (A
) PMSM1
Cu
rren
t (A
)
96
0 2 4 6 8 100
1000
2000
3000
Conventional method
Proposed method
Figure 4.6: Comparison of speed responses between a conventional method
(using two identical modules) and the proposed method
(time-division multiplexing)
0 2 4 6 80
500
1000
1500
2000
2500
Figure 4.7: Experimental results showing dynamic speed responses of four motors
during a step speed command applied to the motor PMSM1
Time (s)
Sp
eed
(rp
m)
Sp
eed
(rp
m)
PMSM1
PMSM4
PMSM3
PMSM2
Time (s)
800 rpm
1000 rpm
1200 rpm
1400 rpm
1600 rpm
97
0 0.5 1 1.5 2-12
0
12
0 0.5 1 1.5 2-12
0
12
0 0.5 1 1.5 2-12
0
12
0 0.5 1 1.5 2-12
0
12
Figure 4.8: Experimental results showing stator currents of four motors during a
step load change applied to the motor PMSM1
4.4 Performance analysis of multi-unit PMSM motor drive system
The detail of resource utilization for implementing the proposed time-division
multiplexing scheme is presented in Table 4.2. The time multiplexing and
demultiplexing module utilizes 1.27% (188 of 14,752) for occupied slices, 0.7% (200 of
29,504) for Configurable Logic Block (CLB) flip flops, and 0.13% (40 of 29,504) for
4-input Lookup Tables (LUTs). Table 4.3 shows a comparison of resource utilization on
a XCS1600E FPGA for controlling a different number of PMSM motors. It should be
noted that in case of the design of two units of PMSM motor, once the number of
embedded multipliers reaches to the maximum 100% of the available resources, the rest
are converted into a LUT-based multiplier implementation. It can be seen that the
proposed time-division multiplexing scheme effectively minimizes the resource usage
comparing with a conventional method, and can be employed to alleviate the design
constraints related to resource limitations. This approach improves considerably the
resources utilization allowing the system to control a large number of motor units
(four-motor units in the present case). The performance analysis shows that total
occupied resources for the four motor units design with the proposed method are
perfectly fitted and can be accommodated into low-cost FPGAs. The overall system
consumes 66% of occupied slices, 28 % of CLB flip flop, 59% of 4-input LUTs and
80% of embedded multipliers of available FPGA resources on the chip.
Cu
rren
t (A
) PMSM1
PMSM3
PMSM4
Nr= 800 rpm
Nr= 1000 rpm
Nr= 1400 rpm
Nr= 1200 rpm
PMSM2
Time (s)
Cu
rren
t (A
) C
urr
ent
(A)
Cu
rren
t (A
)
98
Table 4.2: Detail of resource utilization for implementing the proposed
time-division multiplexing scheme on XCS1600E FPGA
Module Circuit Occupied
Slices
CLB
Flip Flops
4 input
LUTs
MULT18X18
ISOs
Time multiplexing and
demultiplexing 188 200 40 0
Analog multiplexer interface 31 16 58 0
Signal conditioning 964 337 1632 0
Total 1183
(8%)
553
(1%)
1730
(5%)
0
(0%)
Table 4.3: Comparison of resource utilization for controlling different units of
PMSM motors
Unit of
PMSM
motors
Hardware design
approach
Occupied
Slices (%)
CLB Flip
Flops (%)
4 input
LUTs (%)
MULT18X18
ISOs (%)
1 Single module 39 20 34 80
2
Two identical
modules 81 40 76 100
Proposed time
multiplexing 55 25 48 80
4
Four identical
modules Insufficient resources
Proposed time
multiplexing 66 28 59 80
For embedded system design, nowadays two main design approaches, namely
the HDL coding and the code generator tool, have been widely used. For the HDL
method, hardware programming can be optimized at low-level design aspects with
minimum resource usage whereas it requires more design time and efforts during the
debugging process. The code generator can provide fast development cycle while the
traceability and readability of the generated HDL code is poor. In order to evaluate the
efficiency of code generators, in the literature several studies on a comparison between
the HDL coding and the XSG implementation have been investigated, including
adaptive filer [73], and image processing [74],[75]. In this thesis, for a comparison
purpose the complete motor control system have been developed with two design
methods. The standard VHDL code is designed with the same control algorithm and
similar to Xilinx hardware blocks in term of algorithm complexity, functionality, and
signal word-lengths. Table 4.4 shows a comparison of resource utilization between
VHDL and XSG implementations for four motor units with the proposed time-division
multiplexing. By setting with the same number of embedded multipliers usage, it can be
clearly observed that resource utilization of the HDL coding is lower than the code
generator tool. The maximum clock frequency of the XSG implementation can be
achieved at 50.186 MHz, which is slightly lower than the VHDL approach of
50.203 MHz. In this thesis, although the code generator tool cannot provide an
area-optimized solution compared to the VHDL design method, the XSG tool is
efficient to realize the complete system on low-cost FPGAs with similar performance in
term of clock speed. Thus, for multi-motor control system the code generator tool can
99
provide fast design entry and allows to refine control algorithms without translating the
design into real hardware, which is very useful for complex control systems.
Table 4.4: Comparison of resource utilization between VHDL and XSG
implementations for four-unit motors with the proposed time-division
multiplexing scheme
Hardware implementation VHDL System generator
Occupied Slices 6994 (47%) 9878 (66%)
CLB Flip Flops 7038 (23%) 8475 (28%)
4 input LUTs 11884 (40%) 17624 (59%)
MULT18X18 ISOs 29 (80%) 29 (80%)
Max. operating frequency 50.203 MHz 50.186 MHz
A comparison of chip costs between low-cost and high performance Xilinx
FPGAs (in 2014) suitable for this implementation is shown in Table 4.5. For a
consideration of a low-cost technology of MCUs, nowadays modern MCUs integrated
with sophisticated peripherals on chip can fulfill control requirements with large enough
bandwidth for a single or two-unit motor drive with vector control algorithm [76],[77].
However, considering multi-motor control systems, the use of commercial MCUs has
two major technological limitations, including the limitation of computation bandwidth
and the limitation of dedicated PWM peripherals. The use of multiple MCUs degrades
the system integration and increases the board layout. By this reason, a low-cost FPGA
solution is considered for multi-motor control system in this thesis. A comparative study
between low-cost FPGAs and MCUs suitable for the studied implementation is shown
in Table 4.6. It can be seen that the four-unit motor control system using a low-cost
FPGA can outperform over MCU-based controllers in term of computation speed of
7.08 μs at 50 MHz clock frequency. Thus, it can be mentioned that when considering
the system containing a larger number of controlled motors (e.g., more than four motor
units), the incremental system cost for low-cost FPGAs is comparable with multi-unit
MCUs solution whereas low-cost FPGAs can deliver better computation performance
with system integration on a single chip.
Table 4.5: Comparison of chip costs between low-cost and high performance
Xilinx FPGAs suitable for this implementation
Platform Low-cost FPGAs High performance FPGAs
Family Spartan-3E
XC3S1600E
Spartan-3E
XC3S1600E
Virtex-4
XC4VFX60
Virtex-5
XC5VLX155
Number of FPGA Chip 1 4 1 1
Package 320FBGA 4 of 320FBGA 672FCBGA 1136FCBGA
Occupied Slices 14752 4 of 14752 25280 24320
CLB Flip Flops 29504 4 of 29504 50560 97280
Dedicated multipliers 36 4 of 36 128 128
Commercial price
(USD) ≈ 67 ≈ 268 ≈ 856 ≈ 2671
Information obtained from: http://www.xilinx.com and http://www.digikey.com
100
Table 4.6: Comparison of chip costs between commercial MCUs and a low-cost
Xilinx FPGA suitable for this implementation
Platform MCU [76] MCU [77] FPGA (Proposed)
Model series MK40DX256
Cortex-M4
TMS320
F28069F
Spartan-3E
XC3S1600E
Computation time (μs) 63 28 7.08 (37.1)*
PWM peripheral unit 1 2 -
Number of required chips 4 2 1
Cost per chip (USD) 11.39 21.3 67
Total system cost (USD) ≈ 45.56 ≈ 42.6 ≈ 67
Note: * indicates the value in parentheses obtained from the implementation with
the analog multiplexer.
4.5 Speed synchronization performance of a cross-coupling multi-motor drive
system
In this section, in order to evaluate the control performance of the proposed
single chip system with cross-coupling control scheme, a comparative study between a
conventional independent control and the relative-coupling control scheme has been
performed. For this experiment, four PMSM motors (PMSM1 to PMSM4) are running
at the same speed of 1200 rpm, then PMSM1 is disturbed with two step load changes,
firstly a load torque of 0.12 Nm is applied at t = 0.8 s, and secondly a load torque of
0.12 Nm is removed at t = 3.3 s. Figure 4.9 and Figure 4.10 show a comparison of
dynamic speed responses and speed synchronization errors between a conventional
control scheme and the cross-coupling control scheme for four-unit motor drive system,
respectively. The experimental results confirm that a single chip cross-coupling drive
system with time-division multiplexing scheme can provide good disturbance rejection
with less speed synchronization error compared to a conventional control scheme.
For the latency analysis of a single-motor system, the current acquisition using
the ADCs requires 204 clock cycles, the computational blocks for motor controller
(Clark and Park transformations, current and speed PI controllers) take 38 clock cycles,
and the SVPWM module needs 58 clock cycles. Thus, the whole algorithm execution
requires a total of 300 clock cycles, meaning 6 μs at 50 MHz clock rate. For a
four-motor system, the time-division multiplexing scheme introduces more
computational time for running different control algorithms sequentially on the same
hardware structure. In this thesis, the proposed four-motor system with time-division
multiplexing takes a total computation time of 7.08 μs (37.1 μs when implemented with
analog multiplexers), which is much less than the sampling interval of the inverter,
62.5 μs (16 kHz), and hence does not affect the control performance of the overall
system. Figure 4.11 shows a comparison of speed response between a single-motor
system and the proposed four-motor system with time-division multiplexing. The
experimental results confirm that the proposed system with time-division multiplexing
can operate effectively with the same control performance comparing with a
single-motor system. Often, the computation time required for one motor is much lower
than the switching period of the inverter. This condition implies that several control
algorithms can be either allocated in sequential manner as a pipelining operation, or
executed in a series of cycles as a time-division multiplexing, as shown in Figure 4.12.
From the viewpoint of control performance, the proposed four-motor system with
101
time-division multiplexing can permit and extend the operation at higher maximum
inverter switching frequency (up to 141 kHz), which is applicable for a high-bandwidth
speed and torque control system.
0 1 2 3 4 5400
800
1200
1600
2000
0 1 2 3 4 5400
800
1200
1600
2000
Figure 4.9: Experimental results showing dynamic speed responses during load
disturbances applied to PMSM1: (a) Conventional control scheme;
(b) Cross-coupling control scheme
0 1 2 3 4 5-500
-250
0
250
500
0 1 2 3 4 5-500
-250
0
250
500
Figure 4.10: Experimental results showing speed synchronization error:
(a) Conventional control scheme; (b) Cross-coupling control scheme
Time (s)
Sp
eed
syn
chro
niz
atio
n e
rro
r (r
pm
)
(a)
(b)
TL=0.12 Nm
Time (s)
Sp
eed
(rp
m)
PMSM1 TL=0 Nm
(b)
Sp
eed
(rp
m)
PMSM1
TL=0.12 Nm
TL=0 Nm
(a)
PMSM2
PMSM3
PMSM4
PMSM2
PMSM3
PMSM4
102
0 1 2 3 4 5500
1000
1500
2000
Single-motor system
Proposed system with time-division multiplexing
Figure 4.11: Experimental results showing a comparison of speed responses
between a single-motor system and the proposed four-motor system with time-
division multiplexing during step load changes
Tsw= TPWM = 62.5 μs
Time
6 μs
(a)
nTsw (n+1)Tsw
(b)
Time
Ttotal = 7.08 μs
TCLK = 2x10-8
sMotor 1 to 4
Motor 1
Motor 2
Motor 3
Motor 4
Motor 1 - 4
Ttotal = 24 μs
Motor 1
Motor 2
Motor 1 - 4
Figure 4.12: Comparison of the system-timing diagram for the proposed four-
motor control system: (a) Single module with pipelining; (b) Single module with
time-division multiplexing
A comparison of resource utilization on a XCS1600E FPGA for controlling a
single-unit and four-unit PMSM motor drive system is summarized in Table 4.7. For
single-unit motor system, the motor controller module utilizes 39 % of occupied slices,
20 % of CLB flip flops, 34% of LUTs, and 80% of embedded multipliers available on
the chip. It can be seen that due to a limited number of dedicated multipliers available in
the FPGA target, it is not possible to fit four identical controller modules into a single
device. By considering for four-unit motor system, the proposed single chip solution
with time-division multiplexing scheme can simplify the entire system into a single
hardware module, which improves significantly the total resource utilization. The area
performance analysis shows that the total occupied resources for the entire system with
time-division multiplexing approach are perfectly fitted for a single chip target. The
overall system consumes 82% of occupied slices, 43 % of CLB flip flops, 77% of
LUTs, and 80% of embedded multipliers of available resources.
Time (s)
Sp
eed
(r
pm
)
103
Table 4.7: Comparison of resource utilization for a single-unit and for a four-unit
PMSM motor drive system
Unit of
motors
Hardware design
approach
Occupied
Slices (%)
CLB Flip
Flops (%)
4 input
LUTs (%)
MULT18X18
ISOs (%)
1 Single module 39 20 34 80
4
Four identical
modules Insufficient resources
Single module with
time multiplexing 82 43 77 80
104
CHAPTER 5
CONCLUSIONS AND RECOMMENDATIONS
5.1 Conclusions
The work described in this thesis has been concerned with a single chip
FPGA-based solution for independent control of a multi-unit PMSM motor drive system
with SVPWM-based vector control scheme. An area-efficient design method based on
system-level time-division multiplexing is proposed in order to minimize the resource
requirements of the control algorithm. The proposed solution with time-division
multiplexing can simplify the entire system into a single hardware module, improving
significantly the total resource utilization. For FPGA realization, the circuit design of
motor controller modules with the proposed time multiplexing scheme is described. In
order to validate the proposed method, a case study of four-unit motor control system is
demonstrated. The experimental results confirm that a multi-motor drive system using a
low-cost FPGA based on the proposed method can operate simultaneously with
robustness under different operating conditions while maintaining the aspect of system
integration and cost effectiveness.
For the application of multi-motor control systems, this thesis has presented a
fully integrated single chip solution for a cross-coupling multi-motor control system
applicable for steel rolling process. The proposed single chip solution has been
implemented with the concept of time-division multiplexing approach and hardware
solution using analog multiplexers in order to make the entire system possible to realize
on a single device. A case study of a four-unit motor drive system with cross-coupling
control scheme has been demonstrated. The experimental results confirm that the
proposed single chip control system can successfully operate a group of multiple
motors, whereas multi-motor controller modules can transmit processing data to each
other internally within the same chip.
5.2 Recommendations
Although the results presented in this thesis have demonstrated the effectiveness
of the proposed system-level time-division multiplexing scheme applicable for
multi-motor control system, the proposed method could be further developed in a
number of ways. The following recommendations are listed for related research in the
field of a FPGA-based multi-unit control system as follows.
It is possible to extend the proposed approach to multi-motor control systems
with a larger number of motor unit or to other industrial multi-unit control
systems, whereas the maximum number of motors depends on the following
factors: (1) The complexity of control algorithms; (2) The resource architecture
of FPGA device; (3) The number of latency or clock cycle for motor controller
module; and (4) The number of FPGA board I/O pins.
The proposed approach can be modified to support high speed multi-motor
systems. In this thesis, the motor drive system can operate four motors up to the
speed of 3,000 rpm with an inverter switching frequency of 16 kHz. Since the
total computation time of the system of 7.08 μs, it is much lower than the
105
switching period of the inverter of 62.5 μs. This implies that the proposed
time-division multiplexing method allows the system to extend the operation to
a higher inverter switching frequency, which can be useful for high speed motor
control applications.
It is interesting to extend the proposed approach for a multi-motor system with
different machine sizes or different control complexities, by using only a single
hardware structure with appropriate timing organization, and also sharing some
common functional-equivalent modules.
The proposed approach can be extended to more complex control systems, in
order to accomplish control performance improvement, such as sensorless
control, adaptive fuzzy logic control, neural network-based speed control, torque
distribution control, cross-coupling method with predictive control, and control
with extended Kalman filter. An application of this system could be, for
example, a four-wheel drive for electric vehicles, using PMSM motors.
106
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111
Appendix A
PMSM motor specifications and parameters
112
Table A-1: PMSM motor specifications
Manufacturer
Shenzhen Tiger Motion
Control Technology
Co., Ltd
Model TGSM-060R10B30M2N
Type
AC radial flux permanent
magnet synchronous
(RFPM) motor
Insulation class F (155 ˚C)
Cooling Air cooling
Stator winding connection Star
Power (W) 100
Rated speed (rpm) 3000
Rated torque (Nm) 0.318
Rated voltage (V) 36
Rated current (A) 4
Frequency (Hz) 200
Number of poles 8
Weight (kg) 0.84
Table A-2: Simulation parameters of the PMSM motor
Parameter Value
Stator resistance (Rs) 0.3731
Back EMF constant (kE) 5.4038 V/krpm
Permanent magnet flux linkage (m) 0.010535 V·s
Direct-axis inductances (Ld) 1.683 mH
Quadrature-axis inductances (Lq) 2.041 mH
Moment of inertia (J), 1.034x10-5
kg·m2
Friction damping coefficient (B) 1.349x10-6
Nm·s
Table A-3: Simulation parameters of the three-phase inverter with SVPWM
technique
Parameter Value
DC bus voltage (VDC) 36 V
Switching frequency (fs) 16 kHz
113
Appendix B
Lists of components and datasheets
114
Table B-1: Lists of components
No. Component Manufacturer/ Part Number Quantity
1 100 W PMSM motors
Tiger Motion Control
Technology/
TGSM-060R10B30M2N
4
2 Xilinx Spartan 3E-1600 FPGA
development board Digilent/ 410-1008P-KIT 1
3 Three-phase IGBT-based
intelligent power module Mitsubishi/ PM30CSJ060 4
4 ADC PmodeAD1 converter
module Digilent/ 410-064P-KIT 3
5 Analog-to-Digital converter
AD7476 Analog Device/ AD7576 See No. 4
6 DAC PmodDA2 converter
module Digilent/ 410-113 2
7 Digital-to-Analog converter
DAC121S101
National Semiconductor/
DAC121S101 See No. 6
8 FX2 module interface board Digilent/ 210-161P 1
9 Analog multiplexer MAX4618 Maxim Integrated/ MAX4618 1
10 AC current sensor
(-30A to +30A) Pololu/ ACS714 4
11 Current sensor ACS714 Allegro/ ACS714 See No. 10
12 DC voltage and DC current
sensor (90A and 51.8 V) Sparkfun/ AttoPilot - 90 A 1
13 Current shunt monitor INA139 Texas Instruments/ INA139 See No. 12
14 Hex schmitt trigger CD40106BC National Semiconductor/
CD40106BC 2
15 Hex schmitt trigger inverters
SN74LS14 Texas Instruments/ SN74LS14 2
16 Quadruple differential line
receiver AM26C32 Texas Instruments/ AM26C32 4
17 Octal bus transceiver
SN74LVC245
Texas Instruments/
SN74LVC245A 4
18 Dual 4-input AND gate
74HCT21N
Philips Semiconductor/
74HCT21N 1
19 High CMR, high speed
optocouplers HCPL-4504
Avago Technologies/
HCPL-4504 6
20 Photocoupler PC817 Sharp/ PC817 17
115
Table B-2: FPGA pin connection
Pin Name FPGA Pin Connected To
Pin Name FPGA Pin Connected
To
CS1 B4 ADC1 A1_ENC A8 ENCODER1
DATAIN1A D5 ADC1 A2_ENC G9 ENCODER2
DATAIN1B A6 ADC1 A3_ENC A7 ENCODER3
SCLK1 E7 ADC1 A4_ENC D13 ENCODER4
CS2 A4 ADC2 B1_ENC E6 ENCODER1
DATAIN1C C5 ADC2 B2_ENC D6 ENCODER2
DATAIN1D B6 ADC2 B3_ENC C3 ENCODER3
SCLK2 F7 ADC2 B4_ENC C15 ENCODER4
SYNC1 F11 DAC1 PWM1_A D7 PWM1_A
DATAOUT2A E12 DAC1 PWM1_B F8 PWM1_B
DATAOUT2B A13 DAC1 PWM1_C F9 PWM1_C
SCLK3 A14 DAC1 PWM1_OC D11 PWM1_OC
SYNC2 E11 DAC2 PWM2_A C7 PWM2_A
DATAOUT2C F12 DAC2 PWM2_B E8 PWM2_B
DATAOUT2D B13 DAC2 PWM2_C E9 PWM2_C
SCLK4 B14 DAC2 PWM2_OC C11 PWM2_OC
A_MUX C14 AMUX PWM3_A N15 PWM3_A
B_MUX A16 AMUX PWM3_B N14 PWM3_B
EN_MUX E13 AMUX PWM3_C E15 PWM3_C
CS_FAULT B11 LED PWM3_OC V7 PWM3_OC
IGBT_FAULT D14 LED PWM4_A V5 PWM4_A
UV_FAULT B16 LED PWM4_B V6 PWM4_B
ENABLE D13 SL_SWITCH PWM4_C N12 PWM4_C
ROTARY_A K18 ROTARY_SW PWM4_OC P12 PWM4_OC
ROTARY_A G18 ROTARY_SW LCD_E M18 LCD
ROTARY_P V16 ROTARY_SW LCD_RS L18 LCD
UP V4 P_BUTTON LCD_RW L17 LCD
RESET K17 P_BUTTON SF_CE0 D16 LCD
BACK D18 P_BUTTON SF_D<0> M16 LCD
ENTER H13 P_BUTTON SF_D<1> P6 LCD
RX R7 RS-232 SF_D<2> R8 LCD
TX M14 RS-232 SF_D<3> T8 LCD
116
Figure B-1: Datasheet of the 100 W PMSM motors
117
Figure B-2: Datasheet of the Xilinx Spartan 3E-1600 FPGA development board
118
Figure B-3: Datasheet of the three-phase IGBT-based intelligent power module
119
Figure B-4: Datasheet of the ADC PmodAD1 converter module
120
Figure B-5: Datasheet of the analog-to-digital converter AD7476
121
Figure B-6: Datasheet of the DAC PmodDA2 converter module
122
Figure B-7: Datasheet of the digital-to-analog converter DAC121S101
123
Figure B-8: Datasheet of the analog multiplexer MAX4618
124
Figure B-9: Datasheet of the current shunt monitor INA139
125
Figure B-10: Datasheet of the hex schmitt trigger CD40106BC
