Controller design by R.L. Typical setup: C(s)G(s) Controller Design Goal: 1.Select poles and zero of C(s) so that R.L. pass through desired region 2.Select

Controller design by R.L.Typical setup:

C(s) G(s)

01

1

1

sd

sn

ps

zsK

sdsn

sG

21

21)(psps

zszsKsC

Controller Design Goal: 1.Select poles and zero of C(s) so that R.L. pass through desired region2.Select K corresponding to a good choice of dominant pole pair

Types of classical controllers• Proportional control

– Needed to make a specific point on RL to be closed-loop system dominant pole

• Proportional plus derivative control (PD control)– Needed to “bend” R.L. into the desired region, when RL does not

• Lead control– Similar to PD, but without the high frequency noise problem; max angle

contribution limited to < 75 deg

• Proportional plus Integral Control (PI control)– Needed to “eliminate” a non-zero steady state tracking error

• Lag control– Needed to reduce a non-zero steady state error, no type increase

• PID control– When both PD and PI are needed, PID = PD * PI

• Lead-Lag control– When both lead and lag are needed, lead-lag = lead * lag

Proportional control design

1. Draw R.L. for given plant

2. Draw desired region for poles from specs

3. Pick a point on R.L. and in desired region• Use ginput to get point and convert to complex #

4. Compute

5. Obtain closed-loop TF

6. Obtain step response and compute specs

7. Decide if modification is needed

01sd

snK

DPGsGK

11

nump=…; denp= …; sysp=tf(nump, denp); rlocus(sysp);

use your program from several weeks ago to do all these

syscl = feedback(sysc*sysp,1);

Gpd=evalfr(sysp,pd);K=1/Gpd;sysc = K;

[x,y]=ginput(1); pd=x+j*y;

Design steps:

1. From specs, draw desired region for pole.Pick from region, not on RL

2. Compute

3. Select

4. Select:

dd jp dpG dd pGzpz s.t.

dd pGz tan i.e.

DP

ddD

KzKpGzp

K1

Gpd=evalfr(sysp,pd)phi=pi - angle(Gpd)

z=abs(real(pd))+abs(imag(pd)/tan(phi));

Kd=1/abs(pd+z)/abs(Gpd);Kp=z*Kd;

PD controller design


Lead Control:

1. Draw R.L. for G2. From specs draw region for desired c.l.

poles3. Select pd from region

4. LetPick –z somewhere below pd on –Re axisLetSelect

dd jp

dpG

121 ,zpd 2 s.t. ppp d 2tan i.e. dp

• Approximation to PD• Same usefulness as PD

0

zpps

zsKsC

dd

d

dpdp

zdp pGzp

pp

pGK

1Let

ps

zsKsC

:is controllerYour

[x,y]=ginput(1); z=abs(x);phi1=angle(pd+z); phi2=phi1-phi;



p=abs(real(pd))+abs(imag(pd)/tan(phi2));

K=abs((pd+p)/(pd+z)/Gpd);

sysc=tf(K*[1 z],[1 p]);Hold on;rlocus(sysc*sysp);

Lead Control with angle bisector1. Draw R.L. for G2. From specs draw region for desired c.l.

poles3. Select pd from region

4. Let

Select

dd jp

)(),( dpd ppGd

2222 21

dd pp

21 tan;tan dd pz

dd

d

dpdp

zdp pGzp

pp

pGK

1

ps

zsKsC

:is controllerYour

phipd=angle(pd);phi1=(phipd+phi)/2; phi2=phi1-phi;

p=abs(real(pd))+abs(imag(pd)/tan(phi2));

z=abs(real(pd))+abs(imag(pd)/tan(phi1));

K=abs((pd+p)/(pd+z)/Gpd);

sysc=tf(K*[1 z],[1 p]);Hold on;rlocus(sysc*sysp);



Lag controller design

• It has “destabilizing” effect (lag)

• Not used for improving MP, tr, …

• Use it to improve ess• Use it when R.L. of G(s) go through the

desired region but ess is too large.– First select K, as in proportional control– Select z, p so that z/p>1, ess*p/z = ess_des

,s z

C s K z ps p

Lag Design steps

1. Draw R.L. for G(s).

2. From specs, draw desired pole region

3. Select pd on R.L. & in region

4. Get

5. With that K, compute error constant(Kpa, Kva, Kaa) from KG(s)

6. From specs, compute Kpd, Kvd, Kad

dpGK

1

Kdes = 1/ess; sysol = sysc*sysp;[nol, dol]=tfdata(sysol,'v');dn0=dol(dol~=0); Kact=nol(end)/dn0(end);

P

7. If Kact > Kdes , done

else: pick

8. Re-compute

9. Closed-loop simulation & tuning as necessary

20~5

Re dpz

act

des

Kp z

K

1

p zddp pd

KG p

z=-real(pd)/…;

p=z*Kact/Kdes/(1+…);

0.05 or 0.1

K from 8 should be ~1, so 8 is normally skipped.

5~20

Example:

Want:

Solution:

%161 PM

sec5,sec202 rs tt

0step to3 sse2.0ramp to sse

5.0%16 PM

36.0sec5 nrt

C(s)1

( 1)( 2)s s s

2.0sec20 st

• Draw R.L., and region for desire pole

• Pick pd on R.L. & in Regionpick pd = – 0.35 + j0.5

•

• Since there is one in G(s)

86.01

211

ddd

d

ppp

pGK

s

1

0step to,1Type sse

vss Ke

1ramp to

2.0:Desired sse

52.0

1 vdK

:have What we ssKGK

sva

0lim

43.021

186.0lim

0

ssss

s

07.0

5

35.0RePick

dpz

006.05

43.007.0 p

-1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

0.94

0.985

0.160.320.480.620.760.86

0.94

0.985

0.20.40.60.811.21.4

0.160.320.480.620.760.86

Root Locus

Real Axis

Imag

inar

y A

xis

: compute-Re K

914.0

1

dpdp

zdp pGK

Simulation : 27%PM

2.8 5 ,

28 20r

s

t s s

t s s

0 10 20 30 40 50 60 700

0.2

0.4

0.6

0.8

1

1.2

1.4

Time (sec)

Am

plit

ud

eUnit Step Response

ts=28.1 tp=6.46

Mp=27.2%

ess tolerance band: +-2%

td=2.77

tr=2.77

yss=1

ess=0

New root locus: RL going north-east, reduce K will increase and and increase

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

0.78

0.94

0.080.160.250.360.480.62

0.78

0.94

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

0.080.160.250.360.48

0.62

Root Locus

Real Axis

Imag

inar

y A

xis

Use original K=0.86 instead of 0.914; ess should be OKVirtually no change to step response. No need to re-compute K.

0 10 20 30 40 50 60 700

0.2

0.4

0.6

0.8

1

1.2

1.4

Time (sec)

Am

plit

ud

eUnit Step Response

ts=28.8 tp=6.96

Mp=26.1%


td=2.78

tr=2.78

yss=1

ess=0

0 10 20 30 40 50 60 70 800

0.2

0.4

0.6

0.8

1

1.2

1.4

Time (sec)

Am

plit

ud

eUnit Step Response

ts=42.1 tp=6.94

Mp=15.8%ess tolerance band: +-2%

td=2.78

tr=2.78

yss=1

ess=0

Change that divide # from 5 to 15.

0 10 20 30 40 50 60 70 800

0.2

0.4

0.6

0.8

1

1.2

1.4

Time (sec)

Am

plit

ud

eUnit Step Response

ts=10.6 tp=6.94

Mp=15.8%ess tolerance band: +-5%

td=2.78

tr=2.78

yss=1

ess=0

ans =

yss=1; ess=0; tr=2.78; td=2.78; ts=10.6; tp=6.94; Mp=15.8

Lead-lag design example

Too much overshoot, too slow & ess to ramp is too large.

984.125.0at poles loop-closed ,1With jsC

125.0

C(s) Gp(s)R(s) E(s) Y(s)U(s)

)5.0(

4)(

sssGp

0 5 10 15 20 250

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Time (sec)

Am

plit

ud

e

Unit Step Response

ts=14.6 tp=1.57

Mp=67.3%


td=0.628

tr=0.628

yss=1

ess=0

%16 :Want pMsec36.0rt

%2ramp to sse

5.0%16 :Sol pM

cone 60 i.e.

58.1

sec36.0 r

nr tt

%21

%2 vd

ss Ke

50let vdK 1 Type

Draw R.L. for G(s) & the desired region

3.45.2 jpd

Clearly R.L. does not pass through desired region.

need PD or lead.

Let’s do lead.Pick pd in region

3.43 picked have could j

3.45.2 jpd

: Compute

Now choose zlead & plead.

Could use bisection.Let’s pick zlead to cancel plant pole s

+ 0.5

dpG 235

55235180

5.0let leadz

Use our formula to get plead

Now compute K :

Now evaluate error constant Kact

021.5leadp

26.6

1

dlead

lead

pspszs sG

K

0

lim leadact

slead

s zK sK G s

s p

spss leadKs

41

0lim

021.526.644

leadpK

4 6.265.021 50 0.1act

des

KK

20~5

5.2

20~5

RePick

d

lag

pz

2.0Pick lagz

02.0then vd

valaglag K

Kzp

Could re-compute K, but let’s skip:

do step response.

02.0

2.0

021.5

5.026.6

s

s

s

ssC

02.0021.5

2.026.6

sss

ssGsC

2.026.602.0021.5

2.026.6..

ssss

ssGc

-6 -4 -2 0 2-5

0

50.8

0.91

0.975

0.140.280.420.560.680.8

0.91

0.975

123456

0.140.280.420.560.68

Root Locus

Real Axis

Imag

inar

y Ax

is

0 0.5 1 1.5 20

0.2

0.4

0.6

0.8

1

1.2

1.4Step Response

Time (sec)

Am

pli

tud

e

0 0.5 1 1.5 20

0.2

0.4

0.6

0.8

1

1.2

1.4Step Response

Time (sec)

Am

pli

tud

e

005.0

05.0

02.0

2.0

:from Lag Changing

s

ssC

tos

ssC

• Lag control can improve ess, but cannot totally eliminate ess

• Use PI control to eliminate ess

• PI : s

sKK

sKKsC PIIP

1

s

sK

s

zsK I

IP

1

P

I

K

Kz :where

zK

K

I

PI

1

PI Controller

, , 0

1 1( )

IP P I

I P

KC s K K K

s

K K s PDs s

, , 0, 0s z

C s K K z ps p

A PI controller can also be viewed as a Lag with p=0

PI controllers are used to get rid of a nonzero steady state error, by increasing the type by 1.

It has strong destabilizing effects.

First PI design (a special Lag design):

1. Draw R.L. for G(s)

2. From specs, draw desired region

3. Pick pd on R.L. & in region

4. i. Choose

ii. Choose

5.

6. Simulate & tune

20~5

Re dpz

sGs

zssz

0s

lim s.t. tsrequiremen meets sse

PI

pss

zsP KzKsG

K

d

,

1

PI Design steps

Alternative PI design• Since PI = PD/s,

• Can first multiply system by 1/s

• Then design using PD

• The overall controller is the controller you designed divided by s

Overall controller design

1. Draw R.L. for G(s), hold graph

2. Draw desired region for closed-loop poles based on desired specs

3. If R.L. goes through region, pick pd on R.L. and in region. Go to step 7.


4. Pick pd in region (near corner but inside region for safety margin)

5. Compute angle deficiency:

6. a. PD control, choose zpd such that

then

dpG

pdd zp

pdzssC

6. b. Lead control: choose zlead, plead such that

You can select zlead & compute plead. Or you can use the “bisection” method to compute z and p.

Then

leadd

leadd

pp

zp

lead

lead

ps

zssC

If < 60~70 deg, a single stage of PD or lead will work.If > 80~90 deg, use a two-lead or PD-lead controller.

7. Compute overall gain:

8. If there is no steady-state error requirement, go to 14.

9. With K from 7, evaluate error constant that you already have:

dps

sGsCK

1

0

lim Na

sK s KC s G s

avp ,,

2,1,0

The 0, 1, 2 should match p, v, a

This is for lag control.

For PI:

s

zssGsCKsK pi

sa

*lim0

control. PI theis wheres

zs pi

10.Compute desired error const. from specs:

11.For PI : set K*a = K*d & solve for zpi

For lag : pick zlag & let

advdpdss KKKe

1or ,

1or

1

1

d

alaglag K

Kzp

lag

lagpi

ps

zs

s

zssC

or

12.Re-compute K (this step may be unnecessary)

13. 14.Get closed-loop T.F. Do step

response analysis.15.If not satisfactory, go back to 3

and redesign.

dps

sGsCsCK

1

sCsCKsC

If we have both PI and PD we have PID control:

s

zszsK

s

KsKKsC

pipd

IDP

)(

KKD :where

pipdP zzKK

pipdI zKzK

If we have both Lead and Lag, we have lead-lag control:

lag

lag

lead

lead

ps

zs

ps

zsKsC

lead lead

lag lag

lead lead lag lag

where: z 0

p 0

z p

p

z

p z

Control System Implementation


Controller Actuator

ReferenceCommand error

outputcontrol

Plant

Sensor

disturbanceinput

noise

+ _ plantinput

PC-in-the-loop Control

PowerAmp

Actuator

ReferenceCommand output

Plant

Sensor

disturbanceinput

A/D

D/APC

I/OI/O

All control algorithms implemented in PC (could be Matlab Real-Time)

Needs data acquisition system, including A/D and D/A

Needs power amplifier

Signal conditioner

and amplifier

-Controller based control

PowerAmp

Actuator

ReferenceCommand output

Plant

Sensor

disturbanceinput

-Controller I/O

I/O

Very similar architecture to PC-in-the-loop control

All control algorithms implemented in -controller

-controller has its own A/D and D/A, but make sure resolution is OK

Still needs power amplifier, because -controller outputs weak signal

Signal conditioner

and amplifier

Power electronic based control

Op Ampcircuit

Actuator

ReferenceCommand

outputPlant

Sensor

disturbanceinput

Differenceamplifier

Analog operation, fastest

Inexpensive

All algorithms in circuit hardware

Op Amp circuits for various controllers are given in book

No sampling and aliasing issues

Documents

Controller design by R.L. Typical setup: C(s)G(s) Controller Design Goal: 1.Select poles and zero of C(s) so that R.L. pass through desired region 2.Select