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TET4190 Power Electronics for Renewable Energy
Topic No. 16
Control of Permanent Magnet Synchronous Generator Interfaced to the Grid
Group 8:
Valter Colaço ([email protected])
Michael Kramer ([email protected])
Kenneth Tjong ([email protected])
Dmitrij Tschechonadskij ([email protected])
Contact person: Rabah Zaimeddine ([email protected])
i
Table of Contents
Table of Contents ........................................................................................................................................................................... i!
Table of Figures ........................................................................................................................................................................... ii!
1.!"""""!Introduction ......................................................................................................................................................................... 1!
1.1.! Problem 1!
1.2.! Approach 1!
2.!"""""!Back-to back Converter .................................................................................................................................................... 2!
2.1.! Two-level three-phase Inverter 2!
2.2.! Three-level three-phase NPC Converter 3!
2.3.! Comparison of a two and a three-level three-phase NPC Converter 5!
3.!"""""!Modulation techniques ...................................................................................................................................................... 6!
3.1.! Pulse Width Modulation (PWM) 6!
3.2.! Space Vector Modulation (SVM) 8!
4.!"""""!Capacitor unbalance and simulation ............................................................................................................................ 10!
4.1.! Capacitor unbalance 10!
4.2.! Simulation in MATLAB/SIMULINK 11!
4.2.1.! Basic setup 11!
4.2.2.! Simulation results 11!
4.2.3.! Conclusion 14!
References ..................................................................................................................................................................................... iii!
Appendix ....................................................................................................................................................................................... iv!
ii
Table of Figures
Figure 1: The two-level three-phase Inverter 2!
Figure 2: Output-voltages in the two level inverter 2!
Figure 3: The three level phase NPC Converter 3!
Figure 4: One leg of a two-level back-to-back inverter 3!
Figure 5: One leg of a three-level back-to -back inverter 3!
Figure 6: Output-voltages in the three level inverter 4!
Figure 7: Switching states of one leg in the three-level inverter 5!
Figure 8: The PWM, from the inverter in our simulation. 6!
Figure 9: Operation modes in a three-phase two-level inverter 7!
Figure 10: Switching states of a three level converter 8!
Figure 11: Switching The 19 distinctive space –vectors for a 3-level converter 8!
Figure 12: Switching state 9!
Figure 13: VREF constructed by three switching states 9!
Figure 14: The DC bus 10!
Figure 15: The gate signals for the transistors in one leg 12!
Figure 16: The neutral point current 12!
Figure 17: The capacitor voltages 13!
Figure 18: The voltage across the DC-bus 13!
Figure 19: Inverter three phase output to the grid 14!
1
1. Introduction
1.1. Problem
To integrate renewable energy sources like wind power into the utility grid, the connection of two
different frequencies at the source and the load side must be taken in account. Variable speed wind
turbines like the synchronous generator or the doubly-fed induction generator require a converter to
achieve grid frequency. Here the most chosen converter structure is the back-to-back three-level
Neutral-Point-Clamped (NPC) Voltage Source Converter (VSC). The converter allows the direct
connection between the generator and a grid of medium voltage without a transformer [1].
The project deals with the simulation of the back-to-back three-level NPC converter control and
shows the existing voltage unbalance in the DC-bus. Due to the possibility of overvoltages in the
circuit and the worsening of the quality of the currents regarding the load side, it is one of the main
goals to delimit the neutral-point current and to keep the capacitor voltages balanced [1]. So beside
a modulation technique and its switching strategy [2], it is necessary to extend the converter by for
example additional resistors [1] or a buck-boost converter to balance the DC-bus capacitor voltages.
1.2. Approach
Initially the two-level three-phase inverter and subsequently the three-level inverter will be intro-
duced for the basic understanding. After the presentation of their circuit buildups, switch states and
output-voltages, a short comparison between the inverters will be given. In a second step the Pulse-
With-Modulation (PWM) and the Space-Vector-Modulation (SVM) are introduced.
In the next step, the basic equations for the DC-bus unbalance are derived. With this background it
is then possible to verify the capacitors voltage unbalance in a MATLAB/SIMULINK simulation.
After a basic explanation of the simulation model a descriptional explanation of the measured outputs
will be given.
2
2. Back-to back Converter
2.1. Two-level three-phase Inverter
The two-level three phase inverter circuit shown in Fig. 1 consists of three similar legs, one for every
ac-phase. There are two IGBTs per leg which are always in an opposite switching position (state “1”
for upper switch on and state “0” for the lower switch on.) Under these conditions for every leg, there
are 2!=8 possible switching states. The output-voltages !!!!,!!!!!,!!!!! only depend on the dc-
voltage Vdc/2 and the switch states [4].
Figure 1: The two-level three-phase inverter [6]
For example the state (1,0,0) describes the switches T11, T22 and T32 on and the other switches off.
The following voltages result:
!!!!= Vdc/2 !!!!!= -Vdc/2 !!!!= -Vdc/2
!!!!= !!!!-!!!!!=Vdc !!!!= !!!!!- !!!!=0 !!!!= !!!!- !!!!=-Vdc
Hence, depending on the time remained in one state, the following voltage-waveforms occur.
Figure 2: Output-voltages in the
two level inverter[3]
3
2.2. Three-level three-phase NPC Converter
Figure 3: The three level phase NPC Converter [2]
In lot of modern, large converters, three–level three-phase back-to-back converters are being used. A
three-level converter is based on the same philosophy as the 2-level converter, with another level of
commutation. A three-level back-to-back converter has an equal rectifier and an inverter part. Where
the two-level back-to-back converter has an IGBT in parallel with a diode for each leg, the three-
level has added another parallel diode and IGBT in series.
As seen in Fig. 3 the three-level converter has a neutral point, which is connected to a common point
between each parallel IGBT and diode. The adding of the two extra IGBT and diodes for each leg
gives it the ability to have one more commutation per phase, and thereby generating a voltage with
less ripple, which is a better approximation of a sinusoidal wave which can be seen in Fig. 6[3].
Figure 5: One leg of a two-level
back-to-back inverter [2]
Figure 4: One leg of a three-
level back-to -back inverter [2]
4
Figure 6: Output-voltages in the three level inverter [3]
The switching steps are:
I: Positive voltage from phase A: T11 and T12 are closed
and D11 and D12 are conducting. The voltage !!!!"
equals !!"!! during this step.
II: Zero voltage from phase A: T12 and T13 are closed and
D12 and D13 are conducting. The voltage !!!!" equals 0
during this step.
5
III: Negative voltage from phase A: T13 and T14 are closed and
D13 and D14 are conducting. The voltage !!!!" equals !!!"!!
during this step.
The introduction of a neutral-point between two capacitors
(DC-link) makes it possible to double the DC-voltage, and hence
the output voltage.
2.3. Comparison of a two and a three-level three-phase NPC Converter
In a lot of heavy duty applications the three-level back to back converter is often utilized. One of the
benefits of the three-level converter, compared to the two-level converter, is that the DC-voltage can
be doubled. The integration of a neutral point makes this feasible. With doubled DC-voltage for the
same capacitor size the output power can also be doubled – this makes the three-level converter very
favorable e.g. for large wind-turbines. In addition this is achieved without or with little extra hard-
ware for voltage and current sharing [5].
The three level converter has by its buildup 33=27 switching stages, while the two-level converter
has 8. Thereby the generated AC-voltage is much more sinusoidal, than the two-level. With less rip-
ples, the losses are reduced up to 25% for the same wave-form quality [6]. Passive components in
converters are normally a large and costly part of a converter. By reducing the harmonics, the three-
level converter can reduce the size of the filters compared with the two-level and hence the costs [5].
The three-level converter has about twice as many power-and control components than the two-level
converter. This makes the converter more complex and the converter has higher costs than the two-
level converter [5]. The active losses in the various components increase by the numbers of compo-
nents. With more active components, the controller for the three-level converter will be more com-
plex. The three-level converter utilizes two capacitors in series in the DC section. Even though the
two capacitors are engineered to be balanced, voltage-fluctuations will occur while charg-
ing/discharging the capacitors [5].
Figure 7: Switching states of
one leg in the three-level
inverter [6]
6
3. Modulation techniques
In order to achieve a sinusoidal output voltage controllable in magnitude and frequency a modulation
technique is required. In practice you can differ between the carrier based and space vector based
modulation techniques. In the following paragraph the two most common modulation techniques are
introduced.
3.1. Pulse Width Modulation (PWM) The carrier based Pulse Width Modulation (PWM) technique is in general based on a comparison of
a triangular high frequency carrier with a low frequency sinusoidal signal. This continuous compari-
son between a sinusoidal reference signal and each carrier assigned to a switch generates the PWM
signals to each switch. The switching states are defined as follows. If the reference signal !!"# is
larger than the carrier signal !!"# , the corresponding active device will switch on (!!"# > !!"# , on). If
the reference signal is smaller than the carrier signal, the corresponding active device switches off
(!!"# < !!"# , off)[7]. In Fig. 8 you can see the sinusoidal reference signal, the positive and the nega-
tive carrier signal, which are in phase to each other. In a three level inverter an additional carrier
signal is needed to establish the previously explained switching states in Fig. 7. Looking for example
on the first leg, the transistor
T11 will be switched as ex-
plained above, referring to
the positive carrier signal.
T13 will be switched re-
versely, the logical inverse of
T11. T12 has the same
switching condition as T11,
but with reference to the
negative carrier, thus is
switched on during the
whole first half-cycle of the
reference signal. T14 is the
logical inverse of T12.
Figure 8: The PWM, from the inverter in our simula-
tion.
7
The frequency of the triangular waveform !!"# sets the switching frequency !! of the inverter and is
kept constant over the time with its amplitude !!!"#. !!"# modulates the switch duty ratio by its am-
plitude. Its frequency !! is called the modulation frequency and is equal to the desired output fre-
quency of the inverter. The following terms characterize a PWM: The amplitude modulation ratio of
an inverter is defined as
!! ! !!!"#!!"#
where generally !!"# is kept constant. The frequency modulation ratio is defined as
!! ! !!!!!
[4].
As a function of !!, an inverter can operate in a linear
(!! ! !!, overmodulation (!! ! !) or square-wave region.
Fig. 9 shows the rms value of the line-to-line output voltages
fundamental frequency component !!!! in relation to the DC
input voltage depending on !! for a basic three phase inverter.
The ratio no longer increases linearly when the overmodulation
region is entered. As the ratio between !!"# and !!"# becomes
higher, the width of the switching pulses increases until finally
square-waves are generated. In the square-wave mode of opera-
tion the magnitude of the ac output can only be controlled by
varying the DC input voltage.
Figure 9: Operation modes in a
three-phase two-level inverter [4]
8
3.2. Space Vector Modulation (SVM)
One of the most common control-methods of a 3-level converter is the Space Vector Modulation
(SVM). SVM for a 3-level converter is utilizing 19 space vectors, which gives 27 switching states.
There are four different vector types, one zero voltage vector (ZV), four small voltage vector (SV),
four middle voltage vectors (MV) and three large voltage vectors (LV). The vectors indicate an area
where you have a desired voltage reference. Three different switching states can represent every
voltage sector [8].
Table 1(see Appendix A1) indicates 3 switching states for the zero-vector and for the small vectors.
This indicates that the converter has redundancy for these. There are also two states for each of the
small vectors. [8]
The switching state notations (P, O and N) refer to the pair of transistors for each leg. P corresponds
to the upper pair (positive voltage), O to the center pair (neutral voltage) and N to the lower pair
(negative voltage). For instance the vector [PON] indicates that the upper pair of phase U, the cen-
ter part of phase V, and the lower transistors of phase W are closed. [8]
Figure 11: Switching The 19 distinctive
space –vectors for a 3-level converter [8]
Figure 10: Switching states of a three level
converter [5]
9
The task of the 3-level converter is to generate desired output-voltages (Va, Vb and Vc). This is
achieved by the use of a voltage reference VREF. The VREF is “constructed” by the space vector modu-
lation. A given VREF can be represented by the three closest switching state vectors, which are closest
to the sector where VREF is located. As seen from Fig. 15 the VREF is constructed by the three vec-
tors VS0, VM and VL. [5]
To get a better approximation of VREF there are different duty
cycles for each of the three voltage vectors (dvector_index).
VREF = dS0 VS0 + dM VM + dL VL
0 1S M Ld d d+ + =! [5]
The different duty cycles are functions of the modulation index m – which represents the desired
voltage amplitude of either phase voltage. [5]
Figure 12: Switching state [PON] [8]
Figure 13: VREF constructed by
three switching states [5]
10
4. Capacitor unbalance and simulation
4.1. Capacitor unbalance
For a back-to-back NPC VSC the design of the DC-bus capacitors is a critical part of the engineering.
Due to the low frequency neutral point current, the voltage across the capacitors can be unbalanced.
Because of possible overvoltages in the circuit and the worsening of the quality of the currents re-
garding the load side, it is one of the main goals to delimit the neutral point current and to keep the
capacitor voltages balanced[1].
In the following the basic equations to express the unbalanced capacitor voltages and the neutral
point current are explained. The voltage across the capacitors-bus is divided by the two capacitors,
each capacitor voltage is defined to consist of a constant DC part and a voltage ripple.!
!!" ! !! ! !!
!! ! !! ! !!"!! !!! !
!!"!! !!!
The neutral point voltage can be written as
!!" ! !!! ! !!!
The equation for the currents at the neutral point is the sum of the currents from the rectifi-
er/inverter and the capacitors.
!!"# ! !!"# ! !!" ! !!" ! !
The neutral point current !!" is defined as
!!" ! !!"# ! !!"# !!" ! !! !!!!!"
!!" ! !! !!!!!"
!!" ! !! !!!!!" ! !! !
!!!!" ! !! !
!!!!"! ! !!!!!" ! !! !
!!!!"! ! !!!!!"
! !! !!!!!!!!"
! !! !!!!!!!
!"
Figure 14: The DC bus
11
Assuming the same value for the capacitances, a neutral point current of zero will occur when the
voltage ripples in both capacitors are zero or equal to each other. The simplified formula below
shows that the neutral-point current is a function of the 3-harmonic of the line frequency. The !!"
gets larger with a high ma, and with a small DPF (power factor displacement) following the load. An
expression for !!" is given for an simplified modulation example with ma=1 and DPF=0. [1]
23
8 ˆ( ) cos3base
NP phase basei t i t!
!"
= #
4.2. Simulation in MATLAB/SIMULINK
4.2.1. Basic setup
The perfect sinusoidal ac-source, representing the generated energy of the wind turbine is set to an
arbitrary frequency of 40 Hz, with an amplitude of 1800 V. This frequency will vary when using a
synchronous generator. The grid side is represented by a R-L load with L=500 mH and R=10 !,
with a desired frequency of the converter output voltage at 50 Hz. The capacitors connecting the
rectifier and the inverter are set to C=4500 µF.1
The gate signals to the transistors in the rectifier and the inverter are simulated by the above de-
scribed PWM. The frequency of the reference voltage in the rectifiers PWM is equal to the ac source
frequency and analog equal to the grid frequency in the inverters PWM. Both the rectifier and the
inverter are working in the linear region, since !! =0,8. The frequency modulation ratio !! is 33 in both
the rectifier and the inverter.
A visualization of the MATLAB model can been seen in the Appendix A2.
4.2.2. Simulation results
The PWM of the inverter was shown previously. Fig 15 shows the resulting gate signals to fire the
transistors in one leg. The other legs gate signals will be a 120° and 240° shifted.
1 MATLAB requires to integrate a small resistance of 0,01 ! in series to each capacitor.
12
The measured current in the neutral point is shown in Fig. 16
Figure 15: The gate signals for the transistors in one leg
Figure 16: The neutral point current
13
It can be seen that there is a periodic changing in the direction of the current. The peaks mean a dif-
ference between the currents from the rectifier and to the inverter, thus the capacitors will be
charged or discharged.
The resulting unbalance in the DC-bus voltage is proven by the measurements shown in Fig. 17. It is
to notice that in the plot the voltage across the lower capacitor is measured in the opposite direction
compared to the upper one. The neutral point voltage, the sum between the upper and lower capaci-
tor voltages, shows a periodic ripple which refers to the neutral point current shown above. The re-
sults show that each capacitor voltage consists of a DC part and a ripple part due to the neutral point
current, which charges the capacitors.
Figure 17: The capacitor vol-
tages
Figure 18: The voltage across the
DC-bus
14
So the total voltage across the capacitors consists of a DC part and a not desired ripple part, as
shown in Fig. 18. To reduce the ripple, one solution is to increase the capacitances, but this will also
mean more space for the elements and higher costs. Another possible solution offer external circuits
like a buck-boost converter to compensate the unbalanced voltage. The optimal solution can be an
improvement of the strategy and type of modulation technique, like using the Space Vector Modula-
tion in closed-loop.
Finally in Fig. 19 the three phase output of the inverter part is plotted.
The phase to phase signals are a 120° phase shifted and their frequency is 50 Hz, as it was desired for
the output.
4.2.3. Conclusion
The three-phase three-level back-to-back NPC converter was successfully simulated in MATLAB.
The measured outputs prove the previously derived neutral point current fluctuation and the corre-
sponding capacitor voltage unbalance. In a further work a closed expression of the neutral point cur-
rent must be found, showing on which variables it depends. Then an optimal value for the capaci-
tances can be acquired, taking the worst case into account.
Figure 19: Inverter three phase output to the grid
iii
References
[1] E. J. Bueno, S. Cobreces, F. J. Rodriguez, F. Espinosa, M. Alonso, R. Alcaraz. “Calculation of the DC-bus Capacitors of the Back-to-back NPC Converters”. EPE-PEMC 2006 Portoroz, Slovenia. Pages: 137-142.
[2] A. Calle, J. Rocabert, S. Busquets-Monge, J. Bordonau, S. Alepuz, J. Peracaula.
“Three-Level Three-Phase Neutral-Point-Clamped Back-to-Back Converter Applied to a Wind Emulator”. Universitat Politecnica de Catalunya, Escola Universitaria Politecnica de Mataro.
[3] A. Nabae, I. Takahashi, H. Akagi. “A New Neutral-Point-Clamped PWM Inverter”. IEEET-ransactions on Industry Applications, Vol.1a-17, No.5, Sept/oct1981. Pages: 518-523.
[4] N. Mohan, T.M. Undeland, W.P. Robbins. “Power Electronics-Converters, Applications, and
Design”. 2nd edition, 2003, Chapter 8. [5] N. Celanovic, D. Boroyevich. “A Comprehensive Study of Neutral-Point Voltage Balancing
Problem in Three-Level Neutral-Point-Clamped Voltage Source PWM Inverters”. IEE Transaction on power electronics, Vol. 15, No. 2, March 2000
[6] J.Sayago, “Three Level Neutral Point Clamped Voltage Source Converter (3L-NPC-VSC)”
Tecniche Universitet Berlin 06.06.06 (Power point presentation) [7] E.J. Bueno,R. Garcia, M. Marron, J. Urena, F. Espinosa.”Modulation Techniques Comparison
for Three Levels VSI Converters”. IEEE 2002 Madrid, Spain. Pages: 908-913 [8] R. Zaimeddine: ENOFF Presentation: Three level voltage source inverter.
iv
Appendix
A1: [8]
#$%&'()!*)+&$,! -.'+)!*)+&$,! -/0&+102(!3&'&)3! #)+&$,!&4.)!5+%'33060+'7
&0$28! #)+&$,!9'(20&:;)! <);:2;'2+4!
=!>!?! !!! @AAAB!@CCCB!@DDDB! !E),$!#)+&$,!5E#8! ?! F!3/0&+102(!3&'&)3!6$,!&1)!G),$!H*)+&$,!
=!>!I! !!!! A7&4.)! D7&4.)!
-J'%%!#)+&$,!5-#8!!
A7&4.)!-J'%%!#)+&$,!5A-#8!
!D7&4.)!-J'%%!#)+&$,!
5D-#8!
13 dV !
K!3&'&)3!6$,!)'+1!*)+&$,!
!!! ! @ACCB! !
!!! ! ! @CDDB!
=!>!K! !!!!!! ! @AACB! !
!!! ! ! @CCDB!
=!>!F! !!!!!! ! @CACB! !
!!! ! ! @DCDB!
=!>!L! !!!!!! ! @CAAB! !
!!! ! ! @DCCB!
=!>!M! !!!!!! ! @CCAB! !
!!! ! ! @DDCB!
=!>!N! !!!!!! ! @ACAB! !
!!! ! ! @CDCB!
=!>!O! !!! @ACDB!
9);0:J!#)+&$,!59#8! 33 dV !
D$!
=!>!P! !!! @CADB!
=!>!Q! !!! @DACB!
=!>!I?! !!"! @DCAB!
=!>!II! !!!! @CDAB!
=!>!IK! !!"! @ADCB!
=!>!IF! !!"! @ADDB!
R',()!#)+&$,!5R#8!23 dV !
=!>!IL! !!"! @AADB!
=!>!IM! !!"! @DADB!
=!>!IN! !!"! @DAAB!
=!>!IO! !!"! @DDAB!
=!>!IP! !!"! @ADAB!S$&'%!3.'+)!*)+&$,3!IQ! ! S$&'%!3/0&+102(!3&'&)3!KO! ! ! !
v
A2: The MATLAB model
Layout of three-phase three-level back-to-back NPC converter:
Layout of PWM in rectifier (inverter is the same):
vi
Layout of the rectifier (the inverter is the same):