2W4 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany. 2604

Control design for integrated switch-mode power a new challenge?

Bruno Allard', Senior Member, ZEEE, SBverin Trochutt , Xuefang Lin-Shi*, Jean-Marie RBtif' 'CEGELY, CNRS UMR 5005, INSA-Lyon

Building L. De Vinci, 20 avenue A. Einstein, F-69621 Villeurbanne Cedex, France Email: {hruno.allard, xuefangshi, jean-marie.retif}@insa-lyon.fr

t STMicroelectronics. TPA-Cellular Terminal Division 12, rue Jules Horowitz, BP 217, F-38019 Grenoble Cedex, France

Email: severin.trochut@st.com

AbsIract- Hard switching DClDC converten have been stud- ied for decades. Many control techniques have heen reported, and textbooks detail so-called classical control design methods. The Buck converter is known as a simple topology of satisfying stability. However the monolithic integration of a buck converter including the control system leads to a possible non-slable con- verter in case of large load transienL More generally it is difficult to certify the accuracy of the control system. Integrated switch- mode power supplies needs to he investigated focusing control design issues. Global efficiency dictates to limit the budgets in biasing current of control loops, hence limits their bandwidth. Among others, Ib is latter limitation renders the classical control design methods non satisfying. The paper investigates the control design challenge related to integration of switch-mode power supplies (SMF'Ss). Applications are discussed from simulation point-of-view. Particularly a trade-off must be set between control accuracy and performances on load transients. As it is not possible to specify the worst-case load transient, classical control design methods do not offer satisfying results. Alternative control design methods are investigated. Sensitivity transfer functions are introduced and an application method is detailed. Hybrid system methods are also investigated and their application is discussed. The design of integrated SMPSs requires adequate modifications of CAE-tools and design flows.

I. INTRODUCTION

Fig. 1 pictures the awaited evolution of CMOS technology thickness as published in various papers [I]. The power supply voltage is intended to decrease down to OSV in few years from now. The MOSFET transistor threshold voltage will also suffer a significant decrease. This effect will cause an increase in the transistor leakage current, hence an increase in steady-state power losses (Fig. I ) . To overcome this dangerous situation with regard to digital circuits, many solutions are already available to the design engineer, and other solutions are under development [2]. For example the dual-gate transistor offers a normal operating gate, and a second gate where a different voltage is applied to stop the drain leakage current when the transistor is in idle mode [3]. Many papers are promoting the adaptive variation of the power supply voltage: the technique is called "voltage hopping" 141. Threshold voltage and power supply voltage must be varied spatially inside the integrated circuit and temporarily during operation to create efficient active leakage control [5]. Embedded voltage regulators will he necessary to produce the variable voltages inside the chip.

2002 '04 '06 '08 '10 '12 '14 '16 Year Year

Fig. I . Predictable evolution of CMOS technology in terms of thickness. power supply voltage, transistor threshold voltage (left). switching power losses and leakage power losses (right).

Due to a poor efficiency, a linear voltage regulator is not a practical option particularly if large currents have to be processed, or multiple regulators have to be embedded inside the chip. Integrated synchronous switch-mode power supplies (SMPS) seem to he good candidates.

Integration of synchronous SMPS is also boosted by the microprocessor demands in power [6], (71. Switched capacitor converters [8] had been originally studied but show a signifi- cant limit in current. They offer no tuning range.

SMPS and its monolithic integration is not a new topic [9]. Fully monolithic SMPSs have been presented [IO] and many products are commercially available. The control circuit is not always included and controllers like [ I I ] are often encountered since they are optimized for synchronous converters and offer a predictive gate drive technology. However these demonstrators suffer several limits:

the efficiency remains low (less than a minimum go%), . the dynamic performances can not cop with large power transient, the design remains quite empirical what is not compatible with the development of Intellectual Properties (IP).

The boost converter detailed in [I21 features a little bit more than 50% efficiency. Moreover the optimization procedure detailed in [I31 does not take into account the efficiency as a constraint. The authors only retain the following specifications ignoring the converter control issues.

0-7803-8399-0/04/$20.00 02004 IEEE. 4492

2004 35lh Annual lEEE Power Elecrronics Specialists Conference Aachen, G e m n y , 2004

P. the m i m u m rated wwer Row. W Vi , the w e q e input volmge. V va , the BVErop ou,put " d l a p , v

f, he switching frequency. Hz Ax the output mak-to-@ "pple. V

..:. I

Fig. 3. Schematic of a Convenient compensator network

delay should be kept at a minimum value to minimize body- diode conduction loss. In addition, the body-diode reverse- recovery related to EM1 is a big concern in high frequency operation. It is assumed here that the driver is optimal (it does not interact with the control design issue).

." .- .. .I .- .* .. .-.- Fig. 4.

The corrector circuit is proposed to implement the following idea, The LC-circuit offers a limited bandwidth (L=IOpH, C=22fiF, fLsdB=lOkHz). An additional frequency decade is at least necessary to obtain the regulation performances. Near IOOkHz the corrector should bring 40dB amplification. The corrector then exhibits a significant gain at the switching frequency. A discrete implementation allows a sever cut-off at the switching frequency but not the monolithic implementation unless sacrifying the efficiency. It is considered a 3V input- voltage SMPS that regulates a 1.8V output-voltage within a 3% bandwidth. The load current maximum rating is 1A. The error amplifier supply voltage is 3V. Fig. 4 pictures the error voltage during steady-state. Fig. 5 pictures the error voltage during a load transient (load-current demand rises from 6mA to 450mA in Ifis). Saturation appears. The output voltage oscillates and recoven to the regulated value. The 3% bandwidth is exceeded (Fig. 5 ) . Fig. 6 pictures an other case of load current transient that initiates a stable oscillation on the output voltage. This oscillation is not the consequence of a tremendous load transient but the behavior of a particular compensator optimization and the load transients observed in

Sawtooth, error signal and output voltage during steady-state

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2w4 35111 A n n u l IEEE Power Electronics Specialisrs Conference Aachpn, Germany, 2004

.* ^* , - . l : .cul : , amplifier main pole. A third pole is not physicaly implemented as it should be less than the amplifier Miller pole. With respect to discrete converter, the amplifier main pole is assumed to be sufficiently large, what is not the case in integrated converters.

, , , , /

.. .. L. .. ..

Fig. 6. Saw-tooth, error signal and o~tput voltage during a large load transient

Fig. 5. The controller has been optimized as explained in next section. It is obviously non satisfying.

111. THE CLASSICAL CONTROL DESIGN METHODS

DC/DC converter topologies are presented in numerous textbooks [14][15]. Control of DC/DC converters is also presented. Several hypotheses are introduced. Among others, the network time-constants should be larger than the switching period. The so-called averaged modeling approach may be applied. This method yields in a systematic manner the various transfer functions required to build the control circuit (Fig. 7). The method is available in several commercial CAE-tools [16]. Fig. 3 pictures a convenient compensator circuit. The circuit provides 2 zeros and 3 poles including the operational

Fig. 1. Small-signal model of the pilot SMPS

Classicaly the first compensator pole, fplr is used to cancel the inductor ESR zero and provide controlled gain roll-off. The second compensator pole, fp2, is used to obtain maximum attenuation of the switching ripple and high frequency noise with minimum phase lag at close-loop crossover frequency fOdB. Two zeros are used to avoid the conditional stability related to L-C double pole and provide additional phase boost. When designing fz, and fi2, the trade-off between the stability margin and the regulator performance should% he considered. The settling time during a load transient is then related to the first zero. The higher is the first zero frequency, the faster is the settling time. Both zeros affect the stability margin and closed-loop overshoot voltage during a load transient. When the frequencies of these two zeros move higher, the stability margin decreases and the overshoot voltage decreases. In fact the design engineer has to settle a trade-off between stability and load transient performances. It is not practicable to test a design against all possible load transients, i.e. for the awaited variations of current starting from any conditions of load current, and for various settling times. Only corner simulations are affordable.

Fig. 5 and Fig. 6 relate the limitations of the here-above optimized corrector. Fig. 5 indicates a saturation of the error voltage. In fact the PWM stage may be optimized to attain 100% duty ratio before the error voltage saturation. When including this non-linearity into the small-signal model in Fig. 7, the Nyquist representation in Fig. 8 is obtained. Instead of checking for the locus - I , the designer evaluates the system stability with respect to the curve h(c), related to the first harmonic effect of the considered non-linearity.

1 V&t h(c) = - arcsinX + A.-, x = - (1) The Nyquist figure shows 2 regions. When the load transient

is smooth enough to avoid saturation (region #I), the locus - I is not circled and a local stability is assessed. If saturation occurs (region #2), the local stability locus is circled (once) and the stability criterion is endangered. The error voltage saturation leads to an open-loop operation of the SMPS. The output voltage evolves until saturation disappears and the regulation capacity is recovered. The oscillating behavior is then unstable as shown in Fig. 5 . Unfortunately the duration of

A c

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2004 35th Annual IEEE Power Electronics Specialists Conference Aachen. G e m n y , 2W4

sensitivity functions.

= r.w + syy.wy i syB.wB + s y u . w , %"

Fig. 8. Nyquist represenlatian including the saturation effect

the oscillating behavior is uncontrolled and the output voltage surely exceeds the 3% bandwidth.

The stable oscillation (Fig. 6) is related to a phenomenon called "period doubling" as detailed in [17]. It is a complex critical behavior behind the SMPS conditional stability analy- sis.

It appears that the classical control design method shows limitations when applied to a monolithic SMPS compensator. Alternative control design methods must be evaluated. The compensator circuit may also be adapted, and design methods are required to guide the circuit synthesis.

IV. ALTERNATIVE METHODS

The paper investigates two alternative ways for control design.

LYY -~ K P r=-- I + K P 1 + L y y

(3) 1 1 syy = ~ -

1 + K P - 1 + L~~ (4)

( 5 )

-KP -Lyy SYB = - = - 1 + K P 1 + L y y

syu = - - - 1 + K P l + L y y

P - P

Constraints or disturbance rejections are naturally expressed in terms of frequency sensitivity shapes. For a given corrector optimization, the sensitivity functions allow to evaluate the corrector behavior in relation to the desired attenuation con- straints. In addition, the margin module and the margin delay quantify the robustness of the modeling uncertainties. Fig. IO presents the Nyquist plot of Lyy . The module margin AM is defined as the minimum distance of L y y to the critical locus -1. The delay margin AT is deduced from the phase margin A@ by Ar= e

/--h

A. Sensirivizy transfer matrix Fig. 10. Typical Nyquist plot of L u y

Sensibility transfer functions may be considered instead of the output-to-duty-ratio and the output-to-input transfer functions. Fig. 9 represents the SMPS (P(s ) ) and its corrector (K(s)) when adding control noise Wu, output noise W y and measurement noise W E . The objective is the study of the system dynamics, robustness and noise rejection properties. From Fig. 9, i t comes the following relation that leads to the

Fig. I I illustrates the sensibility of output-to-output S y y , the sensibility of measure to output and the sensitivity of control-to-output.The module and the delay margins in Syy evaluate the stability of the closed loop system; and the gradient of S y y on low frequency determines the dynamic behavior of the system. The bandwidth on S y s defines the close-loop bandwidth and the influence of noise on the output voltage. The gain on Syu verifies the rejection of control perturbations such as the noises introduced by the PWM. The

behavior of the system. The bandwidth of Sya defines the close-loop bandwidth and the influence of noise on the output voltage. The gain of Syu verifies the rejection of control perturbations such as the PWM-related noises. The robustness constraints and the knowledge on the disturbances leads to design the correctors in terms of poles and zeros assignments. The margin values depend on the model precision and the component dispersion. In order to ensure robustness, the

W"

Y gradient of Syy at low frequency determines the dynamic

wh

Fig. 9. Flow-graph representation of the SMPS

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2004 351h Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2W4

Fig. I I . Sensitivity Functions

module margin AM is kept higher than 0.5, the phase margin is about 45'. Experience leads to set the delay margin at ahout half the switching period Tawitch. But the frontier is not so strict. Fuzzy logic is more suitable to quantify robustness, An example of membership functions qualifying the phase margin and delay margin is shown in Fig. 12.

Fig. 12. Membership functions based on AM and AT

The membership function of a cost on the output voltage is given in Fig. 13. The stability robustness can be expressed by

Fig. 13. Membership functions of a cost on the output voltage

the fuzzy rules defined in the following table.

Medium

On the same way, other membership functions and fuzzy rules in relation with the sensitivity functions can he defined to quantify disturbance rejection. The corrector design becomes an optimization problem in order to find the optimum of the global fuzzy cost function which takes into account constraints of robustness and satisfies the requirements of disturbance rejection performances. A stochastic genetic algorithm is gen- erally used to realize this optimization. The authors have no results to include at time of edition.

B. Hybrid dynumicul systems

Hybrid system approaches [IS], [19], [ZO], [211, [22] have been introduced to solve control problems in case of complex systems. The synchronous buck converter may be seen as an hybrid system, with 2 or more states depending on current conduction conditions.

I) Definition: A hybrid system is a dynamical system that cannot be represented and analyzed with sufficient precision either by the methods of the continuous systems theory or by the methods of the discrete systems theory ([231). A hybrid system is consistently a combination of continuous states and abrupt state jumps. The jump conditions and dates may not be easily predicted. Basically the jumps are classified between autonomous jumps and controlled state jumps. Autonomous and control switchings will then define the environment of the related jumps. The hybrid automaton in Fig. 14 comprises 3 states in discontinuous conduction mode. It combines 3 time- independent models. The separate analysis of the 3 models is very easy but the analysis of the system as a whole is difficult. It is known for example that the system may be unstable even if the two matrices A. to A2 are stable ([24]).

2 ) Srabilify: The methods are based on hybrid automaton representations but may be separated in two classes.

Methods rely on sensitivity matrices with varying eigen- values, and tend to picture locuses of eigenvalues that correspond to converter stability. Worst-case corner of operating conditions are pictured on the locuses and a trade-off may be defined from graphical data. Other methods state the problem in terms of collections of states (trajectories during a transient), and try to define safe sets of state. called "safe balls". Trade-offs between stability and load transient performances may be accessed through graphical representation.

Most of the papers detail the application to boost topologies, as they are reputed of bad stability. The pilot SMPS hybrid automaton is pictured in Fig. 14.

3) Simulation: Many simulators are able to handle hybrid system and perform some accurate simulations. Since many of them are not free of charges, the authors decided to implement their own simulator based on a free framework (scilab [E]) which is able to solve differential equation. Fig. 15 shows the simulation results of Fig. 14 hybrid model. Some sub- harmonics oscillations are present. This is due to numerical integration precision. But still, this result can be compared 10 Fig. 4.

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2004 35rh A n n u l IEEE Power Electronics Specialists Conference

IC IIFs

lI=O

VerrorcVramp Lo_1 x- = A,X +B,U 1' = CIX + DIU

Fig. 14. Hybrid model of the buck SMPS

, a l l

I-

,- ,MI

IWL

I-

,rnM 1%

I-

21% I_ n u .%.a 227- '2- >% .- ..,_ .,h. Fig. 15. Hybrid model simulation of the buck SMPS

V. CONCLUSION

The paper issue i s to enlighten the problem o f control design for integrated SMPSs. Classical methods have proved efficient on discrete SMPSs, hut lead to limited results in the case of integrated SMPSs. A large SMPS bandwidth i s desired and unstable compensators are required. Particularly the limited bandwidth of the amplifiers modifies the specifications of the control system. Ever-increasing switching frequencies wil l st i l l harden the situation. Digital control systems are not practicable and the analog counter-parts require to fix values for poles and zeros i n order to satisfy a trade-off between accuracy and performances with regard to load transients. The paper explains the inner stability problem. Alternative control design methods are investigated. Sensibility functions appears more robust but do not solve the stability problems. Hybrid dynamical systems have proved efficient with boost technologies and could be fruitfully applied to the monolithic buck topology. However the method complexity increases and adequate design tools should be provided to the I C designer whose prime concerns are related to silicon implementation.

ACKNOWLEDGMENT

The authors wish to thank Dr Christophe Pr6mont for his technical support and also STMicroelectronics i n Grenoble,

~

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France, for the manufacturing o f SMPS ICs and for the financial support o f this study.

REFERENCES 111 T. Sakurai. "Perswctives no nower-aware electronics."Pmc. ofthe IEEE

~1 r~ ~~~~ . ~ ~~~~~~~~~, ~~ L ~ 1 ~ r~~~~ ~~ ~ lnternatinnnl Solid-Stare Circuit Conference, 2003, cdrom, paper 1.2.

(21 MARLOW, "A comprehensive bibliography on low-power design:' www.1owpwernrg. 2002.

[3] W. Kludge, L. Dathe, and R. Jaehne, "A 2.4GHz CMOS msceiver for 802.1 Ib wireless lans:' Pmc. of the IEEE hrernntionul Solid-State Circuir Confennce, 2003. cdrom, paper 20.6.

141 S . Lee and T. Sakurai. "Run-time voltage happing for low-power rea- time systems," Pmc. of Design Auto,mtinn Conference. pp. 806-809. lllne 2000~ .. ~~~~

[5] Y. Nakagome, M. Horiguchi, T. Kawahara. and K. Itoh, "Review and prospects of low-voltage RAM circuits," IBM Journal ofR&D, vol. 47, "0. 516. SeptINov 2003.

[6] H. Wetrel, N. Fraehleke, F. Meier. and P. Ide, "Comparison of low- voltage tooologies for voltage regulator modules:' P m . of the IEEE - - Indutry Applicorionr Society Annul Meering. 2002, cdrom.

171 "Center for Dower electronic svstems : Annual reoort." Wminia Tech

"0. 2, pp. 228-235. 1998. [9] A. Stratakos. S. Sanders, and R. Brodersen. "A low-voltage CMOS

DCIDC convener for a portable batteryoprated system:' Pme. < f i h e IEEE Power Electmnics special is^'^ Conference, pp. 619426. 1994.

[ IO ] K. S . A. Abedinpour, Trivedi, "DC-DC power converter for monolithic implementation," Pmc. of the IEEE Industry Applicorims Society An- nu01 Meeting. pp. 2471-2475. 2000.

[ I I] T12003. "TPS4002X datasheet, enhanced. low-input voltage-mode syn- chronous buck controller:' Tam Insrru,nents Literorure, vol. SLUS535, 2003.

[I21 E. McShane and K. Shenai, "A CMOS monolithic 5MHz. SV, 250mA. 56% efficiencv switch-mode boost converter with dvnamic PWM for embedded power management," Pmc. cfthe IEEE Industry Applicrrtions Sociefy Annual Meeting, pp. 653451, 2001.

1131 S . Musunuri and P. Chapman, "Optimization issues for fullyintegrated CMOS DC-DC conveners.'' Pmc. of the IEEE Industry Applicolions

~~

Society Annual Meeting. 2002, cdrom. I141 N. Mohan, T. Undelmd. and R. Robbins, Power electmnics cunve~t-

ers,rrpplicrrtiunr ond design. [IS] R. W. Erickson and D. Maksimavic, Fundomentdv of Power E1ectmnic.v.

Kluwer, 2001, 2nd edition. [I61 N. Froehleke, D. H a m , H. Mundinger, H. Njiende. and P. Wallmeier,

"Cae-tool for optimizing development of swichted mode power sup- plies,'' Pmc. of the IEEE Applied Power Electmnics Conference. vol. 2, pp. 752-758. March 2001.

[I71 G. Papafotiu and N. Margaris. "Calculation and stability investigation of periodic steady-states of the voltage-controlled buck DCfDC converter," IEEE Transactions Power Electmnics. 2003, to be published.

1181 K. Wong, "Stability study of a voltage-mode buck regulator using system poles approach," Pmc. ofthe IEEE. 2002.

[I91 B. Wong and H. Chung. "Steady-state analysis of PWM DCIDC switching regulators using iterative cycle time-domain simulation," IEEE Tronsactionr Industry Applications, vol. 45, no. 3, pp. 421432, 1998.

1201 M. Senesky, F. Eirea, and T. Kao. "Hybrid modelling and control of power electronics:' P m . of rhe Hybrid System Contml Conference, pp. 4 5 W 6 5 , 2003.

[2 I] B. Wong, H. Chung, and S . Lee, "Computation of the cycle state-variable sensitivity matrix of PWM DCIDC eonvenem and its applications," IEEE Trmactiuns Circuitr&Systems-l. vol. 47, no. IO, pp. 1542-1548, 2000.

[22] D. Liberaon, Switchin8 in sysemr and conrml. sec Foundations and Applications Series.

1231 J. Lunle and J . Raisch. Discrere models for hybrid sysretns, ser. Modelling, Analysis, and Design of Hybrid Systems. Springer, 2002. DD. 3-14.

Wiley Inter-Science. 1995. 2nd edition.

Systems and Contml Ed.. 2003, 248p.

1241 M. Bmickv. "StabiliN of switched and hybrid svstems:' Pmc of the . . ~I IEEE Conference on Dension and Contml. pp. 3498-3503, 1994.

[25] INRIA. Scilab [Online]. Available: www.scilal.org