IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002 613

Constant Charge Erasing Scheme for Flash MemoriesAndrea Chimenton, Paolo Pellati, and Piero Olivo

Abstract—This paper presents a new erasing scheme forFlash memories based on a sequence of bulk to gate-box pulseswith increasing voltage amplitude. It will be experimentally andanalytically demonstrated that the erasing dynamics alwaysreaches an equilibrium condition where each pulse induces aconstant and controllable injected charge and, therefore, con-stant threshold shifts. The analytical study allows us to expressboth the final threshold voltage and the oxide electric field as afunction of technological, physical, and electrical parameters.Electrical parameters can be conveniently adapted to control boththe threshold voltage and the oxide fields, thus reducing oxidestresses. Advantages with respect to the standard box erasingscheme are theoretically and experimentally demonstrated.

Index Terms—Erasing operations, Flash memories, integratedcircuit reliability, reliability, semiconductor memories.

I. INTRODUCTION

T HE MOST common schemes used for the erase operationin Flash memories are based on a sequence of box

pulses with a constant amplitude applied to the bulk of thesector/array [1], [2] until a target erased threshold is reached.Erasing curves, i.e., the threshold voltage evolution for a singlecell versus erasing time during a single erase procedure, arenonlinear starting with a high initial threshold shift due tothe first erasing pulse. The following pulses have a decayinginfluence on the threshold shift. Therefore, the erasing speedcan be improved only by increasing the amplitude of theerasing pulses. Such an approach, however, may have harmfulconsequences in terms of reliability. In fact, owing to the highinitial value of the programmed threshold voltage, the use ofa high voltage implies a high electric field peak within theoxide at the beginning of erasing, that may be dangerous forthe reliability and the performance of the memory since highelectric fields produce degradation in the oxide properties[3]–[5].

To overcome this problem and to reduce the reliability effects,some authors proposed erasing schemes that are based on a con-stant tunneling current [6], [7] showing improvements in termsof endurance. Such a method requires an additional current reg-ulator to be integrated.

This paper presents and analyzes the Constant Charge ErasingScheme (CCES), based on the concept of injecting a constantcharge during erasing, which is similar to the constant tunnelingcurrent approach. Differently from the Standard Box ErasingScheme (SBES) where a sequence of erasing pulses with a con-

Manuscript received Ocotber 15, 2001; revised December 19, 2001. Thiswork was supported in part by CNR under the MADESS II Project. The re-view of this paper was arranged by Editor T. Skotnicki.

The authors are with the Dipartimento di Ingegneria, University of Fer-rara, Ferrara, Italy (e-mail: achimenton@ing.unife.it; pellati@ing.unife.it;olivo@ing.unife.it).

Publisher Item Identifier S 0018-9383(02)03050-2.

stant gate-to-bulk amplitude is used, the CCES consists in a se-quence of box pulses with increasing amplitude. As it will bemathematically and empirically demonstrated, an equilibriumcondition is soon reached for any cell so that , that is thethreshold shift provoked by theth erasing pulse, is equal to thebulk voltage step . In such a condition, it is guaranteed thatthe charge injected from the floating gate by each pulse remainsconstant.

The shape of the resulting erasing curves is so simple thatthe final threshold voltage can be analytically expressedas a function of physical, technological and electrical parame-ters. This allows the analytical control of through the elec-trical parameters. The final threshold voltage can be easily mod-ified by acting on the number of pulses, each one producing athreshold shift that exactly equals the bulk voltage step. Finetuning of is achievable varying the amplitude of thefirst pulse because of the one to one relation betweenand

variations.The evolution of the oxide electric field during an erase op-

eration can also be analytically expressed and it will be shownthat, when equilibrium is reached, it can be confined in a fullycontrollable range of values. The use of a small amplitude for thefirst pulses removes the problem of high initial encounteredwith SBES. Consequently, because of the reduced oxide degra-dation, CCES is experimentally found to guarantee a higher en-durance with respect to SBES. Besides the advantages relatedto the analytical expression of both and , the proposedmethod is particularly suitable for reliability studies. In fact,by considering physical parameters as constant during a nom-inal erase operation, any deviation from the expected behaviorcaused by oxide degradation and/or erratic bits, can be analyzedin terms of variation of physical parameters.

II. EXPERIMENTAL SETUP

All measurements have been performed on 512k bits sectorsof Flash test chips, that are standard NOR Flash memories (cellarray, decoders, read path) but the internal finite state machinecontrolling writing algorithms and internal generators providingprogramming and erasing waveforms. The cell’s nominal tunneloxide thickness was 10.2 nm.

By means of a dedicated automated test equipment (researchinstrument for flash evaluation [8] [RIFLE]), it has been pos-sible to perform a set of experiments fully characterizing theimpact of any modification in the writing procedures.

Both erase (via FN tunnel) and program (via hot electron)operations have been performed applying a sequence of boxpulses. In particular, during the erase operation, the cells’ con-trol gates were biased by pulses with a constant amplitude

V, while the common bulk was driven by a sequence onpulses with increasing amplitude by steps of starting at

0018-9383/02$17.00 © 2002 IEEE

614 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002

Fig. 1. Shape of the erasing pulses applied to the bulk.

(Fig. 1). Both control gate and bulk pulses have a constantduration . The common source has been kept at Vto avoid the source/bulk junction turn on, while the drains havebeen left floating.

The alternative choice of a constant and of a varyingdoes not produce different results in our test chips and the twopossible CCES implementations are theoretically equivalent. Indifferent architecture the limitations imposed by the internal de-sign can make one solution more convenient.

The threshold voltage is here defined as the control gatevoltage at which the metal–oxide–semiconductor (MOS) celldrains a predefined current.

III. B ASIC DEFINITIONS

Floating gate cells are normally programmed via hot electroninjection and erased via Fowler–Nordheim tunneling (FN). Inthis paper, we consider the simple FN model, valid for triangularbarrier [9], where the injected current can be expressed as

(1)

In (1)

(2)

and

(3)

where represents the equivalent energy barrier [10], isthe electron free mass, is the electron effective mass in theoxide, is the tunneling area, is the electron charge, is thenormalized Plank constant, and is the oxide electric field.

As demonstrated in [11] when CCES is applied, the thresholdvoltage after erasing pulses, i.e., , is

(4)

where

(5)

Fig. 2. Erasing curves for the same cell obtained using two different erasingschemes: standard box (dotted line) and constant charge (solid line). The samenumber of pulsesN = 15 of duration�t = 10 ms have been applied. For theramped boxV = 3:0 V, �V = 0:3 V. For the standard boxV = 6:3 V. Inboth cases, the control gate was biased at�8 V.

Fig. 3. Oxide electric fields at the beginning and at the end of each pulse forthe two erasing curves of Fig. 2. The dashed line refers to the SBES, where theelectric field at the end of the pulse coincides with that at the beginning of thefollowing pulse. The solid lines refer to the CCES.

and and are defined as

(6)

(7)

is the threshold value measured after UV erase, andand are the source to bulk voltage and the drain to bulkvoltage, respectively. is the totalcapacitance, and is the coupling coefficient wherethe symbol indicates indifferently the control gate, the drain,the source and the bulk.

The expressions for the electric field at the extremes of theth pulse, also demonstrated in [11], are

(8)

(9)

where is the threshold measured after pulse, forand .

As mathematically demonstrated in the Appendix, when theequilibrium condition has been reached, i.e., after a reasonablenumber of pulses, the expressions of the electric field at the be-

CHIMENTON et al.: CONSTANT CHARGE ERASING SCHEME FOR FLASH MEMORIES 615

Fig. 4. Distribution of the erased thresholds for two different sectors of 512k cells erased using the SBES (full lines) and CCES (dotted lines). For each erasingscheme two distributions are shown: after one cycle and after 60k cycles. Erasing conditions have been selected to guarantee the same average threshold in virginsamples:N = 11,�t = 10 ms. For CCES,V = 3:15 V and�V = 0:3 V; for SSEB,V = 5:25 V.

ginning and at the end of each pulse can be calculated from thefollowing equations:

(10)

(11)

and their difference can be derived from (10) and (11)

(12)

It is worth noticing that the use of CCES with a fixedinstead of a fixed brings to similar equations. In partic-ular, in all equations must be replaced by , where

is the gate step voltage.

IV. EXPERIMENTAL RESULTS AND DISCUSSION

Fig. 2 shows two measured erasing curves for the same cellwhere each point represents the threshold voltage measuredafter each pulse. The same pulse duration and total number ofpulses have been used for both SBES and CCES. The same

has been achieved adjusting the bulk voltage in SBES.It can be noticed that in CCES, after the first few pulses, theerasing dynamics reaches the expected equilibrium condition,so that the slope is .

It is evident that in SBES the major contribution to thethreshold shift comes from the first pulses, the others producingonly small threshold variations. This implies the existence of aharmful oxide electric field peak at the beginning of the erasingprocedure, as it can be seen in Fig. 3 showing the electricfield at the beginning and at the end of each pulse, calculated

Fig. 5. Erasing curves for the same cell and different initial thresholdsV .After few pulses, the curves join together and begin to move on the same straightline.

using (8) and (9) with V. In the CCES the electricfield does not show any dangerous peak and after few pulsesit oscillates between two almost constant values which arewell controlled by the electrical parameters and . Inequilibrium conditions, any reduction in produces both anequal reduction of [see (12)], and proportional decreasesin and . A reduction in , instead, only produces anincrease in and in without affecting . The otherelectrical parameters and do not control the equilibriumoxide fields.

The electrical control of the peak oxide field must takeinto account the situation before the equilibrium condition isachieved. Assuming that a fixed must be reached in afixed amount of time, then, if a small is chosen, the caseof standard box erase is approached and an increase in the peakvalue must be expected. On the contrary, a large produceslarger oxide fields at equilibrium. Hence, there is a value of

setting the optimal tradeoff for both the confinement of

616 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002

Fig. 6. (a) Erasing curves (left) for three cells selected among a set of 10 000 cells featuring almost the sameV and erased by CCES. a) The highest, b) themedian, and c) the lowest curves are shown. TheV distribution for the entire set of cells is shown on the right-hand figure. (b) Erasing curves (left) for the sameset of cells selected for Fig. 6(a) but erased by SBES. Again, a) the highest, b) the median, and c) the lowest curves are shown. TheV distribution for the entireset of cells is shown on the right-hand figure.

the electric field in a restricted range and the lowering of theinitial electric field peak value. The absence of a dangerouselectric field at the beginning of the erasing operation has astraightforward impact on the charge trapping and therefore onmemory endurance. Fig. 4 in fact, shows the distribution shiftsafter 60K cycles induced by charge trapping in two differentsectors of the same chip, the former erased by CCES, the latterby SBES. Erase conditions have been chosen to guarantee thesame erased time and average threshold shift in virgin samplesand kept constant throughout the experiment by deactivatingthe erase verify procedure. The lower average distribution shiftobservable with CCES is a clue of a reduced charge trappingguaranteed by a limited electric field.

As can be seen in (4), depends on physical ( , ),technological ( , , , , , , ), and electrical( , , , , , , ) parameters. Therefore, (4)provides a simple tool for the full electrical control and anal-ysis of erasing. As expected, the expression of does notdepend on the threshold voltage and this result is well con-firmed by the experiments of Fig. 5 where the same cell pro-grammed at different has been erased using the same elec-trical parameters.

The natural spread of technological parameters does notallow, however, achieving the same for an entire sector.Fig. 6(a) shows the erasing curves for three different cells withthe highest, the median, and the lowest among a set of10 000 cells with the same and belonging to the samesector. The distribution for the same set of cells is alsoshown in Fig. 6(a). It is important to notice that an equilibriumcondition characterized by a linear erasing curve and a welldefined value is always reached. A similar distribution isalso found with SBES [Fig. 6(b)], confirming that such a spreadcannot be attributed to or controlled by the erasing scheme.

As a reference, the technological and physical parameters ofany cell can be considered as constant and thereforecan be

Fig. 7. Erasing curves for the same cell erased with differentV varying from0 V up to 2.8 V with steps of 0.4 V. All other electrical parameters have beenkept constant.

regarded as a cell attribute for a given set of electrical parame-ters. Hence, having a full control over the nominal erase opera-tion, any deviation from the reference behavior caused by erraticbits [12] and/or charge trapping/detrapping within the tunnelingoxide [4] can be experimentally observed by checking for a dif-ferent constant slope of the erasing curves [11] and it can bemodeled in terms of physical parameter variation.

Fig. 7 shows the influence of the parameter on the erasingdynamics for the same cell. It is evident that the erasing curvessimply differ because of a translation in the asymptotic straightline. In fact, when the equilibrium conditions have been reached,the threshold voltage shifts equal . Therefore does notinfluence the slope of the asymptotic straight lines.

From (4) and (5), it is reasonable to expect

(13)

as experimentally confirmed in Fig. 8.

CHIMENTON et al.: CONSTANT CHARGE ERASING SCHEME FOR FLASH MEMORIES 617

Fig. 8. Relative dependence ofV on V (dotted line),�V (solid line),and�t (dotted line). The nominal values areV = 1:5 V, �V = 0:225 V,and�t = 5:5 ms.

This result can be usefully applied to control : in partic-ular, the entire erased threshold distribution can be shifted upand down simply adjusting the value of by the same desiredquantity, while keeping constant all other electrical parameters.

The experimental sensitivity of on and is alsoshown in Fig. 8. As it can be seen, produces nonlinear andrelatively small variations, while for , an almost linear de-pendence is found in the selected range.

Summarizing the previous results, it can be stated thatcan be directly controlled by acting on , and at the same time,on and to successfully limit the oxide electric field.

V. CONCLUSION

In this paper, a new erasing scheme for Flash memories,based on bulk to gate box pulses with increasing amplitude, hasbeen presented and analyzed. It has been experimentally andmathematically demonstrated that the erasing dynamics alwaysreaches an equilibrium condition where each pulse provokes aconstant charge injection corresponding to constant thresholdshifts. With respect to an erasing scheme with constant ampli-tude pulses, this method allows to control the erasing dynamics,the final threshold voltage and the oxide electric field, thusreducing oxide long-term wear out.

has been analytically expressed as a function of physical,technological, and electrical parameters, and its dependence onelectrical parameters has been deeply investigated. It has alsobeen found that varies linearly with the amplitude of thefirst pulse, so that the entire threshold distribution can be shiftedby simply varying this parameter while keeping constant all theothers.

Analytical expressions for the oxide field at the beginning andat the end of each pulse have been provided, showing that theelectric field can be usefully controlled by the duration of eachpulse and by the pulse amplitude increment.

The proposed erasing scheme can be also conveniently usedfor reliability studies, since any deviation from the nominallinear behavior imposed to the erasing curves by a set ofelectrical parameters can be modeled as a variation of physicalparameters.

APPENDIX

The expressions of the electric field at the beginning and atthe end of each erasing pulse are [11]

(14)

(15)

where the time series is defined as

(16)

for and .is calculated as [11]

(17)

Here it is demonstrated that the electric field always con-verges toward a stable equilibrium value. This is true if and onlyif the time series always converges toward a stable equilib-rium point hereafter denoted as. Then, its expression is givenas a function of the other electrical and physical parameters. Fi-nally, its stability when changing the starting value is shown.

a) Existence of an Equilibrium Point:For the time series, it can be easily noticed that

(18)

Therefore, in equation (18), if an integerexists so that

(19)

then for any and viceversa, i.e.,is an equilibrium point for the time series (16).

b) Equilibrium Expressions of the Electric Field and of theThreshold Voltage:Using (17) and (19), the following expres-sion for can be obtained:

(20)

Expressions (10) and (11) can be easily obtained from (20) using(14)–(16).

c) Stability of the Equilibrium:Let us consider the functiondefined as

(21)

which describes the threshold voltage shift for any valueof the time series .

is a decreasing function ofwith an oblique asymptotewhose slope is 1.

Considering the time series at a generic instant, andsupposing that it differs from by the positive quantity

(22)

then, since is decreasing, we have

(23)

where .

618 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002

Therefore, using (18), will be given by

(24)

and increases without exceeding, i.e.,

(25)

The same arguments apply when

(26)

i.e.,

(27)

Therefore, for the generality of, always gradually ap-proaches .

ACKNOWLEDGMENT

The authors would like to thank A. Modelli for helpfuldiscussions.

REFERENCES

[1] J. T. Perk, J. Y. Chun, H. K. Kim, S. J. Jang, and C. G. Yu, “New program-ming and erasing schemes for P-channel Flash memory,”IEEE ElectronDevice Lett., vol. 21, pp. 491–493, Oct. 2000.

[2] T. Endoh, K. Shimizu, H. Iizuka, and F. Masuoka, “A new write/erasemethod to improve the read disturb characteristics based on the decayphenomena of stress leakage current for Flash memories,”IEEE Trans.Electron Devices, vol. 45, pp. 98–104, Jan. 1998.

[3] P. Olivo, T. N. Nguyen, and B. Riccò, “High-field-induced degradationin ultra-thin SiO films,” IEEE Trans. Electron Devices, vol. 35, pp.2259–2267, 1988.

[4] Y. B. Park and D. K. Schroeder, “Degradation of thin tunnel gate oxideunder constant Fowler–Nordheim current stress for a Flash EEPROM,”IEEE Trans. Electron Devices, vol. 45, pp. 1361–1368, June 1998.

[5] P. Cappelletti and A. Modelli, “Flash memory reliability,” inFlash Memories, P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni,Eds. Amsterdam, The Netherlands: Kluwer, 1999, pp. 399–442.

[6] R. Bez, D. Cantarelli, L. Moioli, G. Ortolani, G. Seravalli, C. Villa,and M. Dallabora, “A new erasing method for a single-voltage long-endurance Flash memories,”IEEE Electron Device Lett., vol. 19, pp.37–39, Feb. 1998.

[7] M. Dallaboraet al., “A 20MB/s data rate 2.5V Flash memory with cur-rent controlled field erasing for 1M cycle endurance,” inISSCC97, 1997,pp. 396–397.

[8] P. Pellati and P. Olivo, “Automated test equipment for research onnonvolatile memories,”IEEE Trans. Instrum. Meas., vol. 50, pp.1162–1166, Oct. 2001.

[9] M. Lenzinger and E. H. Snow, “Fowler–Nordheim tunneling into ther-mally grown SiO ,” J. Appl. Phys., vol. 40, p. 278, 1969.

[10] P. Olivo, J. Suné, and B. Riccò, “On the determination of the Si–SiObarrier height from the Fowler–Nordheim plot,”IEEE Electron DeviceLett., vol. 12, pp. 620–622, Nov. 1991.

[11] A. Chimenton, P. Pellati, and P. Olivo, “Analysis of erratic bits in Flashmemories,” inProc. Int. Rel. Phys. Symp., 2001, pp. 17–22.

[12] T. C. Onget al., “Erratic erase in ETOX™ Flash memory array,” inProc.VLSI Symp. Technology, 1993, pp. 83–84.

Andrea Chimenton received the degree in elec-tronic engineering from the University of Ferrara,Ferrara, Italy, in 2000, where he is currently pursuingthe Ph.D. degree.

His scientific interests are in the area of non-volatile memory characterization and reliabilityand modeling of physical mechanisms controllingmemory writing.

Paolo Pellati received the degree in electronic engi-neering from the University of Ferrara, Ferrara, Italy,in 1997. He received the Ph.D. degree in informationengineering from the University of Modena, Modena,Italy, in 2001.

Since 2001, he has held a research contractwith the University of Ferrara for the design ofdedicated instrumentation. His scientific interestsare in the area of electronic instrumentation design,high-performance board design, nonvolatile memorycharacterization, and testing.

Piero Olivo received the degree in electronic engi-neering and the Ph.D. degree from the Universityof Bologna, Bologna, Italy, in 1980 and 1987,respectively.

In 1983, he joined the Department of Electronicsand Computer Systems, University of Bologna,where he became Associate Professor of electronicinstrumentation and measurements in 1991. In 1993,he became Full Professor of Applied Electronics,University of Catania, Catania, Italy. In 1995, hejoined the University of Ferrara, Ferrara, Italy.

From 1986 to 1987 and autumn 1989, he was a Visiting Scientist at the IBMT. J. Watson Research Center, Yorktown Heights, NY. His scientific interestsare in the area of: a) solid state devices and b) ICs design and testing. Inthe field of solid state devices, he has worked on SiOphysics, quantumeffects, charge transport through thin SiOstructures, charge trapping in SiO,oxide breakdown and reliability, MOS measurements techniques, thin-oxideproperties, and nonvolatile memories characterization. In the field of ICsdesign and testing, instead, he has worked on signature analysis testing, designfor testability techniques, fault modeling and fault simulation, IDDQ testing,self-checking circuits, and nonvolatile memory testing.