computer organization Unit3c

8/3/2019 computer organization Unit3c

1/51

OBJECTIVES

Controlling Device RequestsExceptions

Direct memory Access (DMA)

Bus ArbitrationBuses


2/51

CONTROLLING DEVICE REQUESTS

Till now, we have seen that an I/O device interfacegenerates an interrupt request, whenever the SINflag is equal to 1.

It is important to ensure that interrupt requests aregenerated only by those devices that are being usedby a given program.

Other devices must not be allowed to generate

interrupt requests.

So, we need a mechanism to control whether adevice is allowed to generate an interrupt request.


3/51

The control needed is provided in the form of aninterrupt-enable bit in the device's interface circuit.

KEN & DEN flags in control register perform thisfunction.

If either of these flags is set along with SIN/SOUTflags in status register, the interface circuit

generates an interrupt request.

At the same time, the interface circuit sets bit KIRQDIRQ in status register to indicate that either of thecircuit is requesting an interrupt.

If an interrupt-enable bit is equal to 0 , the interfacecircuit will not generate an interrupt request,regardless of the state of the status flag.


4/51

Main program

Move #Line,PNTR

Clear EOLBitSet #2,CONTROLBitSet #9,PS...

Interrupt Service Routine

READ MoveMultiple R0-R1, -(SP)Move PNTR,R0MoveByte DATAIN,R1MoveByte R1,(R0)+Move R0,PNTR

CompareByte #$0D,R1Branch!=0 RTRNMove #1,EOLBitClear #2,CONTROL

RTRN MoveMultiple (SP)+,R0-R1Return-from-interrupt


5/51

To summarize , there are two independentmechanisms for controlling interrupt requests,

-At the device end , an interrupt-enable bit in acontrol register determines whether the device isallowed to generate an interrupt request.

- At the processor end, either an interrupt enablebit in PS register or a priority structure determineswhether a given interrupt request will be accepted


6/51

EXCEPTIONS

An interrupt is an event that causes the execution ofone program to be suspended and the execution ofanother program to begin.

So far, we have seen the interrupts caused by I/Odevices for I/O data transfer.

But, the interrupt mechanism is used in other situations.The term exception is used to refer an event thatcauses an interruption.


7/51

I/O interrupts are one example of an exception & nowwe will see few other kinds of exceptions.

Recovery from errorsComputers use a variety of techniques to ensure that allhardware components are operating properly.


8/51

For example

Error-checking code in the main memory, whichallows detections of errors in the stored data. If anerror occurs, the control hardware detects it andinforms the processor by causing an interrupt.

The processor may also interrupt a program if itdetects an error while executing the program. Forexample, an arithmetic instruction may attempt a

division by zero.


9/51

In response to interrupts, the processor executes theexception service routine.

This routine takes appropriate action to recover fromthe error, or to inform the user about it.

Exception processing begin immediately withoutcompleting the execution of the interruptedinstruction.


10/51

Debugging

The exception is used as an aid in debuggingprograms.

System software usually has a program called

debugger, which helps the programmer to finderrors in a program

The debugger uses exceptions to provide two

important facilities called trace and breakpoints.


11/51

EXCEPTIONS

Interrupts caused by anevent

TrapsFaults

Aborts

Helps Programmer tofind the errors

y Tracey Break points

Debugger


12/51

PRIVILEGE EXCEPTIONS

To protect the O.S. of a computer from beingcorrupted by the user programs, certain instructionscan be executed only when the processor is in thesupervisor mode.

Those instructions are called privileged instructions.

The processor is in the supervisor mode only whenexecuting O.S. routines.

An attempt to execute such an instruction will produce

a privilege exception, causing the processor to switchto the supervisor mode and begin executing anappropriate routine in the O.S.


13/51

DIRECT MEMORYACCESS

To transfer large blocks of data at high speed, analternative approach is used called DMA.

In which a special control unit is provided to transfer a

block of data directly between a device and thememory without continuous intervention by theprocessor.

Data transfers are performed by the control circuit that

is a part of the I/O device interface called DMAcontroller


14/51


15/51

DMA controller can transfer data without interventionof the processor, but its operation must be under thecontrol of a program executed by the processor.

To initiate the transfer of a block words, theprocessor sends the starting address, the number ofwords in the block and the direction of the transfer.


16/51

CPU tells DMA controller:-

- Read/Write- Device address- Starting address of memory block for data- Amount of data to be transferred

- CPU carries on with other work-DMA controller deals with transfer

- DMA controller sends interrupt when finished


17/51

DMA is implemented using a DMA controller

-Receives instructions from processor

-Processor gives details to the DMA controller

I/O device number

Main memory Starting address

Number of bytes to transfer

Direction of transfer (memoryp I/O

device, or vice versa)


18/51

On receiving this information, the DMA controllerproceeds to perform the requested operation.

Steps in a DMA operation

- Processor initiates the DMA controllerGives device number, memory buffer pointer,

Called channel initialization

Once initialized, it is ready for data transfer

- When ready, I/O device informs the DMA controllerDMA controller starts the data transfer process

Obtains bus by going through bus arbitration

Places memory address and appropriate controlsignals


19/51

- Completes transfer and releases the bus updatesmemory address and count value

- When the controller is ready to accept the nextblock for transfer, it sets the Done flag to 1.

- If more to read, loops back to repeat the process

- Notify the processor when done ,by setting Doneflag to 1.

- When Interrupt Enable IE bit is set to 1, controllerhas to raise an interrupt

- When IRQ bit is set to 1 , interrupt signal isreceived by the processor


20/51

REGISTERS IN DMA

IRQ IE R/W Done

Status andControl

Starting Address

Word Count

013031


21/51

- While the DMA transfer is taking place, the program that

requested the transfer cannot continue & the processor can

be used to execute another program.

- The program that requested the transfer is put in

the Blocked state .

- Once the data transfer involving DMA is done , then the

processor can return to the program that requested the

transfer


22/51

Processor Memory

Disk/DMAController

DMAController Printer

Disk DiskNetworkInterface

Keyboard


23/51

The status register can also be used to record other informationlike the transfer took place correctly or errors occurred.

Memory accesses by the processor and the DMA controller areinterwoven.

Request by DMA device for using the bus are given higher prioritythen processor request.

DMA controller will steal memory cycles from the processor &this interweaving technique is called Cycle Stealing.


24/51

Alternatively, the DMA controller may be given exclusive access tothe memory & this is known as Block or Burst mode.

Most DMA controllers incorporate a data storage buffer.

A conflict may arise if both the processor & a DMA controller or two

DMA controllers try to use the bus at the same time to access thememory.

To resolve this conflict bus arbitration procedure is implemented.


25/51

BUS ARBITRATION

BBSY

BG1 BG2 BG3

ProcessorDMA

Controller

1

DMAController

2BG1 BG2

BR


26/51

CENTRALIZED BUSARBITRATION

The bus arbiter may be the processor or a separate unit connectedto the bus.

One bus-request line and one bus-grant line form a daisy chain.

This arrangement leads to considerable flexibility in determiningthe order.


27/51

DISTRIBUTED BUSARBITRATION

All devices have equal responsibility in carrying outthe arbitration process.

Each device on the bus assigned an identificationnumber.

Place their ID numbers on four open-collector lines.

A winner is selected as a result.

The connection performs an OR function in whichlogic 1 wins


28/51

For Ex :

Device A - 0101

Device B 0110

-Now the code seen by both the devices is 0111- Each device compares the pattern from most significant bit.

-- Device A detects a difference in the on line ARB1 , Sodisables its drivers on ARB1 and ARB0


29/51


30/51

BUSES

The processor, main memory & I/O devices areinterconnected by means of a common bus.

The primary function of a bus is to provide acommunication path for data transfer.

The bus protocols are used for transferring data

The bus consists of three lines: address, data &

control.


31/51

The control signal specifies R/W operation & the requiredsize of data (byte, word or long word)

The bus control signals also carry timing information.

This specifies the times at which the processor & the I/Odevices may place/receive data on the bus.

The device that initiates data transfer by issuing read orwrite commands on the bus is called as bus master or theinitiator.


32/51

Normally, the processor/DMA Controller acts as

the master.

The device addressed by the master is referredas a slave or target.

The schemes for the timing of data transferover the bus are classified as synchronous orasynchronous schemes.


33/51

SYNCHRONOUS BUSIn this scheme, all the devices derive timing

information from a common clock time.


34/51

SYNCHRONOUS BUS

The equal time intervals constitute a buscycle during which one data transfer can takeplace.

At t0, the master places the device addressand command on the respective lines.

Information travels over the bus at a speed

determined by its physical and electricalcharacteristics.


35/51

The clock pulse width t1-t0, must be longenough than the maximum propagation delay

between two devices + address and controldecode time.

So that the addressed device (slave) can

respond at t1.

The slave places the requested input data onthe data lines at t1.

At the end of bus cycle at t2, the mastercaptures the data on the data lines and storeinto its input buffer.


36/51

Hence, the period t2-t1 must be greater thanthe maximum propagation time - the setup

time of the input buffer register of the master.

A similar procedure is followed for an outputoperation.

The exact times at which signals appear on thebus are somewhat different from those shown.

Because of propagation delays on the bus wiresand in the circuits of the devices as shown.


37/51


38/51

The period t2-tDM is the setup time for themasters input buffer.

The data must continue to be valid after t2 for aperiod equal to the hold time of that buffer.

The processor has no way of determiningwhether the addressed device has respondedor not.

It simply assumes that at t2, the data isavailable on the data lines.


39/51

If, because of a malfunction , the devicedoes not respond, the error will not be

detected.

To overcome, these limitations, most buseshas control signals that represent a response

from the device.

These signals inform the master that theslave has recognized its address and it is

ready for data transfer.


40/51

A high-frequency clock signal is used such thata complete data transfer cycle would take

several clock cycles and are called multiple-cycle transfers.

The member of clock cycles can vary from one

device to another.


41/51

MULTIPLE-CYCLE

TRANSFERS.

Multiple Cycle Transfer


42/51

The slave-ready signal is an ACK from the slaveto the master, confirming that valid data have

been sent.

In above example, the slave responds in cycle3, another device may respond sooner or later.

If the slave does not respond at all, the masterwaits for some predefined number of clockcycles, then aborts the operation resulting in a

device malfunction or an incorrect address.


43/51

The clock signal used on a computer bus is notsame as the processor clock.

The processor chips, clock frequencies isabove 500MHz.

The memory & I/O buses, the clock frequencymay be in the range 50 to 150 MHz.

So many computer buses uses a multiple-cycle

transfer schemes to control the transfer of data.


44/51

ASYNCHRONOUS BUS.

Asynchronous scheme for controlling datatransfers on the bus is based on the

handshake between the master & the slave.

The common clock is replaced by two timingcontrol lines, Master-ready & Slave-ready.


45/51

ASYNCHRONOUS BUS.


46/51

T

he delay t1-t0 is intended to allow for any skewthat may occur on the bus.

Skew occurs when two signals simultaneously

transmitted from one source, arrive at thedestination at different times.


47/51

t0 The master places the address and commandinformation on the bus, and all devices on the bus begin

to decode this information.

t1 The master sets the Master-ready line to 1 to informthe I/O devices that the address and commandinformation is ready. The delay t1-t0 is intended to allow

for any skew that may occur o the bus. Skew occurs whentwo signals simultaneously transmitted from one sourcearrive at the destination at different times. This happensbecause different lines of the bus may have differentpropagation speeds. Thus, to guarantee that the Master-

ready signal does not arrive at any device ahead of theaddress and command information, the delay t1-t0 shouldbe larger than the maximum possible bus skew.


48/51

t2 The selected slave, having decoded the addressand command information performs the required input

operation by placing the data from its data register onthe data lines.

t3 The Slave-ready signal arrives at the master,indicating that the input data are available on the bus.

t4 The master removes the address and commandinformation from the bus. The delay between t3 and t4is again intended to allow for bus skew.

t5 When the device interface receives the 1 to 0transition of the Master-ready signal, it removes thedata and the Slave-ready signal from the bus. Thiscompletes the input transfer.


49/51

A change of state in one signal is followed by achange in the other signal . This scheme is known asa full handshake .

Advantages of Asynchronous bus :

-Eliminates the need for synchronization of the senderand receiver clocks , simplifying timing design.

-- For a synchronous bus ,clock circuitry must bedesigned to ensure proper synchronization anddelays must be kept within strict bounds

Disadvantages of Asynchronous bus :

Each transfer involves two round-trip delays, astransition on Slave-ready must wait for the arrival of atransition on Master-ready and vice versa


50/51

EXPECTED QUESTIONSHow the interrupt requests from different I/O devicesare controlled.

What is an Exception? Explain different types of

Exceptions.


51/51

THANK YOU

Documents

computer organization Unit3c