Computer OrganizationCS224

Fall 2012

Lessons 7 and 8

addi $sp, $sp, 4 #$sp = $sp + 4

slti $t0, $s2, 15 #$t0 = 1 if $s2<15

Machine format (I format):

MIPS Immediate Instructions

0x0A 18 8 0x0F

Small constants are used often in typical code

Possible approaches? put “typical constants” in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants !

The constant is kept inside the instruction itself! Immediate format limits values to the range +215–1 to -215

§2.5 Representing Instructions in the C

omputer

More than one instruction format?

Remember Design Principle #1: Simplicity favors regularity (regularity => simplicity => clean implementation and fast performance)

Thus, ISA designers would like to keep just one instruction format

But to accommodate reasonable-size constants, field width of more than 5-bits is needed (addi, lw, sw,…)

Also, ISA designers would like to keep all instructions the same length

The compromise was to add a new instruction format (I-type), with 16-bit constant field

Design Principle #4: Good design demands good compromises

MIPS (RISC) Design Principles

Simplicity favors regularity fixed size instructions small number of instruction formats opcode always the first 6 bits

Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes

Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands

Good design demands good compromises e.g. 3 instruction formats, size of register file

Logical Operations

Instructions for bitwise manipulation

Operation C Java MIPS

Shift left << << sll

Shift right >> >>> srl

Bitwise AND & & and, andi

Bitwise OR | | or, ori

Bitwise NOT ~ ~ nor

Useful for moving, extracting and inserting groups of bits in a word

§2.6 Logical Operations

Shift Operations

shamt: how many positions to shift

Shift left logical Shift left and fill with 0 bits sll by i bits multiplies by 2i

Shift right arithmetical Shift right and fill with sign bit sra by i bits divides by 2i (signed numbers)

op rs rt rd shamt funct

6 bits 6 bits5 bits 5 bits 5 bits 5 bits

MIPS Shift Operations Need operations to pack and unpack 8-bit characters into

32-bit words, e.g. to isolate bits 23-16 from $s0[31:0], do:

Shifts move all the bits in a word left or right

sll $t2, $s0, 8 #$t2 = $s0 << 8 bits

srl $s0, $t2, 24 #$s0 = $t2 >> 24 bits

Instruction Format (R format)

Such shifts are called logical because they fill with zeros

Notice that a 5-bit shamt field is enough to shift a 32-bit value 25 – 1 or 31 bit positions

0 16 10 8 0x00

MIPS Logical Operations There are a number of bit-wise logical operations in the

MIPS ISA

and $t0, $t1, $t2 #$t0 = $t1 & $t2

or $t0, $t1, $t2 #$t0 = $t1 | $t2

nor $t0, $t1, $t2 #$t0 = not($t1 | $t2)

Instruction Format (R format)

andi $t0, $t1, 0xFF00 #$t0 = $t1 & ff00

ori $t0, $t1, 0xFF00 #$t0 = $t1 | ff00 Instruction Format (I format)

0 9 10 8 0 0x24

0x0D 9 8 0xFF00

OR Operations

Useful to include bits in a word Set some bits to 1, leave others unchanged

or $t0, $t1, $t2 # $t1 is the “OR mask”

0000 0000 0000 0000 0000 1101 1100 0000

0000 0000 0000 0000 0011 1100 0000 0000

$t2

$t1

0000 0000 0000 0000 0011 1101 1100 0000$t0

AND Operations

Useful to mask bits in a word Clear some bits to 0, leave others unchanged

and $t0, $t1, $t2 # $t1 is the “AND mask”

0000 0000 0000 0000 0000 1101 1100 0000

0000 0000 0000 0000 0011 1100 0000 0000

$t2

$t1

0000 0000 0000 0000 0000 1100 0000 0000$t0

NOT Operations

Useful to invert bits in a word Change 0 to 1, and 1 to 0

MIPS has NOR 3-operand instruction a NOR b == NOT ( a OR b )

nor $t0, $t1, $zero

0000 0000 0000 0000 0011 1100 0000 0000$t1

1111 1111 1111 1111 1100 0011 1111 1111$t0

Register 0: always read as zero

Conditional Operations

Branch to a labeled instruction if a condition is true Otherwise, continue sequentially

beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1;

bne rs, rt, L1 if (rs != rt) branch to instruction labeled L1;

j L1 unconditional jump to instruction labeled L1

§2.7 Instructions for Making D

ecisions

MIPS conditional branch instructions:

bne $s0, $s1, Ll #go to Ll if $s0$s1 beq $s0, $s1, Ll #go to Ll if $s0=$s1

Ex: if (i==j) h = i + j;

bne $s0, $s1, L1add $s3, $s0, $s1

L1: ...

MIPS Control Flow Instructions

Instruction Format (I format):

0x05 16 17 16 bit offset

How is the branch destination address specified?

Specifying Branch Destinations Use a register (like in lw and sw) added to the 16-bit offset

which register? Instruction Address Register (the PC)- its use is automatically implied by instruction

- PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction

limits the branch distance to -215 to +215-1 (word) instructions from the (instruction after the) branch instruction, but most branches are local anyway

PCAdd

32

32 3232

32

offset

16

32

00

sign-extend

from the low order 16 bits of the branch instruction

branch destaddress

?Add

4 32

Compiling If Else Statements

C code:

if (i==j) f = g+h;else f = g-h;

f, g, … in $s0, $s1, …

Compiled MIPS code:

bne $s3, $s4, Else add $s0, $s1, $s2 j ExitElse: sub $s0, $s1, $s2Exit: …

Assembler calculates addresses

Compiling Loop Statements C code:

while (save[i] == k) i += 1;

i in $s3, k in $s5, address of save in $s6

Hand “compiled” MIPS code:

Loop: sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, 1 j LoopExit: …

An optimizing compiler will reduce this loop from 6 instructions to 3 (50% speedup). How?

Bottom test_&_branching (back up, or out) saves 1t1<- t1+4 (instead of sll, add, & addi) saves 2

We have beq, bne, but what about other kinds of branches (e.g., branch-if-less-than)? For this, we need yet another instruction, slt

Set on less than instruction:

slt $t0, $s0, $s1 # if $s0 < $s1 then# $t0 = 1 else # $t0 = 0

Instruction format (R format):

Alternate versions of slt

slti $t0, $s0, 25# if $s0 < 25 then $t0=1 ...

sltu $t0, $s0, $s1 # if $s0 < $s1 then $t0=1 ...

sltiu $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...2

In Support of Branch Instructions

0 16 17 8 0x24

Signed vs. Unsigned

Signed comparison: slt, slti

Unsigned comparison: sltu, sltui

Example $s0 = 1111 1111 1111 1111 1111 1111 1111 1111 $s1 = 0000 0000 0000 0000 0000 0000 0000 0001

slt $t0, $s0, $s1 # signed

- –1 < +1 $t0 = 1 sltu $t0, $s0, $s1 # unsigned

- +4,294,967,295 > +1 $t0 = 0

More Branch Instructions Can use slt, beq, bne, and the fixed value of 0 in

register $zero to create other conditions less than blt $s1, $s2, Label

less than or equal to ble $s1, $s2, Label greater than bgt $s1, $s2, Label great than or equal to bge $s1, $s2, Label

slt $at, $s1, $s2 #$at set to 1 ifbne $at, $zero, Label #$s1 < $s2

Such branches are included in the instruction set as pseudo-instructions. These are recognized (and expanded) by the assembler

Its why the assembler needs a reserved register ($at)

Branch Instruction Design

Why not include blt, bge, etc in the actual MIPS ISA?

Hardware for <, ≥, … slower than =, ≠ Combining with branch involves more work per instruction,

requiring a slower clock All instructions would be penalized!

beq and bne are the common case (Principle #3)

This is a good design compromise (Principle #4)