Computer Firmware Design Projects for Undergraduate Students

IEEE TRANSACTIONS ON EDUCATION, VOL. E-27, NO. 1, FEBRUARY 1984

Computer Firmware Design Projectsfor Undergraduate Students

CHARLES W. MERRIAM, FELLOW, IEEE

Abstract-A laboratory-based approach is described for making adiversified set of computer firmware design projects available to largegroups of undergraduate students at a modest cost. All essential functionsare provided as common resources to students. Support functions are madeavailable inexpensively by use of either a minicomputer or a microcom-puter. The computer provides interactive operating and testing aids byissuing prompts for students, loads micromemory and macromemory,initializes program counters for microcode and macrocode, and diagnosesinput/output errors. A general-purpose programmable microsequencerfunctions as a control unit. Students make no electrical connections to thesystem when a macroprocessor is added for computer emulation purposes.However, when the system is used for projects which do not employ amacroprocessor, a number of hardware input and output ports are used bystudents to design a variety of microprogram-controlled devices. A briefdescription of hardware designed to implement the programmable micro-sequencer and macroprocessor is given in the Appendixes.

I. INTRODUCTIONT HE goal of making a diversified set of computer

firmware design projects available to large groups ofundergraduates at a modest cost can be achieved as follows.Use of existing minicomputers or microcomputers in alaboratory setting permits the implementation of requiredhardware resources in an economical fashion. These re-sources can, in addition, be used by large numbers ofstudents under two conditions. First, all hardware designedby students is self-contained and portable. Second, allcomputer program preparation by students is performed oncentral campus computing facilities. This approach is usedfor computer hardware design projects at the Universityof Rochester [1]. The approach is also applied easily tocomputer firmware design projects using hardware de-scribed briefly in Appendixes A and B.

Microprogramming design techniques generally are asso-ciated with control units of modern computers which areimplemented with microprocessor slices [2]. Detailed infor-mation is available from manufacturers, such as AdvancedMicro Devices [3], on the microprogramming approach tocomputer design. Microprogrammable machines, such asthose reported by Roth and Minassion [4] and by Purvis etal. [5], have been built for use by students in courses andprojects that involve firmware design for computer emula-tion purposes. A key objective of the approach describedhere, however, is to involve students in design of hardware tobe controlled by microprogramming techniques. For exam-

Manuscript received April 5, 1983; revised August 8, 1983.The author is with the Department of Electrical Engineering, University

of Rochester, Rochester, NY 14627.

ple, the microprocessor-slice portion of a host computer,such as described in Appendix B, represents such a designproject. The programmable microsequencer described inAppendix A is used for microprogrammed control of allsuch hardware including macroprocessors.Microprogramming design techniques are also used

widely in many modern instruments such as spectrum andlogic analyzers, in "smart" computer interfaces for periph-erals such as floppy disks, and in controllers for devices suchas CRT terminals with editing capabilities. The program-mable microsequencer described in Appendix A can also beused in a flexible manner for these types of firmware designprojects by adding whatever special-purpose hardware isappropriate for a particular design project.

Microprogramming design techniques can further be usedin a novel fashion for prototyping the digital-control portionof high-speed data acquisition systems employing discrete-time devices with analog signals. Specifically, systems em-ploying charge-coupled devices, such as photodiode arrays,correlators, and programmable transversal filters, requirecomplicated count sequences for control purposes. Thesecount sequences also depend upon the particular mode ofoperation being employed. See, for example, Howes andMorgan [6] for a description of these charge-coupled devicesand their applications. Moreover, very high frequenciesnormally are employed to clock these discrete-time devices.Therefore, prototyping the required digital circuitry for var-ious applications is difficult and often very time-consumingwithout the use of microprogramming techniques. Theprogrammable microsequencer described in Appendix A isespecially well-suited to perform this prototyping functionwhile simultaneously buffering digitized analog signals foreventual processing in the minicomputer.

II. PROJECTS FOR MICROPROGRAMMINGCOMPUTER PERIPHERALS

One specific class of microprogramming projects that canbe implemented in a low-cost fashion for numerous studentsentails interfacing computer peripherals and also upgradingthese devices to exhibit various "smart" characteristics. Thehardware that must be added to each laboratory workstation employing a programmable microsequencer gener-ally is inexpensive and involves few components and inter-connections. Such hardware, therefore, can be dedicated toeach available work station so students do not have anydirect hardware design responsibilities. However, studentsshould have previously completed a course on logic design

0018-9359/84/0200-0014$01.00 © 1984 IEEE

14

MERRIAM: COMPUTER FIRMWARE DESIGN PROJECTS

which includes circuit techniques for converting serial datainto parallel form, and vice versa. Students must also havesome assembly language programming experience prior toundertaking one of these projects.

Perhaps the least expensive and most educational projectof this type is the design of a microprogrammed front-panelfor the previously described microsequencer. The mainhardware components used at the University of Rochesterfor this purpose are as follows.

1) A low-cost Burr-Brown TM25 computer terminalwhich has an 8-digit hexadecimal display and a keyboardwith keys for 16 hexadecimal digits and 7 functions. Thisterminal functions as a standard RS232 interface at either110 or 300 baud.

2) A programmable USART such as the Intel 8251A/S2657.

3) A baud rate generator such as the Motorola Kl 135A.Little else, except a few tristate noninverting buffer gates, isrequired for this project.

Students are asked to write microcode necessary to makethis simple computer terminal function as a console devicefor the programmable microsequencer while microinstruc-tions are being executed by the micromemory controller forusers. To do this, students must adopt uniform conventionsfor making the service routine for the console device and theroutine of another user function as two concurrent cooperat-ing firmware processes.

Students may also be asked to write the additionalmicrocode necessary to supervise all communications be-tween the minicomputer and the microsequencer. Thesecommunications serve the purposes of loading macrocode,initializing a macroprogram counter, and activating theinput/ output system of the minicomputer under user micro-program control. The final result of meeting these require-ments is a complete computer system for prototypingmicroprograms.A typical student project of this type involves approxi-

mately 330 lines of microcode when console functions, suchas the following, are implemented.

1) Load console address register.2) Increment console address register.3) Read console address register.4) Load macromemory word.5) Read macromemory word.6) Load microcontroller register.7) Read microcontroller register.8) Turn on single-step mode for executing user micro-

instructions.9) Turn off single-step mode for executing user micro-

instructions.10) Start execution of user microinstructions.11) Resume execution of user microinstructions.12) Transfer front-panel control to minicomputer console

device.A somewhat more expensive, but related, project is the

design of a microprogrammed controller for a keyboard andCRT device which are to function as a computer terminal.Few additional hardware components are needed even for

this project because macromemory of the programmablemicrosequencer described in Appendix A can be used as adual-purpose refresh memory and character generator.Microcode for such a controller requires in the neighbor-hood of 512 lines of microcode. Substantial screen-editingcapabilities can also be implemented using the remaining 512or so lines of microcode.Numerous design projects of the type described here can

be readily implemented depending upon availability of thedesired computer peripheral. At the University of Rochester,approximately 20 students at the junior/ senior level can beassigned to each laboratory work station with dedicatedhardware for such projects. Two such work stations are usedcurrently. In order to succeed with this rather large numberof students, central campus computing facilities must beused by students for writing and assembling both micro-programs and macroprograms.

III. PROJECTS FOR MICROPROGRAMMING COMPUTERS

Another class of microprogramming projects requiresstudents to microprogram computers with various instruc-tion sets. One form of this assignment is to microprogram anemulation of some existing minicomputer or microcompu-ter. This project requires less student preparation than theprojects described previously for computer peripherals. Inparticular, logic design is no longer a prerequisite.

Another form of this assignment is used at the Universityof Rochester. Specifically, students are held responsible fordesigning registers and instruction sets of their computers, aswell as writing microcode to implement their computersefficiently on hardware made available to them. This projectresults in a more sophisticated understanding of relation-ships between computer architecture and computer organi-zations based on microprogramming techniques. Such firm-ware design projects are very well-suited as the prerequisitefor hardware design projects described in Merriam [1].The firmware design projects used at the University of

Rochester for microprogramming computers are subdividedinto the following three phases:

1) design of computer registers and instruction set;2) implementation and checkout of computer;3) documentation of computer for macroprogramers.These computer design projects are posed to students in

terms of various architectural constraints. For example, aversion of the constraints given in Merriam [1] can be usedbut expanded in a number of significant ways such as

1) direct addressing of 4096 main memory words;2) inclusion of at least 4 addressing modes such as

immediate, register-to-register, register-to-memory, andregister-to-indexed-memory;

3) inclusion of signed-integer multiply and divide in-structions.Usually students are allowed to employ no more than 512lines of microcode for these design projects in order to forcethem into making difficult decisions about various archi-tectural tradeoffs.

In order to give students somewhat more definitiveguidance during the architectural design phase of these

15

IEEE TRANSACTIONS ON EDUCATION, VOL. E-27, NO. 1. FEBRUARY 1984

projects, they are required to adopt one of a number ofclearly stated design objectives. For example, appropriateamplifications of one of the following general criteriasuffices.

1) Maximal speed of fetching, decoding, and executingmacroinstructions.

2) Conceptual simplicity and regularity of macroinstruc-tions and their formats.

3) Simplicity and efficiency of macroprogramming at theassembly language level for specific applications.

4) Maximal utilization of hardware resources.Student designs are graded in accordance with one of theabove general criteria. Student designs are also graded basedon performances of the computers when executing a bench-mark macroprogram.

IV. TYPICAL STUDENT COMPUTERS

Computers designed by students have widely varyingcharacteristics, and hence are rather difficult to describe in asuccinct and meaningful way. However, a benchmark micro-programmed computer has been devised as an aid forgrading student design projects. This particular benchmarkcomputer is intended to exhibit maximal speed for decodingand executing macroinstructions and to illustrate an efficientutilization of hardware resources. The hardware resourcesavailable to students are summarized briefly in AppendixesA and B.The benchmark computer makes all 16 registers of the

macroprocessor available to the macroprogrammer for 8-bitdata words in the architectural form of a general-registermachine. These 16 general-purpose registers can also beemployed in double-length pairs Rm, Rn where m = n + 1and n = 0, 2, * - *, 14 for manipulating 12-bit macromemory-address words. In addition, double-length shifting can beaccomplished because the macroprogrammer is also givenaccess to an additional internal register for shift purposes.All arithmetic-logic functions of the macroprocesor areutilized by this benchmark computer.One register of the micromemory controller is used as a

dedicated register for storing computer status. The macro-programmer is given access to this status register which isupdated only when arithmetic and shift macroinstructionsare executed. Three other registers of the microcontroller arealso used for various microprogramming purposes. Theremaining four registers of the microcontroller are not usedfor this particular computer. These remaining registers,therefore, are available for more sophisticated computerdesigns. For example, these registers could be used asmacromemory pointers for implementing macroinstructionsthat operate on stack or queue data-structures.

All arithmetic-logic functions of the micromemory con-troller are also used throughout the microcode for thiscomputer. These functions prove to be particularly efficientfor macromemory-address computations needed for macro-instructions. The barrel shifting and rotating functions oftheparticular microcontroller used are found to be very con-venient. These features of the microcontroller result in theefficient implementation of fast-shift and fast-rotate instruc-

tions where the number of bit positions is specified by animmediate count field.

Characteristics of the 72 instructions of this target ma-chine are summarized very briefly as follows. Data wordswith 8 bits and address words with 12 bits form operands forthese instructions. Instructions have from zero to threeoperands, and an operand is located by one of six addressingmodes. Instruction length varies from 8 to 32 bits, but allbasic register-to-register instructions have a length of 16 bits.General categories of instructions are summarized in TableI. The data movement category includes two instructions ofthe multiple-register type, and the shift-rotate categoryincludes three instructions of the fast type. Cycle times for allregister-to-register instructions in the arithmetic, logic, andshift-rotate categories vary from 1.25 to 1.50 ,us.Complete microcode for this benchmark computer re-

quires 502 micromemory words. Hence, the hardwaredescribed briefly in Appendixes A and B is demonstrablycapable of implementing a large class of powerful 8-bitcomputers. Details of this benchmark computer and com-plete microcode for it are available from the author uponrequest. Moreover, all reports cited in Appendixes A and Bfor the hardware designed at the University of Rochester toimplement these firmware design projects are available fromthe author upon request.

V. CONCLUSIONSThe addition of a properly designed programmable micro-

sequencer to either a minicomputer or a microcomputerresults in a laboratory facility for teaching firmware design.This facility functions much in the way that a small dedicatedcomputer functions for teaching software design. Firmwaredesign projects can, therefore, be offered to a relatively largenumber of students.Moreover, the laboratory setting in which these small

computer systems are employed is essential to offering somefirmware design projects. Namely, projects that involveoperational control of and data communications withphysical devices require laboratory access. The small incre-mental cost of dedicated hardware that can be added to theprogrammable microsequencer described in Appendix Amakes possible implementation of multiple laboratory workstations for a variety of these firmware design projects.

APPENDIX APROGRAMMABLE MICROSEQUENCER

A microprogrammable device [8] was designed at theUniversity of Rochester for the purpose of sequencingmicroinstructions under the supervisory control of a mini-computer. This device is referred to as a programmablemicrosequencer and is organized as depicted in Fig. 1. Theprogrammable microsequencer shown in Fig. 1 performs anumber of vital functions which are summarized brieflyhere.

A. Addressing MicromemoryPerhaps the central issue in the design of a micropro-

grammable device is selection of addressing mechanisms for

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TABLE IINSTRUCTION CATEGORIES OFBENCHMARK COMPUTER

Number ofInstruction Category Instructions

Data movement 17Program control 13Arithmetic 14Logic 12Shift-rotate 11Input-output 5

INTERDATA

USER

Fig. 1. Organization of the programmable microsequencer.

micromemory. As shown in Fig. 1, micromemory CS iscomposed of 1024 36-bit words and is addressed in one oftwo ways. Address register AR is used either when micro-memory is being loaded or when an interrupt is beingserviced under control of the minicomputer. Alternatively,micromemory is addressed by the Signetics 8X300 micro-controller when the interface functions as a microsequencer.

Selection of the Signetics 8X300 microcontroller forsequencing microinstructions wts based on a number ofconsiderations. These considerations are summarized brieflyhere in terms of the timing diagram given in Fig. 2 formicroinstruction execution. A more detailed account of the8X300 is given in Signetics [7].

The chief organizational feature of the 8X300 utilized inthe microsequencer is the fetch-modify-deposit cycle per-formed on all 8X300 instructions involving data movement.During state SI indicated in Fig. 2, a source operand isselected and fetched, usually via the 8X300 bus IVB, forpossible modification in the 8X300. Fetching also mayinvolve rotation and masking of the source operand. Then,during state S2 indicated in Fig. 2, the resulting sourceoperand may be modified by one of a small number ofarithmetic-logic functions involving a second operand storedin a register of the 8X300. Next, during state S3 indicated inFig. 2, the result of the arithmetic-logic function employed instate S2 may be shifted, masked, and then merged with the

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|=62 ns-H 62 ns_

Si S2 S3 S4

Fig. 2. Timing diagram for microinstruction execution.

source operand to form a result. This result is finallydeposited, usually via the 8X300 bus IVB, in the destinationlocation selected for the result. Microprogram control bits,in addition to the 8X300 instruction being executed, selectone of eight operand sources and one of eight resultdestinations connected to the 8X300 bus IVB. Eight internalregisters of the 8X300 may also be selected as source

operands and result destinations by these microprogramcontrol bits and the 8X300 instruction being executed.

These data movement and data modification attributes ofthe 8X300 enable the microsequencer to function in a varietyof microprogramming applications without additional reg-ister and arithmetic-logic functions typically supplied bymicroprocessor slices. The 8X300 micromemory controlleralso includes a move-immediate instruction for transferringliterals from the microinstruction stream to the data stream,usually via the 8X300 bus IVB. The need to store literals ininternal registers of the 8X300, thereby, is largely avoided. Inaddition, the 8X300 micromemory controller sequencesexecution of microinstructions. The normal sequence corre-

sponds to incrementing an internal microprogram counter.Other sequences occur when the 8X300 executes either a

jump, a conditional jump-relative, or an execute-relativeinstruction. These control mechanisms for sequencing mi-croinstructions have proved to be very satisfactory formicroprogramming purposes, except in unusual situationswhere the need for microcode compaction would result inthe nesting of subroutine calls.

Each 8X300 instruction is 16 bits wide so that only one

micromemory fetch is required per microinstruction exe-

cuted. The 8X300 microcontroller is clocked by the active-low clock signal CK which is shown in Fig. 2. In addition, the8X300 microcontroller emits an active-low strobing signalCLK, which is also shown in Fig. 2. Microinstructions are

fetched at the beginning of state S I and hence also at the endof state S4. Therefore, execution of each microinstructionrequires approximately 250 ns.

State S4 is used for clocking hardware external to themicrosequencer before the end of each microinstruction exe-

cution cycle. For example, signal CP shown in Fig. 2 isgenerated easily from signals CK and CLK and can be usedfor clocking results into destination registers. The resultingfour-state microinstruction execution cycle is very fast,requires only one line of microcode, and is free of timingconsiderations. The microinstruction sequencer depicted inFig. 1, therefore, exhibits high performance and is easy tomicroprogram by novices such as undergraduate students.

B. Addressing MacromemoryMacromemory MS is composed of4096 8-bit words and is

also addressed in one of two ways. In particular, eitherdual-purpose register LR/WR or register BR shown in Fig.1 can be selected under microprogram control as an addressregister for macromemory. Base register BR is intended topoint to macromemory data. This register is implemented asa counter so it can also be incremented conditionally on eachmicroinstruction execution cycle under microprogram con-trol. The location-register LR purpose of LR/WR is to pointto macromemory instructions when macroprocessor slicesare connected to the microsequencer for computer emula-tion purposes. Register LR/WR is also implemented as acounter so it can be incremented conditionally on eachmicroinstruction execution cycle under microprogramcontrol.The alternate purpose of LR/WR, namely as a word-

count register WR, is to use registers WR and BR togetherfor high-speed buffering of macromemory data in a mannertypical of input/ output data channels. As indicated in Fig. 3,micromemory address-select line IAS is activated so that ARpoints to the next microinstruction to be executed whencarryout CO occurs as a result of incrementing LR/WR withmicroprogram control bit ILR high. In other words, an in-terrupt is generated at the end of data buffering so that nooverhead microsequencer cycles need be incurred duringdata buffering. Hence, up to 4096 8-bit data words can betransferred either into or out of macromemory at the rate offour million 8-bit words per second. This feature makes themicrosequencer described here suitable for many applica-tions involving high-speed data acquisition.

C. User Ports

User input and output ports of the programmable micro-sequencer are also shown in Fig. 1.

Output ports to the user include micromemory registerMR and data registers OR and CR. These registers areconnected to the 8X300 micromemory controller via its busIVB. Correspondingly, the user has access to 11 micropro-gram control bits at port COM as well as to 8 data bits atboth ports OUT and CON.

Input ports from the user and are connected to the 8X300micromemory controller via its bus IVB. In particular, theuser can enter 8 bits of input data via port IN and can enter 4bits of status information via active-low port SEN.

Input ports IN and active-low SEN and output ports ORand CR comprise the minimal set of ports required tomicroprogram bidirectional communications. For example,these ports permit communications with an auxiliary com-

18


W:INSTRUCTK)N n

CLK

11

..lI

liI1;

111Il1:I

IA,,

INSEiCTION FOR MOVINGNEXT-1O-ASW DATA BYTE

ffi INSTRUCTION n + 1 INSTRUCTION n + 2 j

I Lj L2I } I____

l' I{ ,____

I

I LLINSTRUCTION FOR MOVING FIRST INSTRUCTION IN

LAST DATA BYTE INTERRUPT-SERVICE ROUTINE,

1 J

Fig. 3. Timing of data buffering using an interrupt.

puter that can be structured to function as a macroprocessor

for this microsequencer. The resulting hardware then formsa complete host machine which is microprogrammable forcomputer emulation purposes. Alternatively, these portspermit direct communications with any number of input/output computer peripherals including mass-store devices.

D. Communications with the MinicomputerAs indicated in Fig. 1, the programmable microsequencer

communicates back and forth with a minicomputer, whichhappens to be either an Interdata 6/16 or 7/16 at theUniversity of Rochester. Communications with a minicom-puter are intended primarily to utilize the minicomputer as

an input/output system with secondary memory and pro-cessing capabilities.

Another significant design decision is the centralization ofall input/output functions in the minicomputer. All consolefunctions can then be centralized in the minicomputer so

that the entire system functions under operating systemcontrol. Microcode and macrocode checkout, therefore, canbe performed interactively under control of the operatingsystem and a service routine that reside in the minicomputer.These software mechanisms also are used to load microcodeand macrocode and to initialize the microprogram counterin the 8X300 and the macroprogram counter LR.

Output data are transmitted to the minicomputer via dataregister DR which is connected to the 8X300 bus IVB. Inputdata are transmitted similarly from the minicomputer di-rectly to the 8X300 bus IVB. Processing of this input andoutput data thus is performed under microprogram control.

Synchronization and sequencing of data transfers betweenthe minicomputer and the microsequencer are accomplishedusing busy-done circuitry corresponding to the state-transi-tion diagram given in Fig. 4. State changes indicated in this

diagram correspond to cooperative actions taken by theservice routine residing in the minicomputer and by micro-code residing in the microsequencer. Specifically, commandsissued from the minicomputer, via active-low port CMDshown in Fig. 1, cause reset and start transitions. Thesetransitions reset the microprogram counter to 0 and startexecution of microinstructions, respectively. A micropro-gram control bit is used to cause transition stop undermicroprogram control so that execution of instructions bythe 8X300 is stopped.

Flip-flop outputs busy and done, used to implement thestate-transition diagram given in Fig. 4, form two internalinputs to sense registers SR. This register is used to transmitstatus information to the minicomputer. A number of simpleprotocols can thus be implemented for communicating backand forth with the minicomputer using this busy-donecircuitry.

APPENDIX BMACROPROCESSOR

A complete host machine must be available as dedicatedhardware at each laboratory work station if approximately20 students are to be assigned to each work station. A very

simple but adequate processor [9] is connected to theprogrammable microsequencer for this purpose at the Uni-versity of Rochester.

This processor is constructed with 2 Am2901 micropro-cessor slices as indicated in Fig. 5. Complete details forthese microprocessor slices are given by the manufacturer[3]. Microsequencer output registers OR and CR are usedfor Am2901 data inputs and register addresses, respectively.Microsequencer inputs IN and active-low SEN are savedusing data-buffer register DBR and status-buffer registerSBR, respectively. These buffer registers are clocked condi-

NOI*AL INSTRUCTION SEQUENCE INSTRUCTION FETCHED FROMADDRESS AR WHICH POINTS TOREMAINDER OF SERVICE ROUTINE

I

-.

19

11


BUSY = 0DONE = 0

BW=lDONE = O

BUSY = 0

DONE = 1

Fig. 4. Handshaking states of the programmable microsequencer.

Fig. 5. Organization of a microprogrammable processor.

length shifts are implemented in both left and right directionsusing Am2901 registers RAM and Q. Carry and shift inputs,namely CI and SI, respectively, are determined for theprocessor on each microinstruction execution cycle byrespective microprogram control bits.

Architecture of the complete host machine can now bedefined precisely using conventions of a microassemblersuch as the one available from Signetics [10]. Completearchitectural details of this machine are available in Merriam[I 1].

REFERENCES[I] C. W. Merriam, "Computer hardware design projects for under-

graduates," IEEE Trans. Educ., vol. E-26, pp. 77-85, Aug. 1983.[2] W. 1. Fletcher, An 1ngineering Approach to Digital Design. Engle-

wood Cliffs, NJ: Prentice-Hall, 1980.[3] J. Mick and J. Brick, Bit-Slice Microprocessor Design. New York:

McGraw-Hill, 1980.[4] C. H. Roth, Jr., and G. Minassion, "A bit-slice microprocessor system

for teaching microprogramming," IEEE Trans. Educ., vol. E-24, pp.119-122, May 1981.

[5] -. E. Purvis, R. D. Yoho, and G. B. Lamont, "MIME: An educationalmicroprogrammable minicomputer emulator," IEEE Trans. Educ.,vol. E-24, pp. 257-262, Nov. 1981.

[6] M. J. Howes and D. V. Morgan, Ed., Charge-Coupled Devices andSystems. New York: Wiley, 1978.

[7] Signetics 8X300 Programmable Manual, Signetics Corp., Sunnyvale,CA, 1978.

[8] C. W. Merriam, "UR8X300 prototyping system," Univ. Rochester,Rochester, NY, Apr. 1980.

[9] C. W. Merriam, "UR300 processor," Univ. Rochester, Rochester, NY,Aug. 1981.

[10] Signetics Micro Assembler Reference Manual, Signetics Corp.,Sunnyvale, CA, 1977.

[11] C. W. Merriam, UR302 Microprogrammer's Reference Manual,Univ. Rochester, Rochester, NY, Feb. 1982.

RAMODSSI so

RAMD:

RAMQL

Sl S OSo

soo s

Fig. 6. Shift linkages of the microprogammable processor.

tionally with signal CP shown in Fig. 2 on each microinstruc-tion execution cycle in accordance with a microprogramcontrol bit.

Shift linkages for this processor are implemented in

hardware as depicted in Fig. 6. Single-length and double-

Charles W. Merriam (M'59-SM'73-F84) was bornin Birmingham, AL, on March 31, 1931. He re-

ceived the Sc.B. degree (cum laude) in engineeringfrom Brown Upiversity, Providence, RI, and theM.S. and Sc.D. degrees from the MassachusettsInstitute of Technology, Cambridge, MA, in 1955ad 1958, respectively.He was an Assistant Professor of Electrical

Engineering at M.I.T. from 1958 to 1962, but hetook a leave of absence from M.I.T. to join theGeneral Electric Research Laboratory in 1959

where he remained until 1964. Frpm 1964 to 1971, he was a Professor ofElectrical Engineering at Cornell University, Ithaca, NY. In 1971 he becameProfessor and Chairman of the Department of Electrical Engineering at theUniversity of Rochester, Rochester, NY. Since relinqulishing the Chair-manship in 1980, he has continued his teaching and research interests at theUniversity of Rochester in computer organization and computer applica-tions to control and image-processing problepis. He has published fourbooks and has consulted for numerous companies in the area of computerapplications to control-system design.

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Documents

Computer Firmware Design Projects for Undergraduate Students