Computer Control Of a Direct Digital Synthesizer

Design Engineering Project

BENG (HONS) MOBILE COMMUNICATION ENGINEERING

EN0607 DESIGN ENGINEERING PROJECT

FINAL YEAR ENGINEERING PROJECT

COMPUTER CONTROL OF A DIRECT DIGITAL SYNTHESIZER

PROJECT STUDENT NAME – MANISH ABRAHAM

STUDENT NUMBER - 11033698

PROJECT SUPERVISOR - Dr. DAVID SMITH

SECOND MARKER - Dr. Michael Elsdon

DATE OF SUBMISSION - 16 May 2012

SCHOOL OF COMPUTING, ENGINEERING AND

INFORMATION SCIENCES

Computer control of a Direct Digital Synthesizer

Private and Confidential. 2

Abstract

Direct digital synthesis (DDS) is a process of creating an Analog waveform normally a sine

wave by producing a time-varying signal in the digital form and after that it performs a

digital-to-analog conversion.

The planning for this project required extensive research in to the theory of working as well

as research in to papers as this is an upcoming field with a lot of scope on innovation.

Here, we have tried to develop a set of waveforms using a direct digital synthesizer.

Here, an Evaluation board is being used in order to set a certain frequency range and

understand the usability of those frequencies.

The project looks into the filters and the possible spurs which take is there in a direct digital

synthesizer.



Acknowledgements

This project would not have been possible without the support of the Dr. David

Smith, As my teacher and mentor, he taught me more than I can give him credit

for here. He proved me, by his example, what a good engineer (and a person)

should be.

Dr. David Smith guided me as well as corrected the planning report many a

times. The help in getting the basic Idea clear in mind has helped me to think

more practically.

I would like to thank the Dr. Liam, Dr. Kevin G from Analog devices who has

helped me online by frequent mails in order to explain more about the practical

application of the direct digital synthesizer.

I would like to thank Northumbria University in providing such facilities of

research and the library which has a vast set of research papers for reference.



Table of Contents

Abstract .......................................................................................................................... 2

Acknowledgements ........................................................................................................ 3

Table of Contents ........................................................................................................... 4

Diagrams ........................................................................................................................ 5

Introduction .................................................................................................................... 6

Design Engineering Project ........................................................................................... 7

Aim ................................................................................................................................ 7

Objectives ...................................................................................................................... 7

Outcomes ....................................................................................................................... 7

Function Generator ........................................................................................................ 8

Background Information about the working of a direct digital synthesizer .................. 9

Applications of a Direct Digital Synthesizer ............................................................... 10

Working of A DDS ...................................................................................................... 12

Design work, Procedure and Results ........................................................................... 15

Evaluation Board AD9834 Direct Digital Synthesizer ................................................ 18

Procedure ..................................................................................................................... 30

Calculations/ Results .................................................................................................... 49

Discussion .................................................................................................................... 55

Aliasing in DDS systems ............................................................................................. 60

Band-pass filters .......................................................................................................... 61

Conclusion ................................................................................................................... 63

Project Management and Costing ................................................................................ 66

References .................................................................................................................... 73

Bibliography ................................................................................................................ 75

Appendices ................................................................................................................... 79



Diagrams



Introduction

With the modernization of integrated circuits (IC), digital systems are widely used now a

days in modern electronic devices, which includes communications & measurement

equipment. The main thrust of design consideration is the ability to create a variable

waveform conveniently and cost effectively. As per Eva Murphy (2011) different approaches

have been used, but the most effective one is direct digital synthesis. A direct digital

synthesizer, produces time-varying signals in digital form & then performs Digital to Analog

conversion thus produces an analog waveform which is usually a sine wave, and inherent

triangular and square waves. DDS devices are essentially digital, so they can provide fast

switching between output frequencies, excellent frequency resolution, & functions over a

broad range of frequencies.

Direct Digital Frequency Synthesizers (DDS) is used as transmitter exciters & local

oscillators in receivers, in communications, like the driving clock oscillator and quick

switching time; the DDS has the same advantages like higher frequency stability. The

problems which are faced are lower output frequencies & relatively large spurious signals.

(KROUPA, V. 1999).

At present, the two basic forms of applications of a direct digital synthesizer are in waveform

generation in communications and for signal study in business and biomedicine. "Some

other" uses include electronic article surveillance (EAS), Electro chemical analysis,

Impedance spectroscopy, Non-destructive testing and maritime applications in son buoy

systems.

Applications that exist in communications systems require agile frequency sources with low

phase interferences & spurs, proving that DDS does better frequency-tuning resolution &

spectral analysis. Some distinctive uses of DDS in communications include producing pilot

signals for WDM increased tunability reference frequencies for phase-locked loops (PLLs),

optical-channel identification, as local oscillators, and also for direct transmission.

"In this project" a computer is being used in order to control the direct digital synthesizer to

find out the desired frequency in the desired range.



Design Engineering Project

Aim

This project is a design engineering project which has been undertaken in order to use a

direct digital synthesizer understanding working of DDS, look at types of DDS, choosing

from the specifications and to set accurate frequency in the range of 7.2 MHz to 9.2

MHz’s with a step size of 10 KHz.

Objectives

The main objectives of the project would be to:

• "Understand the Output", Frequencies.

• Collect the Background Information about a DDS.

• To understand the applications of a DDS.

• Determine the required data for select output Frequency.

•"Workout the output frequency", changes of a direct digital synthesizer.

• Produce a circuit, "which will evaluate, and be able to determine the Desired Frequency by

using the Evaluation Board AD_9834" (EVAL 9834EB).

• Prototype development on the sources of spur and errors in a direct digital synthesizer.

• Design considerations for a filter was taken into account and a designing of a band pass

filter.

• Produce a report.

• For Higher Knowledge and appreciation study and outline how to input serial data into a

DDS chip Using Lab view.

Outcomes

I will be able to use an evaluation board in order to do experimental work and specifically

will be able to determine frequency in the range of 7.2 to 9.2 MHz with a step size of 10

KHz. I will be able to explain the operation of a DDS for different purposes. I will be able to

explain the sources of spurs and errors in direct digital synthesizer.



Function Generator

To produce different types of wave forms (sine, square, triangle, etc.) with a particular

frequency bandwidth and for different analysis work, we use a function generator.

Normally we used to use a Manuel Function generator.

Potentiometers are used to adjust the waveforms frequency and amplitude. An example of a

circuit of the function generator built using MAX038 IC. The frequency ranges & waveform

is selected by using switches whereas the voltage level course tuning & fine tuning is

adjusted using a potentiometer. The feedback regarding the provision of the output & the

equipment is not delivered to the user. Hence, we never know whether the desired waveform

is available at the output or not unless it is calculated by using appropriate equipment’s.

A schematic diagram of MAX038 IC (Manuel Function generator)



As per Dayton R.L (1988) the manual function generators are reasonable and user friendly

there are some defects which limits its performance. It is often difficult to adjust the

frequency and magnitude of the waveforms to the precise value needed because with

potentiometers we face tuning problems. The function generator does not recognize distant

control of the waveform. Hence we have to physically regulate the function generator every

time we need to change the waveform. A standard function generator does not allow

interfacing and collaboration with other devices. However by using a computer as a main

station, multiple different devices can be joined together to form a complete testing and

experimentation setup. The above weaknesses of a manual function generator can be

overcome using a computer controlled function generator like the AD9834.

AD9834

The outputs of AD9834 generate sinusoidal, triangular, and square-wave in nature which is

produced by using the DDS (direct digital synthesis) architecture. The Frequency resolution

generated is better than 0.1 Hz, and thus, we can programme the frequencies. As per Schewel,

J (1999) this feature is useful in digital modulation and frequency tuning applications. It is

controlled by using a computer.

Background Information about the working of a direct digital

synthesizer

Direct Digital Synthesizer

DDS generates a periodic, discrete-time waveform of known frequency Fo. The

waveform may be a sine wave, as per Turner, C. S. (2003). As per Jeff Patterson (2010) a

direct digital synthesizer, creates an analog waveform generally a sine wave, but some

times triangular and square waves are fundamental, by producing a time varying signal in

a digital form and which then performs a digital-to-analog conversion. DDS devices are

mainly digital; therefore they provide fast switching between output frequencies, both

excellent frequency resolution, and operation over a broad range of frequencies.

Some facts about the current available, Direct Digital Synthesizers as per Smith. J.

(1998):

• DDS devices are extremely small and draw little power.



• Currently available DDS devices can generate frequencies between 1 Hz and 400

MHz (based on a 1-GHz clock), with a time resolution to 48 bits.

• The new devices which is used, are of low cost as they use the new process

technologies they are combined with DDS’s inherently excellent performance and the

ability to digitally reprogram the output waveform which make the DDS system

particularly appealing compared to more discrete and less flexible standard solutions.

A basic Direct Digital Synthesizer comprises of a frequency reference which may be

crystal or SAW oscillator, a digital to analog converter and a numerically controlled

oscillator (NCO) as shown in block diagram.

Block diagram of a direct digital synthesizer

Jeff Patterson (2010)

The reference provides a reasonable time base for the system and specifies the frequency

accuracy of the DDS. It renders the clock to the NCO which produces a quantized version of

the desired output waveform (normally a sinusoid) at its output at a discrete time, the time is

controlled by the digital information which is stored in Frequency Control Register. The

sampled, digital waveform is then converted in to an analog waveform by DAC. The output

reconstruction filter disapproves the spectral reproductions produced by the zero-order

leverage inherent in the analog conversion process.

Applications of a Direct Digital Synthesizer



Waveform generation in communication.

• Enhanced tunability reference frequencies for phase-locked loops (PLLs).

• Generating pilot signals for WDM optical-channel identification.

• Local oscillators.

• Direct transmission.

• Signal research in industry and biomedicine.

i) Digitally creates programmable waveforms with easily adjustable frequency and

phase.

ii) Locate resonances or compensate for temperature drifts.

iii) Generate pulse width modulated signals for micro actuators.

iv) Examine attenuation in LANs or telephone cables.

v) Flexible frequency boost in measuring sensor impedance.

• Electronic surveillance

• Generating pilot signals for WDM optical-channel identification.

• Maritime applications in sonobuoy systems. An example of a live Function of a DDS

is sonobuoy as per Eva Murphy (2004). A sonobuoy is a tool that lies in the water and

seizes ambient sounds from the ocean; Common practical, applications for sonobuoys

are in the localization, detection, tracking, and identification of seismic events &

underwater objects like whales and submarines. Group of sonobuoys can be used to

determine target location, velocity, and direction.

The AD9834 (which will also be used in this project) is accurate as a definite frequency

reference in the transmitter section of the sonobuoy. Typical frequencies transmitted are from

136 MHz to 174 MHz. A DDS is often used to generate the frequency hopping in the transmit

& the receive sections.

DDS in transmit section of sonobuoy



DDS in receive section of sonobuoy.

The receive section portion of the sonobuoy is made up of a GPS antenna, down-conversion

front-end stage & a low-noise amplifier. The down-conversion is impelled by the Direct

Digital Synthesizer.

Working of A DDS

Adrio Communications (2010)

As the name suggests this is a form of synthesis, which generates the waveform directly using digital

techniques. It is remarkably different from the application of phase locked loop which was an indirect

method of operation.

A direct digital synthesizer functions by storing the points of a waveform in digital format, and then

recalling them to produce the waveform. The rate at which the synthesizer accomplishes one

waveform governs the frequency.

Block Diagram of a Basic DDS.

The operation can be known more easily by looking at the way the phase’s progresses over the course

of one cycle of the waveform. This can be known as the phase increase around the circle. When the

phase changes around the circle, this changes the advances in the waveform.



Working of the phase accumulator in a DDS.

The synthesizer operates by storing different points in the waveform in digital form and hence

recalling them to make the waveform. Its performance can be explained in thorough function by

looking at the phase changes around a circle as show. As the phase changes around the circle, this

corresponds to changes in the waveform, i.e. the more the number correspond to phase, the higher the

value is along the waveform. By one by one moving the number change in phase, it is possible to

proceed further along the waveform cycle.

Phase Accumulator.

The digital unit, which represents the state, is viewed due to the phase accumulator. The number is

held which corresponds to the phase and can be increased at regular intervals. So we can prove that

the phase accumulator is essentially a form of counter. When clocked it adds a pre-set number to the

one already held. While it fills up, it resets & starts counting again from zero. In other words, this

corresponds to reaching one full circle on the phase diagram and restarting again.

Waveform map.

Once the waveform has been decided it alters this into the digital representation of the waveform. This

is practised using a waveform map. This is a store which stocks a number corresponding to the

voltage needed for each value of phase on the waveform. In the position of a synthesizer of this type,

it is a sine look up table as a sine wave is needed. Mostly, the memory is either a read only memory

(ROM) and programmable read only memory (PROM). Which has an infinite number of points on the

waveform, vastly many more than are accessed each cycle. Large number of points is required so that

the phase accumulator could increase by a certain number of points to convey the desired frequency.



Digital to analogue converter (DAC).

The next stage in the action is to convert the digital numbers travelling from the sine look up table

into an analogue voltage. This is done by using a digital to analogue converter (DAC). We filter the

signal to throw away any intruding signals and amplified to achieve the desired level as needed.

Tuning is accomplished by gaining or deterioting the size of the stage or phase gain between different

example points. A higher increment at each update to the phase accumulator will show that the phase

reaches the highest set value faster, and, the frequency is very high. Small increments to the phase

accumulator value show that it takes longer to increase the maximum cycle value and a

correspondingly low value of frequency. In this process, it is possible to limit the frequency.

It is also seen that frequency changes can be made directly by simply changing the increment value.

From this, it can be seen that there is a perfect difference between one frequency & the next & that the

lowest frequency deviation or frequency resolution is determined by the total number of points

accessible in the phase accumulator. A 24 bit phase accumulator provides just over 16 million points

& will give a frequency resolution of around 0.25 Hz when used with a 5 MHz clock. This is

sufficient for most purposes.

Low Pass Filters.

The Direct digital synthesizers have a few disadvantages. There are a number of spurious signals,

which are produced by a direct digital synthesizer,. The most important one of these is called an alias

signal. Multiple images of the signal are produced on either side of the clock frequency.

For example if the desired signal had a frequency of 10 MHz and the clock was at 75 MHz then alias

signals would be 65 MHz and 85MHz etc.. These signals normally can be removed by using a low

pass filter. In case of Ad9834, we use a Band pass filter. Also, some low level spurious signals are

produced near in to the needed signal. These are generally acceptable in standard, but for some of the

applications they can cause problems.

Jim Surber and Leo McHugh Say that new integrated Complete-DDS products offer an attractive

alternative to analog PLLs for acute frequency synthesis applications. Direct digital synthesis (DDS)

has long been seen as a superior technology for producing accurate and changing frequency over a

wide range, low-distortion output waveforms.



Design work, Procedure and Results

Simple Design of a DDS

A main defect with this classic DDS system is that the output frequency can be altered only

by reprogramming the PROM or altering the reference clock frequency, making it quite

difficult.

The heart of the DDS is the phase accumulator, the contents of phase accumulator is updated

every clock cycle. The digital number, M, which is stored in the delta phase register, get

added to the number in the phase accumulator register whenever the phase accumulator is

updated. If we assume that the No.in the delta phase register is 00....01 and that the first

contents of the phase accumulator are 00....00, the phase accumulator is updated by 00...01,

each clock cycle. Since the accumulator is 32-bits wide (in our case it is 28 bits), 232 clock

cycles (over 4 billion) is required before the phase accumulator gets back to 00...00, and the

cycle repeats.

Digital phase wheel.



If fc is the clock frequency, then the frequency of the output sine wave is equal to:

(1)

Where = output frequency.

= Amount of phase Accumulator increased in each clock cycle.

= Number of bits

Frequency resolution of the system is equal to fc/2n.

This equation (1) is known as the DDS Tuning equation.

Theory of operation (AD9834 chip)

The chip operates as a numerically controlled oscillator using Phase accumulator, which is

28-bit phase accumulator, and a 10-bit digital to analog converter & sine coefficient ROM.

The magnitude of the sine wave is considered as A (t) = sin (ωt). Since the chip generates

nonlinear amplitude; hence, it is difficult to be generated.



MAGNITUDE

2p 2π PHASE 4π 6π

0

The angular information is quite linear, i.e. the phase angle keeps on rotating through a

desired angle for each unit in time. If we Know that the phase of the sine wave is linear and,

if we know reference interval (75 MHz in our case), the phase rotation for that period is:

Using this formula, we can produce the output frequencies, knowing the phase and master-

clock frequency. We can Programme a DDS by writing the values to the frequency registers.

The analogue output from the part is then: fo= (M*fc)/2^n.

The output of the DDS has 28-bit resolution ( n = 28) , so effective frequency steps in the

order of 0.1 Hz are likely to a maximum of approximately 20 MHz The phase registers allow

12-bit phase resolution. The Phase shift can be calculated by using the underlying formula.

1

2π 4π

-1

0



The chip AD9834 has 2 frequency registers and 2 phase registers. Each frequency register

has a size of 28 bits while each phase register has 12 bits.

Phase is defined as the value that is contained in the selected frequency register.

What are we using?

Evaluation Board AD9834 Direct Digital

Synthesizer

Analog devices (2010)

The AD9834 is a 75MHz, low power DDS device capable of producing high performance

sine and triangular outputs. Since it consumes only 20mW of power at 3V, it makes the

AD9834 an ideal candidate for power sensitive applications.



For the project plan, we are using an Evaluation board AD_9834 EB. The AD9834 is a

numerically controlled oscillator using a sine look-up table, a phase accumulator and a 10-bit

DAC. The AD9834 can be operated with clock frequencies up to 75 MHz’s. Both phase

modulation and frequency modulation can be performed with the AD9834.

The frequency registers are 28 bits; with a 75 MHz clock speed, resolution of 0.28 Hz can be

achieved. The AD9834 evaluation board includes a 75 MHz oscillator that provides the

MCLK (75MHz) for the AD9834. We can remove this oscillator, if needed, and operate the

AD9834 with an external clock source with the help of a BNC connector. A digital guard is

also on the board in order to buffer the signals on the edge of the connector.

Initially research included the research in to the Hardware descriptions which include looking

in to the power supplies.

Hardware description

POWER SUPPLIES

This evaluation board is made up of 2 inputs which are analog in nature: AVDD (Analog VDD) and

AGND (Analog GND). Digital supplies also form part like, DVDD (Digital VDD) and DGND

(Digital GND). Digital and Analog are free of each other & is powered between 2.3 V to 5.5 V.

All the power supplies are generally decoupled to the ground plane using 10 μF tantalum capacitors

and 0.1 μF ceramic capacitors at the input to the evaluation board.

The power supplies are also decoupled using 0.1 μF capacitors at the AD9834, the crystal, and the

logic.

LINK AND SWITCH OPTIONS

The five link options needs to be set before using the eval board (LK1, LK2, LK3, LK4, and LK5) .

LK1

If we select hardware as the programming method, then the LK1 operates as follows:

• With LK1 in Position A, we can control PSEL with the help of an external logic source through the

SMB connector, PSEL1.

• With LK1 in Position B, we can connect PSEL to SW1, which allows the user to control the PSEL

signal since we use the double throw switch, SW1-2. If we use the programming method as

software we ignore the LK1.

LK2



If we choose programming method as hardware, LK2 operates as follows:

• With LK2 in Position A, we can control FSEL with the help of an external logic source with the

SMB connector, FSEL1.

• If we position LK2 as position B, FSEL is connected to SW1, which allows us to control the FSEL

signal by utilizing the double throw switch, SW1-3. We ignore LK2 if software is selected as the

programming method.

LK3

We keep the LK3 open in order to provide MCLK of 75MHz oscillator.

In order to drive from an external clock we close LK3 which we did not do since we used the internal

clock. If the user requires the AD9834 to be driven from an external clock source with the help of an

SMB connector, CLK1, the on-board 75 MHz oscillator should be removed from the board, and LK3

is closed.

LK4

The digital section is driven by an on chip regulator that helps to step down the applied DVDD

voltage to 2.5 V suppose that DVDD exceeds 2.5 V. LK 4 should be open in case the user applies the

voltage higher than 2.5 V.

If the user applies a voltage of 2.5 V to DVDD, when we can bypass the regulator by closing LK4.

Note that the components on the evaluation board and the Centronics connector do not operate at 2.5

V. For evaluation of the AD9834 at 2.5 V, the evaluation board should be used as a standalone board,

with the user supplying the SCLK, SDATA, FSYNC, and RESET externally. The digital buffer and

the oscillator should also be replaced with 2.5 V compatible devices.

LK5

The AD9834 has a SLEEP pin that allows sections of the device that are not being used to be powered

down to minimize the current consumption.

With LK5 in Position B, the AD9834 is fully powered up, and the sleep function is not being used.

With LK5 in Position A, the on-chip DAC on the AD9834 is powered down, which is useful in

applications where a clock output is being generated using the MSB from the NCO.

EVALUATION BOARD INTERFACING

The evaluation board interfaces via a 36-way Centronics female connector, J1. The pin designations

are given below:

Pin No. Mnemonic Description



2 SCLK Serial Clock. The signal buffering takes place on this pin before

being applied to the SCLK pin of the AD9834. There is a need of

external serial clock where data/control information is written to

the device. The serial clock is normally continuous, or can idle

high or low between write operations.

3 SDATA Serial Data. Data applied to this pin is buffered before being

applied to the AD9834. The serial data applied to the SDATA pin

is written to the serial register of the device. The data is then

transferred to the destination register or the control register. The

two MSBs of the 16-bit word being written are used to identify

the destination for the data information. The AD9834 accepts

CMOS logic levels.

4 FSYNC The signal on this pin is buffered before being applied to the

FSYNC pin of the AD9834. The FSYNC signal frames the 16-bit

word being loaded into the AD9834, the signal going low for 16

SCLK cycles.

14

RESET

Active High Digital Input. RESET resets the phase accumulator

to 0, which corresponds to an analog output of midscale.

19 to 30 DGND Digital Ground. These lines are connected to the digital ground

plane on the evaluation board.

1, 5 to 13, 15 to 18, 31 to 36 No Connect.

SOCKETS

The seven sockets relevant to the operation of the AD9834 on this evaluation board

Socket Function

CLK1 Sub miniature BNC socket for the MCLK input

FSEL1 Sub miniature BNC socket for FSELECT

PSEL1 Sub miniature BNC socket for PSEL



IOUT Sub miniature BNC socket for IOUT

IOUTB Sub miniature BNC socket for IOUTB

SBOUT Sub miniature BNC socket for SBOUT

CONNECTORS

The three connectors on the AD9834 evaluation board are

Connecto

r

Function

J1 36-way Centronics connector.

J2 PCB mounting terminal block. The digital power supply to the evaluation board is provided via

this connector.

J3 PCB mounting terminal block. The analog power supply to the evaluation board is provided via

this connector.

SWITCHES

The AD9834 evaluation board has an end-stackable switch that can be used to control the FSEL and

PSEL inputs.

AD 9834 Chip

Pin No. Mnemonic Description

ANALOG SIGNAL AND REFERENCE

1 FS Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and



ADJUST AGND. This determines the magnitude of the full-scale DAC current. The

relationship between RSET and the full-scale current is as follows:

IOUT FULL SCALE = 18 × FSADJUST/RSET

FSADJUST = 1.15 V nominal, RSET = 6.8 kΩ typical.

2 REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference that is

made available at this pin.

3 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.

17 VIN Input to Comparator. The comparator can be used to generate a square wave from

the sinusoidal DAC output. The DAC output should be filtered appropriately before

being applied to the comparator to improve jitter. When Bit OPBITEN and Bit

SIGN/PIB in the control register are set to 1, the comparator input is connected to

VIN.

19, 20 IOUT,

IOUTB

Current Output. This is a high impedance current source. A load resistor of

nominally 200 Ω should be connected between IOUT and AGND. IOUTB should

preferably be tied through an external load resistor of 200 Ω to AGND, but it can be

tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent

clock feed through.

POWER SUPPLY

4 AVDD Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V

to 5.5 V. A 0.1 μF decoupling capacitor should be connected between AVDD and

AGND.

5 DVDD Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V

to 5.5 V. A 0.1 μF decoupling capacitor should be connected between DVDD and

DGND.

6 CAP/2.5V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated

from DVDD using an on-board regulator (when DVDD exceeds 2.7 V). The

regulator requires a decoupling capacitor of typically 100 nF that is connected from

CAP/2.5 V to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5 V should be

shorted to DVDD.

7 DGND Digital Ground.

18 AGND Analog Ground.

DIGITAL INTERFACE AND CONTROL

8 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of

the frequency of MCLK. The output frequency accuracy and phase noise are



determined by this clock.

9 FSELEC

T

Frequency Select Input. FSELECT controls which frequency register, FREQ0 or

FREQ1, is used in the phase accumulator. The frequency register to be used can be

selected using Pin FSELECT or Bit FSEL. When Bit FSEL is used to select the

frequency register, the FSELECT pin should be tied to CMOS high or low.

10 PSELEC

T

Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1,

is added to the phase accumulator output. The phase register to be used can be

selected using Pin PSELECT or Bit PSEL. When the phase registers are being

controlled by Bit PSEL, the PSELECT pin should be tied to CMOS high or low.

11 RESET Active High Digital Input. RESET resets appropriate internal registers to zero; this

corresponds to an analog output of midscale. RESET does not affect any of the

addressable registers.

12 SLEEP Active High Digital Input. When this pin is high, the DAC is powered down. This

pin has the same function as Control Bit SLEEP12.

CIRCUIT DESCRIPTION



The AD9834 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one

reference clock, one low precision resistor, and eight decoupling capacitors which digitally

creates sine waves up to 37.5 MHz.

The internal circuitry of the AD9834 consists of the following main sections:

Numerically controlled oscillator (NCO),

Frequency and phase modulators,

SIN ROM, a DAC,

Comparator, and a regulator.

NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR

NCO mainly consists of two frequency select registers, two phases offset registers, a phase

accumulator and a phase offset adder. The main component of the NCO is a phase

accumulator which is of 28-bit. A continuous time signal normally has a phase range of 0 π to

2π. The input to the phase accumulator is selected from the FREQ0 register and FREQ1

register which is controlled by the FSELECT pin or the FSEL bit. NCOs inherently generate

continuous phase signals, hence avoiding any output discontinuity when switching between

frequencies.

SIN ROM

The SIN ROM mainly uses the digital phase information as an address and converts the phase

information into amplitude

DIGITAL-TO-ANALOG CONVERTER (DAC)

The AD9834 contains a high impedance current source which is a 10-bit DAC which is

capable of driving a wide range of loads. The DAC is configured for either single-ended or

differential operation. IOUT and IOUTB are connected with the help of equal external

resistors to AGND to develop complementary output voltage.

COMPARATOR

The AD9834 is used to generate synthesized digital clock signals. This is done by using the

on-board self-biasing comparator which has the role of converting the sinusoidal signal of the

DAC to a square wave. The output from the DAC is normally filtered externally before being

applied to the comparator input.



REGULATOR

The AD9834 has two separate power supplies for the analog and digital sections. We had the

applied voltage at the DVDD pin of the AD9834 which was less than 2.7V Hence the Pin

CAP/2.5V and Pin DVDD was tied together, thus bypassing the on-board regulator.

To apply the AD9834 as a clock generator, we had to limit the selected output frequency to

<33% of reference clock frequency which was 75MHz in our case , and thereby we avoided

generating aliased signals that fall within, or close to, the output band of interest.

Software description

From this window, we can control all the functionality of the AD9834.

The main features are listed below and described in detail in the sections that follow.

• Access to both Frequency Register 0 and Frequency Register 1

• Access to both Phase Register 0 and Phase Register 1

• Access to the RESET bit



• Ability to sweep through a frequency range using either the Frequency Register 0 or

Frequency Register 1

• Access to the programming method

• Access to the sleep options

• Access to sign bit output options

• Access to the IOUT output options

FREQUENCY REGISTERS

The AD9834 contains two frequency registers that can be programmed individually. The evaluation

board software allows the user to enter any frequency value between 0 Hz and half the master clock

frequency. If a value outside this range is entered, the software chooses the closest valid value. The

frequency value is converted to a 28-bit decimal number that is loaded to the appropriate frequency

register after clicking Enter. The hexadecimal equivalent is also displayed in the main window.

PHASE REGISTERS

The AD9834 contains two phase registers that can be individually loaded with different values. The

phase numbers are entered as integer values between 0 and 4095 (corresponding to 0° to 360° phase

shift). The values are loaded to the appropriate phase register after clicking Enter.

RESET MODE

The RESET bit in the control register of the AD9834 is controlled by the Reset Bit = 0 and Reset Bit

= 1 buttons of the AD9834 evaluation board software. The RESET bit is initialized to 0 on power-up

by the AD9834 evaluation software. Setting the RESET bit to 1 (by clicking Reset Bit = 1 in the main

window) sets the phase accumulator to zero phase corresponding to an analog output of midscale.

SWEEP FACILITY

Clicking Sweep in the main window displays the Sweep Output Frequency dialog box, which can

be used to program the AD9834 to produce a continuously increasing or decreasing frequency sweep.

The user can enter a start frequency, a stop frequency, or a step frequency. There is also the option of

setting the delay between steps, and the number of time the sweep is to be repeated.



The sweep values in the following example generate the frequency outputs shown in Table 6. If the

frequency span is not an integer multiple of the step frequency, the span from the second to last

frequency to the last frequency is such that the stop frequency is the last frequency output to the

AD9834.

Both Frequency Register 0 and Frequency Register 1 can be loaded with separate frequency, step,

delay, and loop information, but the output from the AD9834 depends on which frequency register is

selected via the FSEL pin or Freq Reg bit.

PROGRAMMING METHOD

The choice of programming method controls the selection of the frequency and phase registers used to

provide the output. If the hardware option is chosen, the frequency and phase selection come from the

FSEL and PSEL pins, respectively. This disables changing the frequency and phase registers from

software as required. If the software option is chosen, the registers are selected by software. Note that

registers are not set to a known value on power-up, so the user should set all the registers to a known

value.

SLEEP OPTIONS

The control register of the AD9834 contains two sleep bits that put the part into a power-down mode.

The sleep options on the evaluation board provide full access to both bits.

Sleep Options

Option Description

Full Power-Up Nothing on the AD9834 chip is powered down.

Disable Internal The internal clock of the AD9834 is disabled. The DAC output remains at its present value as the



Clock NCO is no longer accumulating.

Power-Down

DAC

The DAC on the AD9834 is powered down. This is useful when the AD9834 is used to output the

NCOs MSB only. Note that this option corresponds to the SLEEP pin. When the chosen

programming method is hardware, this option is ignored as the SLEEP pin controls the power-

up/-down operation of the DAC.

DAC and CLK

Down

Both the CLK and the DAC are powered down.

SIGN BIT OUTPUT OPTIONS

The sign bit output options control what the user sees on the SIGN BIT OUT pin. The options are

described below. The user can access this pin through the SMB SBOUT.

Option Description

Output Disabled There is no output at SIGN BIT OUT.

Phase Accumulator MSB The MSB from the phase accumulator is connected to the SIGN BIT OUT pin.

Comparator This connects the on-chip comparator of the AD9834 to the SIGN BIT OUT pin.

Divide Output by 2 This determines the frequency of the square waveform on the SIGN BIT OUT pin. The

user has the option to divide this frequency by 2 by checking this box.

IOUT OUTPUT OPTIONS

The AD9834 provides two IOUT output options

Option Description

Sinusoidal The output from the SIN ROM is fed to the DAC, which results in a sinusoidal output in IOUT.

Ramp The SIN ROM can be bypassed so that a linear up/down ramp is output from the DAC.



Procedure

THE CONNECTIONS

THE BATTERY AND DDS CONNECTIONS



The Experiment was carried out in Microwave electronics lab where firstly the dc convertor was

connected and a voltage was kept between 2.3V and 5.5V. The output wire was connected with the

two devices which we would be discussing ahead in the discussion.

The evaluation board was set up as under two stages:

1. Time Domain.

2. Frequency Domain.

1. Time domain

Time Domain is mainly the analysis of amplitude of functions or sine waves/ signals with respect to

time, an oscilloscope is used to analyse the signals in the time domain.

We know that f(t) = sin(wt)

Here w is frequency component and in this case we observe a sine wave as a DDS produces a sine

wave

The following equipment’s were used for the experiment

3. A computer



4. Evaluation board AD9834

5. Oscilloscope

6. DC power Supply

7. Wire to connect the Spectrum

analyser and Iout.

8. Wire to connect the printer port and

the Evaluation board.

9. Lab view Simulation software

Initially a simulation was carried out on the analog devices

ADIsimDDS design tool

For the output frequency of 7.2 Mhz the time domain graph

without the Filter

We Know that in the evaluation board AD9834 we use a band pass filter, hence if we apply the filter

we get the following graph



The start frequency was 0 MHz and the End frequency was 100 Mhz

In practical situations a series of similar graphs were observed on an oscilloscope.

We used an Oscilloscope to observe the exact wave shape of an electrical signal as per the schematic.

In addition to the amplitude of the signal, an oscilloscope here was used to show distortion, the time

between two events such as pulse width, period, or rise time and relative timing of two related signals.

ADI Sim DDS design tool

The advantage of this tool is to assist a user to select and evaluate Analog Devices; Direct Digital

Synthesis (DDS) IC's which also included AD9834 DDS. It allows a user to analyse a device, enter



the desired operating conditions and evaluate its general performance. The tool uses mathematical

equations to approximate the overall performance of the selected device & calculates possible errors.

Operation Procedure:

Select the correct device (In our case it was AD 9834).

1. Ref. Clock Frequency

Enter the desired device Reference Clock Frequency, also known as the Master Clock, It is

normally automatically selected in our case it is 75MHz.

2. Desired Output Frequency

Enter the desired DDS Output Frequency.

We selected various output frequencies between 7.2 to 9.2 MHz.

Note: The Ref. Clock Frequency determines the number of discrete DAC steps or points

contained in the output frequency. Due to Nyquist requirements the output frequency is

generally limited to approximately 40 % of the Clock Frequency. In case of an AD9834 the

maximum output frequency could be 37.5 MHz.

3. Modifying the Filter Response

The tool provides a check box and configuration and also provides setup for the filter

response applied to the DDS output.

In case of the AD9834 evaluation board we select the filter as a band pass filter hence needs

to select the option of a band pass filter.



Configuration of a band pass filter

In this band pass filter

f1 is the desired output freq i.e. . 7.2 MHz

f2 is the clock frequency i.e. 75MHz

It was observed that the AD9834 used digital signal processing to construct output wave

forms which were sinusoidal in nature. A frequency sweep was done between 7.2 and 9.2

MHz.



A Few Graphs which were detected on the ADSim Simulation

= 75 MHz fo = 7.2 MHz

= 75 MHz fo = 7.3 MHz = 75 MHz fo = 7.4 MHz







= 75 MHz fo = 8.1 fo = 8.2 MHz fo = 8.3 MHz

= 75 MHz fo = 8.4MHz = 75 MHz fo = 8.5 MHz



= 75 MHz fo = 8.8 MHz = 75 MHz fo = 8.9MHz

2, Frequency Domain

Fourier theory (WANG, T. T. & FAN, H. Y. 2009) tells us that the time-domain is made up of few

sine waves of appropriate frequency, amplitude, and phase. We can transform a time-domain signal

into its frequency domain equivalent. Measurements in the frequency domain tell us how much

energy is present at each particular frequency. Fourier theory says that the constituent sine waves are

separated in the frequency domain by 1/T where T is the time period of the signal.


= 75 MHz fo = 9.2 MHz



Frequency-domain graph shows how much of the signal lies within each given frequency band over a

range of frequencies.

People who work in wireless communications are interested in out-of-band and spurious emissions.

For e.g., cellular radio systems must be checked for harmonics of the carrier signal that might

interfere with other systems operating at the same frequencies as the harmonics. Engineers are also

very interested about the distortion of the message modulated onto a carrier. Spectrum monitoring is

another important frequency-domain measurement activity. The Spectrum monitoring can be done

with the help of a spectrum analyser as per Agilent Spectrum Analysis Basics (2006).



The following equipment’s were used for the experiment

A computer

Evaluation board AD9834

Spectrum Analyser

DC power Supply

Wire to connect the Spectrum

analyser and I out.

Wire to connect the printer port and

the Evaluation board.

Lab view Simulation software.

We used a spectrum analyzer to find the frequency, power, noise, modulation and spurs.

The time domain signal is digitalised using a Fourier analyser, then uses digital signal processing

(DSP) techniques to perform a fast Fourier transform (FFT) and display the signal in the frequency

domain.



A spectrum analyser was used in order to analyse the frequency

coming out of the (I out)

In one example for 7.2 MHz

Here F1= Desired output frequency (7.2 MHz)

F2= clock frequency (75 MHz)

Harmonic Spur formula

First = f1, second = f2-f1, third f2+f1, fourth = 2f2-fi, Fifth 2f2+f1



The Start frequency was set as 0 MHz, The end frequency was set

as 100 MHz’s. Hence the simulation should have been as under

Spectrum Analyser

This photo shows when we were able to set an exact frequency of

7.2 MHz the clock frequency is 75MHz hence we observe second

harmonic was observed in the clock frequency of 75-7.2 = 67.8



67.8MHz.

Fo=7.2 MHz

Fo= 7.3 MHz

Fo=7.5MHz Fo=7.6MHz



Fo=7.7MHz Fo=7.8MHz

Fo=7.9MHz Fo=8.0MHz

Fo=8.1MHz Fo=8.2MHz



Fo=8.3MHz Fo=8.4MHz

Fo=8.5MHz Fo=8.6MHz

Fo=8.7MHz Fo=8.8MHz

Fo=8.9MHz Fo=9.0MHz



Fo=9.1MHz Fo=9.2MHz



Lab View Simulation designed to explain the control of a Direct Digital Synthesizer

LAB VIEW (E. Lunca, S. Ursache and O. Neacsu (2011))

Lab View is system design software that provides engineers and scientists with the tools needed to

create and deploy measurement and control systems through unprecedented hardware integration. Lab

VIEW programs are called virtual instruments, or VIs, because their appearance and operation imitate

physical instruments, such as oscilloscopes and millimetres. Lab VIEW contains a comprehensive set

of tools for acquiring, analysing, displaying, and storing data, as well as tools to write the code.

Lab View programme that was made can be organized in to two parts

1. Front panel – It represents the interface between the source programme and the user.

2. Diagram Block-



The edited source programme which was made on the lab view to explain the working of a

DDS.

A DDS system is basically made up of a Lookup Memory, an accumulator (counter), and a

Digital to Analog Converter.

The Lookup Memory (LM) contains one cycle of the waveform to be generated. “Lookup table”, is a

set of consecutive memory addresses, every memory addresses contains value of a sine function for a

particular angle.

In case of an AD9834 Evaluation board, the LM is 12-bits, 4096 samples contains one cycle

(2^12).N= address and x[n

If n increases by 1, [n] Increases by

0879.04096

360.

n [n] x[n]

0 0 0



1 0.0879 0.0015

2 .1758 .0031

⁞ ⁞ ⁞

341 30 0.5

⁞ ⁞ ⁞

4095 359.9121 -0.0015

The Accumulator is similar to a counter, but it has more features. The most important feature is the

ability to count by almost any number as well as one. In this example, the Accumulator is simulated

by a while loop and a shift register to count by the Frequency Control Word. The count is done with

U32 representation and therefore, simulates a 28 bit counter. When it reaches its highest values, the

"counter" rolls over as an Accumulator does.

The Accumulator value is converted to an array of Booleans so that it can easily take the top 12 bits,

and then convert this array to an integer value. The high 12 bits of the "Accumulator" are sent to the

LM and index the array. The indexed value of the Lookup Memory is a 16 bit signed integer sample

of the sine wave, and this value is sent to the DAC.

Phase, Frequency and Control words are all sent to the AD9834 via a 3-wire interface. The three

signals used to transfer these words are: FSYNC, SDATA, and SCLK. Each word is 16 bits in

length, so all transfers are 16 bit transfers. But in case of an Evaluation board Ad9834 we did not

consider the SCLCK because we did not use an external clock instead only used the clock frequency

of 75 MHz.

The appendix has a detailed VI block diagram.

Calculations/ Results

Due to Binary Quatitization the Actual Output Frequency may differ from the Desired Output

Frequency.

We see that the DDS Tuning equation is

(1)

= output frequency.

= Amount of Phase Accumulator increased in each clock cycle =???

= Number of bits = 28 bits

= 75 MHz



We know that the frequency range of output frequency is between 7.2 MHz to 9.2 MHz’s with a step

size of 10 KHz.

Hence we see that the output frequency needs to be changed with a step size of 10 KHz.

The output frequency can be changed instantaneously with no phase discontinuity by simply changing

the contents of the M-register. However, practical DDS systems first require the execution of a serial

or byte-loading sequence to get the new frequency word into an internal buffer register which

precedes the parallel-output M-register. This is done to minimize package pin count..

Frequency resolution of the system is equal to fc/2n.

This equation (1) is known as the DDS Tuning equation. Hence

S/no.

1

Output

Frequency

Fo (Khz)

7200

Clock frequency

Fc (MHz)

75

Bit rate n

28

Phase accumulator increment each cycle

25769803780

2 7210 75 28 25805595170

3 7220 75 28 25841386560

4 7230 75 28 25877177960

5 7240 75 28 25912969350

6 7250 75 28 25948760750

7 7260 75 28 25984552140

8 7270 75 28 26020343530

9 7280 75 28 26056134930

10 7290 75 28 26091926320

11 7300 75 28 26127717720

12 7310 75 28 26163509110

13 7320 75 28 26199300510

14 7330 75 28 26235091900

15 7340 75 28 26270883290

16 7350 75 28 26306674690

17 7360 75 28 26342466080

18 7370 75 28 26378257480

19 7380 75 28 26414048870

20 7390 75 28 26449840260

21 7400 75 28 26485631660

22 7410 75 28 26521423050



23 7420 75 28 26557214450

24 7430 75 28 26593005840

25 7440 75 28 26628797240

26 7450 75 28 26664588630

27 7460 75 28 26700380020

28 7470 75 28 26736171420

29 7480 75 28 26771962810

30 7490 75 28 26807754210

31 7500 75 28 26843545600

32 7510 75 28 26879336990

33 7520 75 28 26915128390

34 7530 75 28 26950919780

35 7540 75 28 26986711180

36 7550 75 28 27022502570

37 7560 75 28 27058293960

38 7570 75 28 27094085360

39 7580 75 28 27129876750

40 7590 75 28 27165668150

41 7600 75 28 27201459540

42 7610 75 28 27237250940

43 7620 75 28 27273042330

44 7630 75 28 27308833720

45 7640 75 28 27344625120

46 7650 75 28 27380416510

47 7660 75 28 27416207910

48 7670 75 28 27451999300

49 7680 75 28 27487790690

50 76900 75 28 27523582090

51 7700 75 28 27559373480

52 7710 75 28 27595164880

53 7720 75 28 27630956270

54 7730 75 28 27666747670

55 7740 75 28 27702539060

56 7750 75 28 27738330450

57 7760 75 28 27774121850

58 7770 75 28 27809913240

59 7780 75 28 27845704640

60 7790 75 28 27881496030

61 7800 75 28 27917287420

62 7810 75 28 27953078820

63 7820 75 28 27988870210

64 7830 75 28 28024661610



65 7840 75 28 28060453000

66 7850 75 28 28096244390

67 7860 75 28 28132035790

68 7870 75 28 28167827180

69 7880 75 28 28203618580

70 7890 75 28 28239409970

71 7900 75 28 28275201370

72 7910 75 28 28310992760

73 7920 75 28 28346784150

74 7930 75 28 28382575550

75 7940 75 28 28418366940

76 7950 75 28 28454158340

77 7960 75 28 28489949730

78 7970 75 28 28525741120

79 7980 75 28 28561532520

80 7990 75 28 28597323910

81 8000 75 28 28633115310

82 8010 75 28 28668906700

83 8020 75 28 28704698090

84 8030 75 28 28740489490

85 8040 75 28 28776280880

86 8050 75 28 28812072280

87 8060 75 28 28847863670

88 8070 75 28 28883655070

89 8080 75 28 28919446460

90 8090 75 28 28955237850

91 8100 75 28 28991029250

92 8110 75 28 29026820640

93 8120 75 28 29062612040

94 8130 75 28 29098403430

95 8140 75 28 29134194820

96 8150 75 28 29169986220

97 8160 75 28 29205777610

98 8170 75 28 29241569010

99 8180 75 28 29277360400

100 8190 75 28 29313151800

101 8200 75 28 29348943190

102 8210 75 28 29384734580

103 8220 75 28 29420525980

104 8230 75 28 29456317370

105 8240 75 28 29492108770

106 8250 75 28 29527900160



107 8260 75 28 29563691550

108 8270 75 28 29599482950

109 8280 75 28 29635274340

110 8290 75 28 29671065740

111 8300 75 28 29706857130

112 8310 75 28 29742648520

113 8320 75 28 29778439920

114 8330 75 28 29814231310

115 8340 75 28 29850022710

116 8350 75 28 29885814100

117 8360 75 28 29921605500

118 8370 75 28 29957396890

119 8380 75 28 29993188280

120 8390 75 28 30028979680

121 8400 75 28 30064771070

122 8410 75 28 30100562470

123 8420 75 28 30136353860

124 8430 75 28 30172145250

125 8440 75 28 30207936650

126 8450 75 28 30243728040

127 8460 75 28 30279519440

128 8470 75 28 30315310830

129 8480 75 28 30351102230

130 8490 75 28 30386893620

131 8500 75 28 30422685010

132 8510 75 28 30458476410

133 8520 75 28 30494267800

134 8530 75 28 30530059200

135 8540 75 28 30565850590

136 8550 75 28 30601641980

137 8560 75 28 30637433380

138 8570 75 28 30673224770

139 8580 75 28 30709016170

140 8590 75 28 30744807560

141 8600 75 28 30780598950

142 8610 75 28 30816390350

143 8620 75 28 30852181740

144 8630 75 28 30887973140

145 8640 75 28 30923764530

146 8650 75 28 30959555930

147 8660 75 28 30995347320

148 8670 75 28 31031138710



149 8680 75 28 31066930110

150 8690 75 28 31102721500

151 8700 75 28 31138512900

152 8710 75 28 31174304290

153 8720 75 28 31210095680

154 8730 75 28 31245887080

155 8740 75 28 31281678470

156 8750 75 28 31317469870

157 8760 75 28 31353261260

158 8770 75 28 31389052650

159 8780 75 28 31424844050

160 8790 75 28 31460635440

161 8800 75 28 31496426840

162 8810 75 28 31532218230

163 8820 75 28 31568009630

164 8830 75 28 31603801020

165 8840 75 28 31639592410

166 8850 75 28 31675383810

167 8860 75 28 31711175200

168 8870 75 28 31746966600

169 8880 75 28 31782757990

170 8890 75 28 31818549380

171 8900 75 28 31854340780

172 8910 75 28 31890132170

173 8920 75 28 31925923570

174 8930 75 28 31961714960

175 8940 75 28 31997506360

176 8950 75 28 32033297750

177 8960 75 28 32069089140

178 8970 75 28 32104880540

179 8980 75 28 32140671930

180 8990 75 28 32176463330

181 9000 75 28 32212254720

182 9010 75 28 32248046110

183 9020 75 28 32283837510

184 9030 75 28 32319628900

185 9040 75 28 32355420300

186 9050 75 28 32391211690

187 9060 75 28 32427003080

188 9070 75 28 32462794480

189 9080 75 28 32498585870

190 9090 75 28 32534377270



191 9100 75 28 32570168660

192 9110 75 28 32605960060

193 9120 75 28 32641751450

194 9130 75 28 32677542840

195 9140 75 28 32713334240

196 9150 75 28 32749125630

197 9160 75 28 32784917030

198 9170 75 28 32820708420

199 9180 75 28 32856499810

200 9190 75 28 32892291210

201 9200 75 28 32928082600

There were 201 different readings taken which was taken individually using the ADIsimDDS Design

tool & practically using a spectrum analyser please refer to the appendix for the detailed readings

which were observed using the tool.

Discussion

There were 201 different readings taken which was taken individually using the ADIsim DDS Design

tool & practically using a spectrum analyser.

As per David Brandon. (2007) the main feature of a direct digital synthesizer is the ability to produce

frequency agile tone with residual phase noise which we were also able to produce but there where

spurs which were observed.



The Digital Word required be loading into or writing to the DDS to Obtain the Actual Output

Frequency. It can be in Decimal Hexadecimal or Binary.

In case of AD 9834 we use the hex decimal for example

Example of The phase accumulator increment For 7.2 MHz is 189374C and for 9.2 Mhz 1F67153

There were spurs which were noticed which led to further research in to the sources and how could

they be changed.

The spurious emissions were observed.



The main sources of spur in a DDS were due to

1. Reference clock

2. Truncation in the phase accumulator

3. Angle to amplitude mapping errors

4. DAC errors

Reference clock

In case of an AD9834 evaluation board the DDS acted like a high resolution frequency divider with

the reference clock in input and the DAC as the output.

When we try modulating the clock amplitude it generates spurs in the output spectrum,

The attenuation calculation of 20 log (75Mhz/7.2MHz) predicted a 20.35dB improvement.

Whereas when we calculated it was noted that there was additional spur attenuation.

This was because the modulating sine wave of the reference clock encounters a limiter which

converted the AM spurs to PM.

A high rate reference clock spends less time to traverse the region where noise is jittered.

As per Intel (1999) Lower clock frequencies allowed higher resolution and better spectral purity for

any given number of bits in the accumulator (N) and a given ROM size

Phase Truncation

The power dissipation and die area is reduced. The o/p is divided in to two sections the phase word p

which sends to the mapper and discards bits M= T-P where T is the phase accumulators tuning word

width. This is the reason for the production of phase modulation spurs. When we do practical



experiments DDS drives a PLL where the spur within the loop is amplified by 20 log (N) dB, where N

is the multiplication factor. The frequency of spur offset ,

= Spur offset frequency.

= Decimal value of discarded bits.

= Number of discarded bits.

= Reference clock output frequency.

The Phase truncation mechanism



Phase truncation spur was observed in the experiments carried on.

Due to the phase truncation we observed that the first harmonic is generally the strongest , It causes

phase modulation with a periodic waveform.

Angle to Amplitude Mapping

The phase to amplitude conversion of a time sampled sine wave is

Where Vai is the sample amplitude, Vp is the half of DACs full scale voltage

and oi is the value of samples phase word.

It was observed that retaining more bits in the phase word reduces these errors, i.e. set the phase word

to a minimum of 3 bits wider than DAC.

Quantization Noise, DAC Nonlinearities

We can calculate the quantization noise as it is directly proportional to the DAC resolution

SNR = 7.21 N +1.3 (dB)

Where N is the DAC resolution in bits.

In the end we came to a conclusion that we can reduce the spurs caused by aliases by increasing the

reference frequency fref

Solution –

– Spurs generally occurs due to uniform stepped periodic sequences.



We can introduce a few jitters (minimal noise) which should be able to destroy the

periodicity.

This would convert the spur energy in to broad band phase noises.

As per Chao Huang (2009) frequency planning is the only way that works in eliminating the spurs of

DDS in real circumstances.

Aliasing in DDS systems

(http://www.digikey.com/us/en/techzone/wireless/resources/articles/fundamentals-of-direct-digital-

synthesis.html)

There is one important limitation to the range of output frequencies that can be generated from the

simple DDS system. The Nyquist Criteria states that the clock frequency (in case of AD9834 it was

75 MHz) must be at least twice the output frequency. We saw that practical limitations restricted the

actual highest output frequency to about 1/3 the clock frequency. It shows the output of a DAC in a

DDS system where the output frequency is 30 MHz and the clock frequency is 100 MHz. An anti-

aliasing filter must follow the reconstruction DAC to remove the lower frequency (100 - 30 =70

MHz) as shown in the figure below.



Since we have an output between 7.2 MHz and 9.2 MHz the filter needs to be a low Band pass filter.

Band-pass filters

As per J. Vankka (2005) DDS has constraints to reach higher frequencies due to large frequency ratio

between clock and output signal frequencies. Finateu, T (2007) said that meeting RF communication

system requirements are strongly affected by this drawback.

There are applications where a particular band, or spread, or frequencies need to be filtered from a

wider range of mixed signals. Filter circuits can be designed to accomplish this task by combining the

properties of low-pass and high-pass into a single filter. The result is called a band-pass filter.

(http://www.allaboutcircuits.com/vol_2/chpt_8/4.html).

Creating a band pass filter from a low-pass and high-pass filter is shown using block diagrams:



System level block diagram of a band-pass filter.

What emerges from the series combination of these two filter circuits is a circuit that will only allow

passage of those frequencies that are neither too high nor too low. Using real components, here is

what a typical schematic might look like

Design of a single supply Band pass filter

Design Procedure

1. Put the value of C1=C2

2. Calculate R1=R4 = 1/ 2 *π * C1*Frequency

Q (gain) = 10 dB

Q= (R3+R4)/2R1



3. Calculate R3= 19*R1

4. Calculate R2= R1/19

5. Put the value of Cin =Cout which should be 200 times C1

In case we have two supplies just change the earth connection as the – ve supply

The band pass filters can also be used to generate waveforms above Nyquist frequency the replicated

images can be filtered to extract the desired image and the sampled signals duplicate at multiples of

the sampling frequency (Fout nFs) Xian Qijun(2008)

DDS various applications such as radio, instrumentation and radar system. The older version of DDS

have been troubled by large and unpredictable Spurious responses but now a days the spurs are small,

we can plan to place the spurs outside the bandwidth of interest . In AD 9834 we see that the

application only uses fraction of the output spectrum and attenuate the rest with the help of external

filters. As discussed before that the bandwidth of interest is typically between 0 Hz to about 40 % of

the clock or sampling frequency. This sub-Nyquist limitation is due to transition band of the external

image rejection filter as per Brandon. David (2004).

Conclusion

Summary of Features in AD9834 are as follows:

(i) A high resolution frequency of three different types of waveform is generated: sine wave, square

wave and triangular wave. We were concerned about the sine wave. The output frequency the chip is

changed by changing the value of the phase accumulator.

(ii)Due to crystal locked output frequency, there is a stable output frequency since there is no time &

temperature drift for the frequency.

(iii) Theoretically, the AD9834 is able to generate a maximum output frequency of fMCLK/2. The

maximum clock frequency that can be used by the AD9834 is 75 MHz. Therefore, the chip is able to

generate a highest frequency of 37.5MHz.

(iv) It had been used for digital communication system, spectrum systems which are spread.

(v) In future the synthesizers will have higher clock speeds and lower spur levels.

(vi) Appropriate in terms of size, switching frequency, resolution, fixedness and accuracy

The project was successful because most of the objectives were completed and more over

there were added objectives which were completed.

Background information was collected effectively and there was a deep understanding about the direct

digital synthesis and applications of direct digital synthesizers.



The Evaluation board was used to test the effectiveness of obtaining the precision wave forms

between the range of 7.2 MHz and 9.2 MHz with a step size of 10 KHz.

There was precise phase control without affecting the output frequencies.

The basic functioning of a direct digital synthesizer was understood, the required input sources for the

output frequencies were kept in consideration.

Got specific output frequency since Fout = FTW * MCLK / 2^N where FTW is the register

value for setting the output frequency and N is the size of the register. With the AD9834 N =

28. To solve for a FTW for a desired output frequency, FTW = (Fout / MCLK) * 2^N. The

changes in an output frequency were established.

Both the time domain as well as the frequency domain was taken into consideration getting

both oscilloscopes as well as spectrum analyzer in to usage. There was a detailed study and

practical experiment done to find out the usage of the evaluation board.

Prototype development on the sources of spur and errors in a direct digital synthesizer and

practically observation with the help of spectrum analyzer. Solutions were researched and

developed to reduce the spur. Basic designing of a lab view programme which explained the

functioning of a direct digital synthesizer. Design considerations for a filter was taken into

account and a designing of a band pass filter. 201 different readings were taken and the

design tool ADI Sim DDS was used effectively to evaluate the general simulated

performance of the AD 9834 DDS chip. The tool used mathematical equations to

approximate the overall performance of AD9834 and calculated all possible errors. Two

different interactive design tools were used effectively (refer appendices).

Designing a lab view program to input serial data was learnt and the initial stage of

development was undertaken by developing a lab view programme for explaining the

functioning of a DDS.

Consideration was given to appropriate technologies which have been developed as well as

broader area of practical implementation of a direct digital synthesizer.

In addition to personal and supervisors input there was additional input taken from the

engineer zone of Analog devices and high level of achievement in gaining knowledge by

external support of Dr. Liam, Dr. Kevin G from Analog devices.



Further Work –

Developing a lab view Programme to practically input serial data on to a DDS.

Use a system development platform (SDP) to build, demonstrate, and prototype embedded

systems and to connect it to the evaluation board, through the use of interposer and 3rd party

boards.

As discussed earlier AD9834 is ideal agile frequency source in the transmitter section of the

sonobuoy, so a further task would be to develop a sonobuoy for are the detection,

localization, identification, and tracking of seismic events and underwater targets such as

submarines and whales.



Project Management and Costing

The project was started as a design engineering project. There was a need of the lab. There

was a meeting with the project supervisor at least once in two weeks

Microsoft Project was used to assist in developing the plan and also to assign resources, to

analyse the various work load and it also helped in managing the budget. There was

continuous review during the project process. The Initial costing of the devices was

calculated from the websites of analog devices and national instruments though the

evaluation board was available we have calculated the cost in order to analyse the real cost in

case we would have to undertake this project from the scratch in a Business environment.

There were few reviews which were taken in to considerations from the initial plan, due to

little delay in getting the oscilloscope and spectrum analyser we had to delay the practical

reading of the direct digital synthesizer. Additionally a mind map was created which focussed

on the learning’s form the project in stages hence making the project move in a flow.









A Mind Map was made which summarised the tasks as well as the outcomes of Project.



Costing

The total costing involves the material cost, cost of supervision and the cost of man power in

case the project was supposed to be carried out in a real environment.

Material cost:

Most of the hardware was available but in case the project was carried out in a real practical

environment there would be a need to buy all these hardware and software.

Material and instrument Cost

Direct Digital Synthesizer(Eval AD9834) £60.83

Cost of the Wires £10

Cost of lab view software £12.29

Connectors £3.5

Cost of spectrum analyser £20,095

Total £20181.62

In case of practical work we would not need the test equipment’s for the whole time hence

we would have hired the equipment’s, instead of buying it to make it economical. So the

hiring cost is 50£ per week (http://www.hotfrog.co.uk/Companies/Watt-Power-Test-Test-

Equipment/Test-and-Measurement-Equipment-168294)

Hence the total cost of the material = 60.83+10+12.29+3.5+50 = £ 136.62

http://www.hotfrog.co.uk/Companies/Watt-Power-Test-Test-Equipment/Test-and-Measurement-Equipment-168294

http://www.hotfrog.co.uk/Companies/Watt-Power-Test-Test-Equipment/Test-and-Measurement-Equipment-168294



Supervision cost:

There was regular meeting with the supervisor which was held once to twice in every two

weeks and 1 hour per week in the first semester and every week in the second semester; the

fee of supervision was set as 60 pounds per hour. In total there was more than 41 hours of

supervision direct or indirect by the project supervisor as well as the engineer zone( Analog

devices)

The total supervision cost = 60*1*41 = £2460

Manpower cost:

The whole project was completed in 24 weeks, and every week approximately 18 hours was

spent in the project. The cost of man power is set as 8 pounds per hours.

The total manpower cost = 24*18*8

= 3456 pounds

Therefore,

the total project cost = material cost+ manpower cost+ supervision cost

= 136.32+2460+3456

= 6052.62 Pounds



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Appendices

Schematic Diagram of DDS AD9834



EAVLUATION BOARD AD9834 of Analog Devices

Documents

Computer Control Of a Direct Digital Synthesizer