Computer Architecture Project #2 Cache Simulator

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Seoul National University

Computer Architecture Project #2

Cache Simulator

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Objectives To understand cache memory

Organization Set associativity

Operation Cache Read & Write, Hit & Miss LRU replacement policy

Performance Hit/miss ratio, miss penalty

To develop your own cache simulator

Cache Simulator

MemoryAccessPattern

CacheOrganization

DisplayOption

Hit/Miss Performance

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General Cache Organization (S, E, B)

E = 2e lines per set

S = 2s sets

set

line

0 1 2 B-1tagv

B = 2b bytes per cache block (the data)

Cache size:C = S x E x B data bytes

valid bit

If e = 1, “Direct Mapped Cache”else If s = 1, “Fully Associative Cache”else “E-Way Set Associative Cache”

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E-way Set Associative Cache (Here: E = 2)E = 2: Two lines per setAssume that cache block size is 8 bytes

t bits 0…01 100Address of short int:

0 1 2 7tagv 3 654 0 1 2 7tagv 3 654

0 1 2 7tagv 3 654 0 1 2 7tagv 3 654

0 1 2 7tagv 3 654 0 1 2 7tagv 3 654

0 1 2 7tagv 3 654 0 1 2 7tagv 3 654

find set

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E-way Set Associative Cache (Here: E = 2)


0 1 2 7tagv 3 654 0 1 2 7tagv 3 654

compare both

match: yes = hit

block offset

tag

valid? +

E = 2: Two lines per setAssume that cache block size is 8 bytes

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E-way Set Associative Cache (Here: E = 2)


0 1 2 7tagv 3 654 0 1 2 7tagv 3 654

compare both

valid? + match: yes = hit

block offset

short int (2 Bytes) is here

No match : • One line in set is selected for eviction and replacement• Replacement policies: random, least recently used (LRU), …

E = 2: Two lines per setAssume that cache block size is 8 bytes

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LRU Replacement Policy Theoretically…

Practically…

Address 1 2 3 4 1 2 3 1 2 3 4 5

Set 1 2 3 4 1 2 3 1 2 3 4 5

1 2 3 4 1 2 3 1 2 3 4

1 2 3 4 1 2 3 1 2 3

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Performance (Average Access Time) = (Hit Time) + (Miss Rate) × (Miss Penalty)

= (Hit Time) + [1 – (Hit Rate)] × (Miss Penalty)

Example Suppose cache hit time is 1 cycle, Miss penalty is 100 cycles, and hit rate is 97%. Then average access time is:

1 cycle + ( 1 – 0.97 ) × 100 cycles = 1 + 0.03 × 100 = 4 cycles.

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Requirements of the cache simulator (1) Cache simulator (hereinafter referred to CSIM) shall implement ar-

bitrary numbers of sets and lines, and block size. You should implement a way to provide the numbers of sets and lines, and

block size as inputs to CSIM. CSIM shall a read trace file line by line and process it.

You should determine whether each memory operation is a cache hit or miss.

You should implement the LRU replacement policy CSIM shall report the result of cache simulation.

You should report these three basic results: numbers of Hits, misses, and evicts You should be able to report the average access time of cache simulation You should be able to report whether each memory access in trace file results

in a cache hit or miss

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Restrictions & Advices Implement method for input parameters.

You should implement it by argument passing. (full credit) If you can’t, you can use standard input such as scanf(). (low credit)

Evaluate only data cache performance. Therefore, you should ignore instruction load. You should assume that the memory accesses are aligned properly.

Therefore, you can ignore requested size in trace file. You should evaluate your CSIM with, at least, 3 different trace data. You can

use one provided with this project. Calculate average access time using below assumption:

Hit time = 1 cycle, miss penalty = 100 cycles. Compile your CSIM without warnings.

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How to trace memory accesses “valgrind”

GPL licensed programming tool for memory debugging, memory leak detection, and profiling. (from http://en.wikipedia.org/wiki/Valgrind)

Usage: >> valgrind -log-fd=1 --tool=lackey -v --trace-mem=yes ls -l– Valgrind prints out memory accesses of “ls -l” on stdout, so you need

to capture it by:>> valgrind -log-fd=1 --tool=lackey -v --trace-mem=yes ls -l > ls.trace

Output Format: [space]operation address,sizeOutput Type Example Naccess [space]

I 0400d7d4,8 Instruction load All instructions 1 X

L 04f6b868,8 Data Load movl (%eax), %ebx 1 O

S 7ff0005c8,8 Data Store movl %eax, (%ebx) 1 O

M 0421c7f0,4 Data Modify incl (%ecx) 2 O

http://en.wikipedia.org/wiki/Valgrind

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Reference Cache Simulator Usage: >>./csim [-v] -s <s> -E <E> -b <b> -t <trace file>

-v: Optional verbose flag that displays trace info -s <s>: Number of set index bits (S = 2s is the number of sets) -E <E>: Associativity (number of lines per set) -b <b>: Number of block bits (B = 2b is the block size) -t <trace file>: Name of the valgrind trace to replay

S = 2s sets

set

line

0 1 2 B-1tagv

B = 2b bytes per cache block (the data)

Cache size:C = S x E x B data bytes

valid bit

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Cache Simulation Example (1) Usage: >>./csim [-v] -s <s> -E <E> -b <b> -t <trace file> Example: >>./csim -v -s 4 -E 1 -b 4 -t ./traces/yi.trace

Number of set index bits = 4 (16 sets) Associativity = 1 (Direct Mapped Cache) Number of block bits = 4 (16 blocks in a cache line)

Output L 10,1 miss M 20,1 miss hit….hits: 4 misses:5 eviction: 3

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Cache Simulation Example (2) Example memory access pattern

Oper. Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 I

2 I

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

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Cache Simulation Example (3)

R/W Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 V 0x0

2 I

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

Hit Miss Evict

0 1 0

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R/W Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 V 0x0

2 V 0x0

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

Hit Miss Evict

1 2 0

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R/W Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 V 0x0

2 V 0x0

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

Hit Miss Evict

2 2 0

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R/W Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 V 0x0

2 V 0x0

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

Hit Miss Evict

3 2 0

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R/W Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 V 0x1

2 V 0x0

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

Hit Miss Evict

3 3 1

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R/W Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 V 0x2

2 V 0x0

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

Hit Miss Evict

3 4 2

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R/W Address Byte

Load 0x10 1

Modify 0x20 1

Load 0x22 1

Store 0x18 1

Load 0x110 1

Load 0x210 1

Modify 0x12 1

S V Tag 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 I

1 V 0x0

2 V 0x0

3 I

4 I

5 I

6 I

7 I

8 I

9 I

A I

B I

C I

D I

E I

F I

Hit Miss Evict

4 5 3

Average Access Time= 1 + (5 / 9) * 100 = 56.5 Cycle

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보고서 작성요령 (1) 아래의 내용을 포함할 것

설계 요구사항 제시된 CSIM 의 설계 요구사항을 자신의 CSIM 에 맞춰

재정의 구현

자신의 CSIM 이 어떤 식으로 동작하며 어떻게 설계 요구사항을반영하는지 서술

자신의 CSIM 의 사용법과 시뮬레이션 결과 출력 방법에 대해 서술 시험

CSIM 의 요구사항을 어떤 방법으로 검증하였는지 서술 최소 3 가지 Trace Data 를 이용하여 검증 수행

추가적으로 , Trace Data 를 어떤 방법으로 얻었는지를 서술 CSIM 구현 내용을 알 수 있도록 캡쳐된 이미지를 첨부할 것

설계

구현

시험

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보고서 작성요령 (2) 아래의 내용을 포함할 것

성능 평가 각각의 Cache 구조 (direct mapped, E-way set

associative 및 fully associative cache) 별로 성능을 측정하고 각각을비교할 것

Design

Coding

Testing

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평가기준Title Pts. Description Pts. Details

CSIM 70 제출 10 Warning: 각 -0.5 pt. / Error: 각 -1 pt.

Parameter Input 10 Argument Passing: 10 pts., Other methods: 5 pts.

Cache Organization 5 Dynamic allocation 사용 시 : 5 pts.- 배열 사용 시 : 2 pts.

Cache Operation 20 Hit/miss 의 정확한 처리 : 10pts.Replacement policy (LRU): 5 pts- implementing random replacement: 3pts.각각의 Memory Access 에 대한 결과 (Hit/Miss) 시현 : 4pts.- 결과 시현 여부를 선택할 수 있는 옵션 제공 : 1pts.

성능 평가 5 정확한 Average Access Time 의 제공

주석 10 최대한 각각의 라인에 주석을 제공

보고서 30 설계 요구사항 7

구현 7

시험 8

성능 평가 8

제출지연 매 1 일 당 -5 제출 기한 1 주일까지 제출 가능

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제출방법 아래 제출 목록의 산출물들을 메일로 제출

E-mail address: [email protected] E-mail 제목 : “[CSIM] 학번 _ 이름” 산출물들은 “학번 _ 이름 .zip” 또는 “학번 _ 이름 .tar” 으로 압축하여 제출

제출 목록 CSIM source code Project 보고서 CSIM 의 검증 시 사용한 Trace file

제출 기한 : ’13. 12. 18( 수 ) 23:59 까지

mailto:[email protected]

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Computer Architecture Project #2 Cache Simulator