ECE540 COMPUTER ORGANIZATION AND ARCHITECTURE

Register Transfer and Microoperationbharat.sanklecha@lpu.co.inBlock 33 Room no : 203 Cabin no : 29

MICROOPERATION An elementary operation performed during one clock pulse, on the information stored in one or more registers

R f(R,R)

f: shift, count, load, clear, add..

REGISTER TRANSFER LANGUAGEDefinition of organization of a computer:

1. The set of registers and their functions;2. The sequence of microoperations;3. The control that initiates the sequence of microoperationsFor any function of the computer, a sequence of microoperations is used to describe it

Register transfer languageA symbolic languageA convenient tool for describing the internal organization of digital computersCan also be used to facilitate the design process of digital systems.

REGISTER TRANSFERDesignation of a register a registerPortion of a registerA bit of a registerCommon ways of drawing the diagram of a register

Representation of a transfer (parallel)R2R1 A simultaneous transfer of all bits from the source to the destination register, during one clock pulseRepresentation of a controlled (conditional) transferP : R2R1A binary condition (p=1) which determines when the transfer is to occur If (p=1) then (R2R1)

HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERSImplementation of controlled transferP: R2R1 Block diagram

Timing diagram

Basic symbols for register Transfer

Represent the following conditional control statement by two register transfer statements with control functions:IF (P=1) then (R1R2)

Else if (Q=1) then (R1R3)

Show the block diagram of the hardware that implements the following register transfer statement:

yT2: R2 R1, R1R2

The outputs of four registers, R0, R1, R2, and R3, are connected through 4-to-1-line multiplexers to the inputs of a fifth registers, R5. Each register is eight bits long. The required transfers are dictated by four timing variables T0 through T3 as follows:

T0: R5R0 T1: R5R1 T2: R5R2 T3: R5R3The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load inputs of register R5.

BUS AND MEMORY TRANSFERPaths must be provided to transfer information from one register to anotherA Common Bus System is a scheme for transferring information between registers in a multiple-register configurationA bus: set of common lines, one for each bit of a register, through which binary information is transferred one at a timeControl signals determine which register is selected by the bus during each particular register transfer

BUS AND MEMORY TRANSFER

3 2 1 0Register DD3 D2 D1 D0

3 2 1 0Register CC3 C2 C1 C0

3 2 1 0Register BB3 B2 B1 B0

3 2 1 0Register AA3 A2 A1 A0

D3 C3 B3 A3 S0S1MUX33 2 1 0

D2 C2 B2 A2 S0S1MUX23 2 1 0

D1 C1 B1 A1 S0S1MUX13 2 1 0

D0 C0 B0 A0 S0S1MUX03 2 1 0

4-Line Common Bus

A digital computer has a common bus system for 16 register of 32 bits each. The bus is constructed with multiplexers.

How many selection inputs are there in each multiplexers.What size of multiplexers are needed?How many multiplexers are there in the bus?

BUS AND MEMORY TRANSFERSThe transfer of information from a bus into one of many destination registers is done:By connecting the bus lines to the inputs of all destination registers and then: activating the load control of the particular destination register selectedWe write: R2 C to symbolize that the content of register C is loaded into the register R2 using the common system bus It is equivalent to: BUS C, (select C)

R2 BUS (Load R2)

THREE-STATE BUS BUFFERSA bus system can be constructed with three-state buffer gates instead of multiplexersA three-state buffer is a digital circuit that exhibits three states: logic-0, logic-1, and high-impedance (Hi-Z)

Normal input AControl input CThree-State BufferOutput B

THREE-STATE BUS BUFFERS

AC=1BAB

AC=0BABBufferOpen Circuit

THREE-STATE BUS BUFFERS

24 Decoder

SelectEnable0123S1S0EBus line for bit 0A0B0C0D0Bus line with three-state buffer (replaces MUX0 in the previous diagram)

Draw a diagram of a bus system similar to the one shown in previous diagram, but use three-state buffers and a decoder instead of the multiplexers.

MEMORY TRANSFERMemory read : Transfer from memoryMemory write : Transfer to memoryData being read or wrote is called a memory word (called M)It is necessary to specify the address of M when writing /reading memoryThis is done by enclosing the address in square brackets following the letter MExample: M[0016] : the memory contents at address 0x0016

MEMORY TRANSFERAssume that the address of a memory unit is stored in a register called the Address Register ARLets represent a Data Register with DR, then:Read: DR M[AR]Write: M[AR] DR

cpe 252: Computer Organization*MEMORY TRANSFER

ARx12

x0Cx0Ex10x12x14x16x181934456601322R1M[AR]

R1100

R166

RAM

R1100

The following transfer statements specify a memory. Explain the memory operation in each case.

R2M[AR]M[AR]R3R5M[R5]

(a) Read memory word specified by the address in AR into register R2.(b) Write content of register R3 into the memory word specified by the address in AR.(c) Read memory word specified by the address in R5 and transfer content to R5 (destroys previous value)

MICROOPERATIONSThe microoperations most often encountered in digital computers are classified into four categories:Register transfer microoperationsArithmetic microoperations (on numeric data stored in the registers)Logic microoperations (bit manipulations on non-numeric data)Shift microoperations

The basic arithmetic microoperations are: addition, subtraction, increment, decrement, and shiftAddition Microoperation:

R3 R1+R2Subtraction Microoperation:

R3 R1-R2 or :R3 R1+R2+1ARITHMETIC MICROOPERATIONS1s complement

Ones Complement Microoperation:

R2 R2Twos Complement Microoperation:

R2 R2+1Increment Microoperation:

R2 R2+1Decrement Microoperation:

R2 R2-1ARITHMETIC MICROOPERATIONS

Draw the circuit diagram and truth table of half adder and full adder using basic gates.

HALF ADDER/FULL ADDERHalf Adder0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1cn = xy + xcn-1+ ycn-1 = xy + (x y)cn-1

s = xycn-1+xycn-1+xycn-1+xycn-1 = x y cn-1 = (x y) cn-1

xycn-1xycn-1

cnsc = xy s = xy + xy = x y

xycn-1S

cnFull Adderx y cn-1 cn s0010011101011010

Implement four bit full adder using 1-bit full adder?

ARITHMETIC MICROOPERATIONS BINARY ADDERC0A0B0S0A1B1S1A2B2S2A3B3S3C1C2C3C44-bit binary adder (connection of FAs)

Draw the block diagram for the hardware that implements the following statements:

x+yz: ARAR+BRwhere AR and BR are two n-bit registers and x,y, and z are control variables. Include the logic gates for the control function.

TERM PAPER Last date for submission of topic 27 Jan 2015Last date for submission of synopsis 17 Feb 2015 (Marks :5 )

Implement 4-bit adder cum subtractor in one circuit.

ARITHMETIC MICROOPERATIONS BINARY ADDER-SUBTRACTORC0A0B0S0A1B1S1A2B2S2A3B3S3C1C2C3C44-bit adder-subtractor

MM=0 AdditionM=1 Subtraction

Design incrementer circuit for four bit register using half adder?

ARITHMETIC MICROOPERATIONS BINARY INCREMENTER

CSxyHA

CSxyHA

CSxyHA

CSxyHAS0S1S2S3C41A0A1A2A34-bit Binary Incrementer

ARITHMETIC CIRCUIT

Design decrementer circuit for four bit register using full adder?

A 1 = A + 2s complement of 1 = A + 1111

B0ARITHMETIC MICROOPERATIONS ARITHMETIC CIRCUIT

3 2 1 0 S1 S041 MUX

FA

FA

FA

FACinD0D1D2D3C1C2C3CoutB010S1S0B1

3 2 1 0 S1 S041 MUXB110S1S0B2

3 2 1 0 S1 S041 MUXB210S1S0B3

3 2 1 0 S1 S041 MUXB310S1S0A0A1A2A34-bit Arithmetic CircuitX0Y0X1Y1X2Y2X3Y3

ARITHMETIC CIRCUITThis circuit performs seven distinct arithmetic operations and the basic component of it is the parallel adderThe output of the binary adder is calculated from the following arithmetic sum:D = A + Y + Cin

LOGIC MICROOPERATIONORANDNOTXOROther logic operation

LOGIC MICROOPERATIONS OR MicrooperationSymbol: , +

Gate:

Example: 1001102 10101102 = 11101102

P+Q: R1R2+R3, R4R5 R6

OR

OR

ADD

LOGIC MICROOPERATIONSAND MicrooperationSymbol:

Gate:

Example: 1001102 10101102 = 00001102

LOGIC MICROOPERATIONS

Complement (NOT) MicrooperationSymbol:

Gate:

Example: 10101102 = 01010012

LOGIC MICROOPERATIONSXOR (Exclusive-OR) MicrooperationSymbol:

Gate:

Example: 1001102 10101102 = 11100002

OTHER LOGIC MICROOPERATIONSSelective-set OperationUsed to force selected bits of a register into logic-1 by using the OR operation

Example: 01002 10002 = 11002

In a processor registerLoaded into a register from memory to perform the selective-set operation

OTHER LOGIC MICROOPERATIONSSelective-complement (toggling) OperationUsed to force selected bits of a register to be complemented by using the XOR operation

Example: 00012 10002 = 10012

In a processor registerLoaded into a register from memory to perform the selective-complement operation

OTHER LOGIC MICROOPERATIONSInsert OperationStep1: mask the desired bitsStep2: OR them with the desired value

Example: suppose R1 = 0110 1010, and we desire to replace the leftmost 4 bits (0110) with 1001 then:Step1: 0110 1010 0000 1111Step2: 0000 1010 1001 0000 R1 = 1001 1010

OTHER LOGIC MICROOPERATIONSNAND MicrooperationSymbols: and

Gate:

Example: 1001102 10101102 = 11110012

OTHER LOGIC MICROOPERATIONS NOR MicrooperationSymbols: and

Gate:

Example: 1001102 10101102 = 00010012

OTHER LOGIC MICROOPERATIONSSet (Preset) MicrooperationForce all bits into 1s by ORing them with a value in which all its bits are being assigned to logic-1Example: 1001102 1111112 = 1111112

Clear (Reset) MicrooperationForce all bits into 0s by ANDing them with a value in which all its bits are being assigned to logic-0Example: 1001102 0000002 = 0000002

LOGIC MICROOPERATIONS HARDWARE IMPLEMENTATIONThe hardware implementation of logic microoperations requires that logic gates be inserted for each bit or pair of bits in the registers to perform the required logic functionMost computers use only four (AND, OR, XOR, and NOT) from which all others can be derived.

*LOGIC MICROOPERATIONSHARDWARE IMPLEMENTATION

S1S0012341 MUXEiAiBiThis is for one bit i

S1S0OutputOperation00E = A BXOR01E = A BOR10E = A BAND11E = AComplement

LOGIC MICROOPERATIONS

SHIFT MICROOPERATIONSUsed for serial transfer of dataAlso used in conjunction with arithmetic, logic, and other data-processing operationsThe contents of the register can be shifted to the left or to the rightAs being shifted, the first flip-flop receives its binary information from the serial inputThree types of shift: Logical, Circular, and Arithmetic

SHIFT MICROOPERATIONS

r0r1r3rn-1

r0r1r2r3rn-1Shift RightShift LeftSerial InputSerial OutputSerial OutputSerial Input

Determines the shift typer2**Note that the bit ri is the bit at position (i) of the register

SHIFT MICROOPERATIONS: LOGICAL SHIFTSTransfers 0 through the serial inputLogical Shift Right: R1shr R1

Logical Shift Left: R2shl R2

The sameThe sameLogical Shift Left?0

r0r1r2r3rn-1

CIRCULAR SHIFTS (ROTATE OPERATION)Circulates the bits of the register around the two ends without loss of informationCircular Shift Right: R1cir R1

Circular Shift Left: R2cil R2

The sameThe sameCircular Shift Left

r0r1r2r3rn-1

ARITHMETIC SHIFTSShifts a signed binary number to the left or rightAn arithmetic shift-left multiplies a signed binary number by 2: ashl (00100): 01000An arithmetic shift-right divides the number by 2

ashr (00100) : 00010An overflow may occur in arithmetic shift-left, and occurs when the sign bit is changed (sign reversal)

ARITHMETIC SHIFTS Arithmetic Shift RightSign BitArithmetic Shift LeftSign Bit?0?

r0r1r2r3rn-1

r0r1r2r3rn-1

ARITHMETIC SHIFTSAn overflow flip-flop Vs can be used to detect an arithmetic shift-left overflow

Vs = Rn-1 Rn-2Rn-2Vs=Rn-1

1 overflow0 no overflow

SHIFT MICROOPERATIONS Example: Assume R1=11001110, then:Arithmetic shift right once : R1 = 11100111Arithmetic shift right twice : R1 = 11110011Arithmetic shift left once : R1 = 10011100Arithmetic shift left twice : R1 = 00111000Logical shift right once : R1 = 01100111Logical shift left once : R1 = 10011100Circular shift right once : R1 = 01100111Circular shift left once : R1 = 10011101

SHIFT MICROOPERATIONS HARDWARE IMPLEMENTATION A possible choice for a shift unit would be a bidirectional shift register with parallel load Has drawbacks:Needs two pulses (the clock and the shift signal pulse)Not efficient in a processor unit where multiple number of registers share a common busIt is more efficient to implement the shift operation with a combinational circuit

SHIFT MICROOPERATIONS HARDWARE IMPLEMENTATION

S10

S10

S10

S10

A3A2A1A0Serial Input IRSerial Input ILSelect0 for shift right1 for shift leftH3H2H1H0MUXMUXMUXMUX4-bit Combinational Circuit Shifter

ARITHMETIC LOGIC SHIFT UNITInstead of having individual registers performing the microoperations directly, computer systems employ a number of storage registers connected to a common operational unit called an Arithmetic Logic Unit (ALU)

ARITHMETIC LOGIC SHIFT UNIT

0123

S3S2S1S0BiAiAi+1Ai-1Select41 MUXCiCi+1One stage of arithmetic circuit (Fig.A)One stage of logic circuit (Fig.B)DiEiFishrshlOne stage of ALU

B0ARITHMETIC MICROOPERATIONS ARITHMETIC CIRCUIT

3 2 1 0 S1 S041 MUX

FA

FA

FA

FACinD0D1D2D3C1C2C3CoutB010S1S0B1

3 2 1 0 S1 S041 MUXB110S1S0B2

3 2 1 0 S1 S041 MUXB210S1S0B3

3 2 1 0 S1 S041 MUXB310S1S0A0A1A2A34-bit Arithmetic CircuitX0Y0X1Y1X2Y2X3Y3

*LOGIC MICROOPERATIONSHARDWARE IMPLEMENTATION

S1S0012341 MUXEiAiBiThis is for one bit i

S1S0OutputOperation00E = A BXOR01E = A BOR10E = A BAND11E = AComplement