Computer Arch

Computer Architecture Project

MULTIPLICATION AND DIVISION ALGORITHMS

Presented by:

Manpreet Bhullar & Matt Hattersley

Instructor: Prof. Ten EyckCourse: Computer Architecture

(CMSC 415)


Binary Multiplication

147 10010011 Multiplicand* 85 * 01010101 Multiplier

10010011 00000000

10010011 00000000 10010011 00000000 10010011 00000000

12495 011000011001111 Product


1. TestMultiplier0

64th repetition?

3. Shift the M’plier register right 1 bit

2. Shift the M’cand register left 1 bit

1a. Add multiplicand to product & place the result in Product register

Multiply Algorithm Version 1

Done

Yes: 64 repetitions

No: < 64 repetitions

Multiplier0 = 0Multiplier0 = 1


Multiplication Hardware 1

32-bit product

32-bit ALU

Shift_left

Shift_right

WriteControl

16 bits

64 bits

32 bits

32-bit multiplicand

lsb

16-bit multiplier


Multiplication Hardware

Product: initialized to all 0’s Control: decides when to shift the Multiplier

and Multiplicand registers and when to write new values to Product register

At the end, the multiplier is out of the product register and the product contains the result


Step-by-step transition in the registers during the multiplication process 1

For Version 1:


Thinking about new algorithm…

Changes can be made: -instead of shifting multiplicand left, shift product right -adder can be shortened to length of the multiplier &

multiplicand(8 bits in our example) -place multiplier in right half of the product

register(multiplier will disappear as product is shifted right

-add multiplicand to left half of product


Multiply Algorithm Final Version

1. TestProduct00

64th repetition?

2. Shift the Product register right 1 bit.

1a. Add multiplicand to the left half of product & place the result in the left half of Product register

Done

Yes: 64 repetitions

No: < 64 repetitions

Product = 0Product = 1


Step-by-step transition in the registers during the multiplication process (Final)

For FinalVersion :


Multiplication Hardware(Final)

product

16-bit ALU

Shift_left

Shift_right

WriteControl Test

16 bits

32 bits

multiplicand


Multiply in MIPSCan multiply variable by any constant using MIPS sll and add instructions:

i' = i * 10; /* assume i: $s0 */

sll $t0, $s0, 3 # i * 23

add $t1, $zero, $t0sll $t0, $s0, 1 # i * 21

add $s0, $t1, $t0

MIPS multiply instructions: mult, multu

mult $t0, $t1– puts 64-bit product in pair of new registers hi, lo; copy to $n by mfhi,

mflo – 32-bit integer result in register lo


Multiplying Signed numbers

Main difficulty arises when signed numbers are involved.

Naive approach: convert both operands to positive numbers,

multiply, then calculate separately the sign of the

product and convert if necessary.

A better approach: Booth’s Algorithm.

Booth’s idea: if during the scan of the multiplier, we observe a

sequence of 1’s, we can replace it first by subtracting the multiplicand

(instead of adding it to the product) and later, add the multiplicand,

after seeing the last 1 of the sequence.


0110 x 0011 (6x3) This can be done by (8- 2) x3 as well, or (1000 - 0010) x 0011 (using 8 bit words)

At start, product = 00000000, looking at each bit of the multiplier 0110, from right to left:

0: product unchanged: 00000000 ,

shift multiplicand left: 00110

1: start of a sequence:

subtract multiplicand from product: 00000000 - 00110 = 11111010 ,


1: middle of sequence, product unchanged: 11111010,


0: end of sequence:

add multiplicand to product: 11111010 + 0011000 = 00010010 = 18


For Example:


Booth’s Algorithm

Scan the multiplier from right to left, observing, at each step, both the current bit and the previous bit:

1. Depending on (current, previous) bits:

00 : Middle of a string of 0’s: do no arithmetic operation.

10 : Beginning of a string of 1’s: subtract multiplicand.

11 : Middle of a string of 1’s: do no arithmetic operation.

01 : End of a string of 1’s: add multiplicand.

2. Shift multiplicand to the left.


Integer Division

0001 1001 quotient (25)(10) 0000 1010 divided into 1111 1010 dividend (250)

-1010 1011

-1010 10 101 1010 -1010

0 remainder


Division Algorithm 1

2b. Restore the original value by adding the Divisor register to the Remainder register, &place the sum in the Remainder register. Alsoshift the Quotient register to the left, setting the new least significant bit to 0.

Test Remainder

Remainder < 0Remainder 0

1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.

2a. Shift the Quotient register to the left setting the new rightmost bit to 1.

3. Shift the Divisor register right 1 bit.

Done

Yes: n+1 repetitions (n = 8 here)

Start: Place Dividend in Remainder

n+1repetition?

No: < n+1 repetitions


Division Hardware

Remainder

Quotient

Divisor

16-bit ALU

Shift Right

Shift Left

WriteControl

8 bits

16 bits

16 bits


Integer Division

– ALU, Divisor, and Remainder registers: 16 bit; – Quotient register: 8 bits;– 8 bit divisor starts in left ½ of Divisor reg. and it is

shifted right 1 on each step– Remainder register initialized with dividend


Step-by-step transition in registors during division process1

For Version 1:


Division Algorithm (Final)

3b. Restore the original value by adding the Divisor register to the left half of Remainder register, &place the sum in the left half of Remainder register. Alsoshift the Remainder register to the left, setting the new rightmost bit to 0.

Test Remainder

Remainder < 0Remainder 0

2. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.

3a. Shift the Remainder register to the left setting the new rightmost bit to 1.

Done. Shift left half of Remainder right 1 bit Yes: n repetitions (n = 8 here)

Start: Place Dividend in Remainder

nrepetition?

No: < n repetitions

1. Shift the Remainder register left 1 bit


Division Hardware (Final)

Remainder

Divisor

8-bit ALU

Shift Right

WriteControl Test

8 bits

16 bits Shift Left


Step-by-step transition in registers during division process (Final)

For Final Version:


Mult/Div Hardware

Top half

Divisor/multiplicand

8-bit ALU Shift_left, shift_right

WriteControl

8 bits

16 bits Result/lsb

alu_control

msb

Carry-out of adder


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