23
LCD

Computer Aided System Design Laboratory

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16x2 LCD
(DD-RAM) (CG -RAM)
6
LCD
1000000000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
7
LCD()
X100000000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
8
LCD()
(Entry Mode)
I/D=0AC1 I/D=1AC1 SH=0 SH=1I/D=0
SH=1I/D=1
SHI/D10000000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
9
LCD
(Display on/off Control)
D=0D=1 C=0C=1 B=0B=1
BCD1000000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
10
(Cursor or Display Shift) (DDRAM)
S/C=0R/L=0 S/C=0R/L=1 S/C=1R/L=0
S/C=1R/L=1
XXR/LS/C100000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
11
(Function Set)(DL) (N)(F)
DL=18DL=04 N=0N=1 F=05x8F=15x11
XXFNDL10000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
12
data01
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
13
ASCII
14
LCD
SHI/D10000000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
1000000000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
BCD1000000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
XXFNDL10000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
XXXX110000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
XXXX110000
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS
8
15

16
LCD
(clk,start,clear,clkm:IN PUT ;
romdatai[7..0] :INPUT ; datai[7..0],mode :INPU T ; romaddro[5..0] :OUTP UT; en,r/w,d/i,db[7..0],tmdt : OUTPUT; )
variable stks[3..0],cntp[2..0],ssk[1..0],d[1. .0],cntd[4..0],cntm[5..0]:dff; dbnc:node;
begin stks[ ].clk=(clk); cntp[ ].clk=clk; ssk[ ].clk=clk; d[ ].clk=clk; cntd[ ].clk=clk; cntm[ ].clk=clkm;
if cntm[ ]==39 then cntm[ ]=0 ; else cntm[ ]=cntm[ ]+1; end if;
17
LCD ()
romaddro[ ]= cntm[5..0]; cntm[ ].clrn=!clear; cntd[ ].clrn=!clear; ssk[ ].clrn=!clear; stks[ ].clrn=!clear; cntp[ ].clrn=!clear; cntd[2..0]=cntd[2..0]+1; cntd3.d=cntd2.q; cntd4.d=cntd3.q; tmdt=cntd2 and !cntd4; d0.d = (start or clkm or clear); d1.d= d0.q; dbnc =((d0 AND d1) OR dbnc) AND (d0 OR d1); case ssk[ ] is when b"00"=> if dbnc==vcc then ssk[ ]=b"01"; else ssk[ ]=b"00"; end if; when b"01"=> ssk[ ]=b"10"; when b"10"=> if dbnc== gnd then ssk[ ]=b"00"; else ssk[ ]=b"10"; end if; when b"11"=> ssk[ ]=b"00"; end case; case stks[ ] is when b"0000"=> if (ssk0 ==vcc ) then stks[ ]=b"0001"; else stks[ ]=b"0000"; end if; when b"0001"=> stks[ ]=b"0010"; when b"0010"=> stks[ ]=b"0100"; when b"0100"=> stks[ ]=b"1000"; when b"1000"=> if (cntp[ ] ==0 or cntp[ ]==1 or cntp[ ]==2 or cntp[ ]==3 ) then stks[ ]=b"0001"; elsif (cntp[ ]==5 ) thenstks[ ]=b"0000"; else stks[ ]=b"1000"; end if; end case;
if (stks3 ==vcc) and (cntp[ ] !=5) then cntp[ ]=cntp[ ]+1; else cntp[ ]=cntp[ ]; end if; r/w = !(stks0 or stks1 or stks2) ; en = stks1 ; if(cntp[ ] ==5) and ((mode==vcc and datai7==gnd) or (mode==gnd and
romdatai7==gnd)) then d/i= (stks0 or stks1 or stks2) ; else d/i= !(stks0 or stks1 or stks2); end if; case cntp[ ] is when b"000"=> db[ ]=h"38"; when b"001"=> db[ ]=h"0e"; when b"010"=> db[ ]=h"06"; when b"011"=> db[ ]=h"01"; when b"100"=> db[ ]=h"80"; when b"101"=> if mode==gnd then if romdatai[7..6]==3 then db[ ]=(romdatai7,0,romdatai[5..0]); elsif romdatai[7..6]==2 then db[ ]=(0,romdatai[6..0]); else db[ ]=romdatai[ ]; end if; else db[ ]=datai[ ]; end if; end case; end;
18
LCD()
19

10LCDclk Verilog HDL module div10(clk_i,clk_o3); input clk_i; output clk_o3; wire clk_o3; reg [3:0] clk_o; assign clk_o3=clk_o[3]; always @ (posedge clk_i) if (clk_o= =4'b1001) clk_o<=4'b0000; else clk_o<=clk_o+1; endmodule
22
LCD
2323
LCD()
CPLD
11db[7]19e 12db[6]86IB25