Computer-Aided Design of Digital VLSI Circuits & Systems

Priyank KallaDept. of Elec. & Comp. Engineering

University of Utah,SLC

Perspectives on Next-Generation Logic Synthesis

Logic Synthesis in VLSI Realization

Specifications

Circuit Netlist

OptimizedNetlist

Tech. Mapping

Place & Route

Sequential Optimization

Cell Library

Objective:Generate Optimal Designs

Semi-Custom Design Styles

Semi-Custom

Cell-based Array-based

Std. Cells

HierarchicalStd. Cells

Macro cells

PLAMemory

Gate-ArraysMPGAsFPGAs

Choice of Design StylesCustom Semi-

custom

Gate-array

Density Very high High Medium

Performanc

e

Very high High Medium

Design time Very Long High Medium/low

Manufacturi

ng time

Medium Medium Short

Low volume

Cost

Very High High Low

High. Vol.

Cost

Low Low High

Design Representations

g Architectural4 F1 = A*A – B*B4 F2 = C*C – D*D4 F = x F1 + x’ F2

Transformation:4 F1 = (A-B)(A+B)4 F2 = (C-D)(C+D)4 F = x F1 + x’ F2

g Behavioural Transformations

s0

s1

s2

s3

s0

s1

s2

s3

s4

Transformation Criteria

g Architectural4 Resource Optimization4 Latency/Throughput Optimization4 Computation Scheduling, Resource Binding4 Testability and Verifiability

g Behavioural4 Logic Area4 Gate Delay (timing performance)4 Switching & Static Power Dissipation4 Testability and Verifiability

Minimization Versus Optimization

g Minimization versus Optimization Trade-offs4 Minimize Logic Area, or Delay, or Power….4 Optimize Area within bounded Delays4 Optimize Delay within bounded Area4 Physical Synthesis: Optimize Area w.r.t.

Reliability and Manufacturability

Delay…

Are

a…

What is Logic Synthesis?

g Given: Logic Functions or Finite-State Machines4 Automatically generate designs (synthesis)4 Minimize or Optimize Logic w.r.t. constraints4 Optimally map logic onto realistic gates

g Problems and Challenges4 Memory: Size! Size! SIZE! 4 Time: Computationally intensive operations4 What kind of representations to use?4 How to optimize logic to target the technology?

When Technology was PLAs….

g Two-Level Logic Minimization: K-map type4 F = a’bc + ab’c + abc’ + abc4 F = ab + ac + bc4 Fewer inputs = fewer transistors4 Reduced Area AND Reduced Delay4 Algorithmic Techniques: 4 Quine-McCluskey, Espresso, Signature-cubes

Then came CMOS Technology….

g Salient Features:4 Very high noise margins4 Design Scalability4 Enabled Standard Cell-based Design4 Abstract Electrical Properties: Area-Delay4 Fanout-Drive Scalability: X’sistor Sizing4 Low (zero) Static Power Dissipation4 Enabled Standard-Cell Place & Route4 Estimates: Close to ~10% of actual layout4 Cheap, Reliable, Scalable, low turn-aournd time

Multi-Level Logic Synthesis

g F = ab + bc + ac4 F = b(a + c) + ac4 F = ab + c(b + a)4 Problem: Area and Delay became dependent4 Problem: How do you factorize?

Multi-Level Synthesis for CMOS

g Synthesis Issues to consider4 Objective: Minimize number of literals (area)4 Delay: Depth of paths, fanouts, signal orders,

arrival and required times….4 Area Delay became dependent4 Factorization:

4Extract common subexpressions4Fanout problems4Routing Difficulties

4 Optimization (instead of minimization) became the dominant issue

Don’t Cares came into Focus….

g F = a(b+c)4 When a = 0, (b + c) = Don’t care4 D.C. = a’(b + c)? Not really….4 How to “generate” D.C. set to optimize logic?4 Problem: How do you factorize to create a good

don’t care set ?4 Problem: How to filter “bad” don’t care sets ?

Don’t Cares Computations…..

g How to efficiently compute D.C.s and simplify ckt?4 Image computations4 Controllability and observability DCs4 Propagate DC set across the circuit

Inp

ut

DC

Image of the DC

Solution: Sequence of Optimizations

g Script-based multi-level logic synthesis4 Collapse the whole circuit into two-level logic4 Apply K-map type two-level minimization4 Perform Greedy Factorization4 Compute Don’t Cares4 Simplify with Don’t cares4 Estimate area/delay, re-factorize if needed4 Delay minimization: depth minimization, fanout

adjustment, transistor sizing, buffer insertion….

Sequential Optimization

g Behavioural Transformations

s0

s1

s2

s3

s0

s1

s2

s3

s4

g Behavioural Optimizations:4 Code assignments: What is there effect on design?4 S0 (00), s1(01), s2(10), s3(11)4 S0(00), s1(10), s2(01), s3(11)

FPGA-based Logic Synthesis

g Look-up Table based FPGAs

g Optimizations Criteria:4 Input-space Partitioning, Decomposition4 Literal minimization does nothing here…..4 Routing resources, congestion……

Look-upTable

a b c f

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

The coming of age of Synthesis….

g Power of multi-level logic synthesis4 Two-level minimization: solved!4 Good factorization techniques found4 Good Boolean Decomposition techniques4 Good representations: ROBDDs…..4 Don’t care theory well understood4 Technological challenges well understood

(CMOS, FPGA, PLA, Memories….)

Some Problems Remain……

g Limitations of conventional synthesis techniques4 Sequential Optimizations not well understood4 Perhaps the problem has become redundant?4 Technology specific decomposition still needs

some work4 Not much support for hierarchical synthesis4 No support for across the boundary optimizations4 Power optimization at logic-level: NO IDEA!!4 Effect of factorization on Placement & routing

New Challenges in Logic Synthesis

g The problems of the future…..4 Static CMOS: area-delay will become

unacceptable4 Layout is already becoming unsolvable4 Static (leakage) power is increasing4 Design granularity…. Large v/s small4 Hierarchical synthesis will become a major issue4 NOISE! Dynamic logic related….

New Technologies to Synthesize

g Dynamic Logic4 Problems: Domino logic is monotonic4 Charge Sharing, leakage, noise….4 Standard-cell based or macro-cell based?

g Pass Transistor Logic (PTL)4 All of the above problems4 Signal degradation + restoration?

s

Need of the Hour: I think……

g Mixed Pass Transistor & Static CMOS Logic4 Area reduction due to PTL4 Delay reduction due to PTL & CMOS buffers4 Signal degradation + restoration can be solved4 Challenges: 4 Factorize to reduce noise4 What to map on PTL and what to map on CMOS?

s1

s2

CMOSGate

Large fanout

Need of the Future: I think……

g For new technologies, “nano”-type4 Area/Delay estimation Rethink4 Sequential Optimization will bounce back!4 Binary valued logic to Multi-values Logic4 Power has to be handled at logic level4 Memory no problem…. But computation time….4 Logic optimization for manufacturability…..4 Structured Logic Decomposition for estimatable

Placement and routing….4 How about “Synthesis for verifiablity” ?