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Computational Intelligence Techniques for Electronic Design Automation Bo Liu Department of Computing, Glyndwr University, UK ESAT-MICAS, Katholieke Universiteit Leuven, Belgium ([email protected], [email protected])

Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

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Page 1: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Computational Intelligence Techniques for Electronic Design Automation

Bo Liu

Department of Computing, Glyndwr University, UK

ESAT-MICAS, Katholieke Universiteit Leuven, Belgium

([email protected], [email protected])

Page 2: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Outline Electronic design and optimisation

Evolutionary algorithms in EDA: How it works and challenges Surrogate model assisted evolutionary algorithms (SAEA)

The SMAS framework, improvements and applications:

Medium-scale problem: automated design of complex antennas Constraint handling: automated design of mm-wave ICs Integer optimisation: NoC design optimisation Challenges and opportunities

Conclusions

Southampton Seminar 2

Page 3: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Microelectronic design

Southampton Seminar 3

Analog

IC

Digital IC

Antenna

RF IC

MEMS

Design variables: W, L of each transistor, Cc

For the goal of (such as):

They are optimisation problems

Page 4: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Computational Intelligence (CI)-based EDA

Traditional Design Process and Challenges

Southampton Seminar 4

Idea of CI-based EDA approaches:

TRANSFORM difficulties on “analysis, intuition and inference” TO difficulties on solving mathematical optimisation problems

Page 5: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Why CI is needed?

Southampton Seminar 5

• Properties of EDA problems: • Multimodal and global optimisation is necessary

• They are simulation-based optimisation, while analytical equations are often unavailable

• The simulation may cost a long time

• CI-based EDA approaches aims at obtaining highly optimised designs (better than manual design) automatically in a practical time by: • Evolutionary computation (EC)

• Machine learning (ML)

Page 6: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Outline Electronic design and optimisation

Evolutionary algorithms in EDA: How it works and challenges Surrogate model assisted evolutionary algorithms (SAEA)

The SMAS framework, improvements and applications:

Medium-scale problem: automated design of complex antennas Constraint handling: automated design of mm-wave ICs Integer optimisation: NoC design optimisation Challenges and opportunities

Conclusions

Southampton Seminar 6

Page 7: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Evolutionary Computation (EC)

Southampton Seminar 7

• Evolutionary computation is a CI method for optimisation

• EC is based on natural selection, survival of the fittest (objective function) • EC has strengths on black-box and multimodal problems

• Different global optimization algorithms: GA, DE, PSO, IA, AC

Initialize population

Evaluation Fitnees

Select Survivors

Crossover

Mutation

Convergance?

Output Result

Yes

No

CompetitionRanking Based

SelectionRoulette wheelTournament

ReproductionOne point, Two point, Uniform, SBX, Linear, etcBinary, Uniform, Gaussian

Page 8: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

How EA Works for EDA Problems?

Simulators: IC: Cadence Virtuoso, Synopsys HSPICE, … Electromagnetic device / antenna: Momentum, CST, SONNET, … MEMS: CoventorWare, MEMS+, COSMOL, … Energy system: AEPS, Energy+, …

Southampton Seminar 8

Page 9: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Southampton Seminar 9

Example: Analog IC Sizing (1)

ARCHITECTURE/

TOPOLOGY SELECTION

CIRCUIT SIZING

LAYOUT GENERATION

VERIFICATION

DRC+EXT+LVS

RE

DE

SIG

N L

OO

P

VERIFICATION

SPECS

M1 M2 vinvip

M13

vvcn

M2CM1C

M3C M4C

vvcp

M3 M4

VSS

M6 M12

M8 M10

cln

VDD

cc

M5 M11

M7M9

clp

cc

Mbp

ibb

Mbn

vonvop

min . . 80

250 60 4

4......

area

s b DC gain dB

GBW MHz

phase margin

output swing V

power mW

• Optimise Ws, Ls, Cc, Ibb

• No initial design

Page 10: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Southampton Seminar 10

Example: Analog IC Sizing (2)

B. Liu, F. Fernández, G. Gielen, R. Lopez, E. Roca, "A Memetic Approach to the Automatic Design of High-Performance Analog Integrated Circuits", ACM Transactions on Design Automation of Electronic Systems, vol. 14, no. 3, pp. 1-24, 2009.

• Two-stage telescopic cascode amplifier sizing with tight constraints (high specifications)

Time: 20 minutes

Page 11: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

CI-based EDA : Investigation & Application

EA-based design automation has been investigated and applied Academic:

IEEE: TCAD, TCAS, TVLSI, MTT, TAP, … ACM: TODAES, … Elsevier: Integration journal, Microelectronics journal, … …

Industry:

Cadence Neocircuit: Analog circuit sizing MunEDA WiCkeD: variation-aware analog circuit sizing SolidoDesign: various software for handling process variations …

Southampton Seminar 11

Page 12: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Main Challenges

Southampton Seminar 12

• Main challenges:

• Robust design

• System synthesis method: from block to system

• Long simulation time: impractical optimisation time • Analog IC with standard process parameters -> < 2 seconds /

simulation

• Yield estimation of analog IC -> a few minutes / simulation

• RF / mm-wave circuit -> 10-20 minutes / simulation

• Antenna / MEMS / NoC: various from 5 minutes to several hours / simulation

• Evolutionary algorithms often needs several hundreds to thousands of simulations to achieve highly optimised solutions.

Page 13: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Example: On-chip antenna design optimisation:

EM simulation for a candidate design: 20 minutes by ADS-Momentum

Convergence: 800 generations

Population size: 40

20min x 40 x 800 = 1.2 years!!!

Southampton Seminar 13

Example

B. Liu, H. Aliakbarian, Z.Ma, G. Vandenbosch, G. Gielen, "An Efficient Method for Antenna Design Optimization Based on Evolutionary Computation and Machine Learning Techniques", IEEE Transactions on Antennas & Propagation, vol. 62, no. 1, pp. 7-18, 2014.

Page 14: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Solutions to the efficiency problem

Southampton Seminar 14

Efficiency enhancement

Evolutionary algorithms

Speed up the simulation

Use fewer simulations

SAEA

Change the optimizer

Page 15: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Outline Electronic design and optimisation

Evolutionary algorithms in EDA: How it works and challenges Surrogate model assisted evolutionary algorithms (SAEA)

The SMAS framework, improvements and applications:

Medium-scale problem: automated design of complex antennas Constraint handling: automated design of mm-wave ICs Integer optimisation: NoC design optimisation Challenges and opportunities

Conclusions

Southampton Seminar 15

Page 16: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Introduction to SAEA

Surrogate model assisted evolutionary algorithm (SAEA): Using surrogate models to replace exact function evaluations

Southampton Seminar 16

Page 17: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Surrogate modelling, Prediction and Prescreening

Southampton Seminar 17

Page 18: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Ordinary GP modeling

Given training data:

Correlation function:

Maximize likelihood function:

Note: solve in closed form, estimate the hyper-parameters

Best linear unbiased prediction and predictive distribution

variants: simple/blind/…

Southampton Seminar 18

Page 19: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Prescreening

• With the uncertainty measurement, we can consider the quality of a candidate design in a global picture

• Even the predicted value is bad, promising solutions can still be discovered

Southampton Seminar 19

D. Jones, 2001. “A Taxonomy of Global Optimization Methods Based on Response Surfaces”, Journal of Global Optimization, pp. 345-383.

Page 20: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Prescreening

• Prescreening methods utilize

the prediction uncertainty.

• Possible promising areas but with less training data can be effectively explored.

•The “guessed” promising points

may not be correct.

• In medium scale (20-30d), prescreening ≈ prediction

Southampton Seminar 20

Page 21: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

A Key Contradiction

Model quality Solution quality

Efficiency *x evalN

How to perform effective global optimisation without high quality surrogate model(s)?

Where are optimal locations of the samples?

Southampton Seminar 21

Page 22: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Brute force, in-fill sampling, SAEA (1)

Brute force off-line surrogate modelling High quality model but too

time consuming

In-fill sampling techniques (EI, PI, LCB, etc) Design space understanding vs.

Optimisation? More than 15-20 dimensions? Do we need understanding of

the whole space or a single road is OK?

Southampton Seminar 22

Most available SAEAs

Page 23: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Brute force, in-fill sampling, SAEA (2)

SAEA EA search -> the next sampling point Dozens of variables: EDA problems

EA search pattern Model quality? Most available SAEAs 20-50

dimensional problems still use many exact function evaluations (5000-50000)

Southampton Seminar 23

Most available SAEAs

Page 24: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Outline Electronic design and optimisation

Evolutionary algorithms in EDA: How it works and challenges Surrogate model assisted evolutionary algorithms (SAEA)

The SMAS framework, improvements and applications:

Medium-scale problem: automated design of complex antennas Constraint handling: automated design of mm-wave ICs Integer optimisation: NoC design optimisation Challenges and opportunities

Conclusions

Southampton Seminar 24

Page 25: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Southampton Seminar

Surrogate Model-Aware Evolutionary Search Framework

A new unified method of surrogate modelling and evolutionary search

•Not using more samples, but control the locations of samples, for the objectives of:

• Good prediction accuracy • Effective search mechanism

B. Liu, Q. Zhang, G. Gielen, "A Gaussian Process Surrogate Model Assisted Evolutionary Algorithm for Medium Scale Expensive Black Box Optimization Problems", IEEE Transactions on Evolutionary Computation (In Press).

25

Page 26: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

SMAS vs. Present SAEA

SMAS Traditional SAEA

Southampton Seminar 26

Page 27: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Advantages of SMAS (1)

Property 1: Using the current best candidates as the parent population.

Advantage 1: Optimal solutions are not far away from each other, so a good surrogate model with much fewer samples can be constructed.

Southampton Seminar 27

Page 28: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Property 2: Only at most one candidate is different from two consecutive parent populations.

Advantage 2: The training data describing the current search region can be much denser.

Southampton Seminar 28

from child population

Advantages of SMAS (2)

Page 29: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Convergence property of SMAS

For a standard EA, some diversity are useful, while some are not.

SMAS emphasizes exploitation.

The exploration ability can be maintained by selecting appropriate EA operators and parameters.

Simulation: 20-dimensional Ackley function (assuming absolutely

accurate model)

Southampton Seminar 29

B. Liu, Q. Zhang, G. Gielen, “Behavioral Study of the Surrogate Model-aware Evolutionary Search Framework”, in Proceedings of IEEE World

Congress on Computational Intelligence, 2014 (In Press).

Page 30: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Optimisation Kernel: Differential Evolution

,1 ,2 ,ˆ ( ) [ , , , ]

i i i MX t x x x 1, 2, , NPi

,,

,

( 1), ( ( ) ) ( ),( 1)

( ), , 1, 2, , i j

i j

i j

v t if rand j CR or j randn iu t

x t otherwise j M

Southampton Seminar 30

Page 31: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Experimental Verifications (1)

Problems: 20-,30-dimensional Ellipsoid (F1-F3, opt:0), Rosenbrock (F4-F6, opt:0), Ackley(F7-F9, opt:0), Griewank(F10-F12, opt:0), 30-dimensional RS-Rastrigin(opt: -330), 30-dimensional RH composition function(opt:10). 1000 evaluations, 20 runs.

SMAS vs. GS-SOMA [Lim IEEE TEVC 2010]

Southampton Seminar

31

Page 32: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Experimental Verifications (2)

SMAS vs. SAGA-GLS [Zhou IEEE TSMC 2007]

SMAS vs. MAES [Emmerich IEEE TEVC 2006]

Southampton Seminar 32

Page 33: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Southampton Seminar 33

Automated Design of Complex Antennas (1)

• EAs have been widely used for antenna synthesis, but the long optimisation time largely limits their applications

Example: Four-element antenna array (3.4GHz – 3.8GHz, FR4 substrate)

Page 34: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Southampton Seminar 34

Automated Design of Complex Antennas (2)

• Maximise realised gain (each sampling point at least 13dB) with S11 below -10dB

Synthesis finished in only one night, with 71.05dB (5 sampling points total) realised gain

Comparable solutions, 3-7 times speed enhancement compared to DE, PSO.

Page 35: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

RF IC / mm-wave IC Design Difficulties for manual design

Passive component design is difficult, although circuit configurations are

simpler than analog IC Long simulation time: EM simulation, HB simulation Design experience intensive for the available step-by-step manual design

method

Difficulties for EA-based automated design

Accurate lumped models (computationally cheap) over a wide bandwidth for passive components are difficult to find at high-frequencies

Long simulation time: EM simulation, HB simulation Medium scale (15-40 variables) Complex and tight constraints

Southampton Seminar 35

Page 36: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Review of RF IC Design Automation

Existing method: equivalent circuit model for passive components, only

applicable to less than 10GHz RF design automation. [Allstot2003Springer] [Ramos2005TCAS ]

mm-wave frequency / general: No design automation method before our work [Liu IEEE TCAD 2012/2014]

Southampton Seminar 36

Page 37: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

The GASPAD Method Focuses on 60GHz and above RF IC

Three Main Goals of the Synthesiser Provide Highly Optimised Results General Enough to Any Circuit Configuration, Any Technology and Any

Frequency Efficient Enough for Practical Use

Update SMAS on constraint handling

Southampton Seminar 37

B. Liu, D. Zhao, G. Gielen, "GASPAD: A General and Efficient mm-wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 2, pp. 169-182, 2014.

Page 38: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Updating SMAS for Constraint Handling

New methods to model the

focused search region

New ranking methods

considering constraint

satisfaction

Separate modelling

objective and constraints

Prescreening + predicted

value

Southampton Seminar 38

Page 39: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

mm-wave IC Design Automation (1)

Synthesis of a 60GHz power amplifier in a 65nm CMOS technology (18 parameters)

Southampton Seminar 39

15 min / simulation

Page 40: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

mm-wave IC Design Automation (2)

Design parameters and their ranges

Southampton Seminar 40

Page 41: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Synthesised Result

Synthesised results: Power added efficiency (@P1dB): 9.85% 1dB compression point: 14.87dBm Power gain: 10.73dB K factor: 10.68 (stable)

About 2 days synthesis time. Much better performance than manual design [He 2010 RFIC]

The first method of general mm-wave IC design automation

Southampton Seminar 41

Page 42: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Expensive EDA Problems with Integer Variables

• Integer design variables lead to discontinuous landscapes, which is a challenge for:

– Surrogate modelling

– Evolutionary search

• NoC design optimisation

Southampton Seminar 42

Page 43: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Updating SMAS for Handling Integer Variables Parameter setting and search strategy selection rules:

Scaling factor Self-adaptive crossover rate DE/ctb/1 strategy

Iterative surrogate-assisted neighbourhood exploration method Aims:

Jump out of local optima Direct improvement Assist the SMAS flow

Methods: A self-adaptive perturbation method Local surrogate modelling Greedy search + Opposite DE search

Southampton Seminar 43

Page 44: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

NoC Design Parameter Optimisation

NoC performance

Design parameter opt

A single simulation costs 15 min to 1 hour for 15x15 to 30 x 30 NoC

Southampton Seminar 44

Architecture (Baseline, VCT, Hybrid, etc.)

Design parameters (Number of virtual channel, buffer depth of the router, etc.)

Application specific (a single loading environment) More general purpose (various loading environments)

Page 45: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Application Specific NoC optimisation

Southampton Seminar 45

Optimisation of a 15 x 15 NoC with hybrid architecture with the environment of PIR=0.018, PS1=2, PS2=12, BR=0 and hotspot nodes at 35, 57, 108, 155, 175 with 3%, 3%, 2%, 2%, 3% (random traffic)

1 1 2 2 5 5

1 1 2 2 5 5

2

minimize ( , , , , , ,..., , )

s.t. ( , , , , , ,..., , ) 0.16

area 850mm

c p

c p

D N S X Y X Y X Y

E N S X Y X Y X Y J

2

37 hours optimisation55.780.153

805.14

D cycles

E J

area mm

[1,10], [1,12], [1,8], , [1,15] (all integers)c pN S B X Y

Page 46: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

NoC Design for General Purpose Dozens of typical loading environments need to be

considered: Example: CMP with cache coherence protocols: 80 combinations of typical broadcast ratio, packet size and

packet injection rate

8 x 8 NoC optimisation for CMP with cache coherence protocols has been addressed, but 15 x 15 NoC, 30 x 30 NoC?

Southampton Seminar 46

Prohibitively expensive simulation

Page 47: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

A Few Challenges and Opportunities (1) Computationally prohibitively expensive

optimisation More than 1 hour / simulation Dozens of design variables Complex landscapes

EDA problems General purpose large dimensional NoC design optimisation Some problems in MEMS design optimisation 3D complex antenna design Some problems in optical devices design optimisation …

Southampton Seminar 47

Page 48: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

A Few Challenges and Opportunities (2) Computationally expensive multiobjective

optimisation

EDA problems: almost every problem

Southampton Seminar 48

B. Liu, Q. Zhang, F. Fernández, G. Gielen, "An Efficient Evolutionary Algorithm for Chance-constrained Bi-objective Stochastic Optimization and Its Application to Manufacturing Engineering", IEEE Transactions on Evolutionary Computation, vol. 17, no. 6, pp. 786-796, 2013.

Page 49: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

A Few Challenges and Opportunities (3) Possible starting points: A system utilising various electronic elements (IC,

MEMS, antenna, optical device, etc) Example: bio-medical system, energy harvesting system

Starting from computational expensive blocks Example: MEMS

From block synthesis to system synthesis

Co-design of hardware and algorithms

Southampton Seminar 49

Page 50: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Outline Electronic design and optimisation

Evolutionary algorithms in EDA: How it works and challenges Surrogate model assisted evolutionary algorithms (SAEA)

The SMAS framework, improvements and applications:

Medium-scale problem: automated design of complex antennas Constraint handling: automated design of mm-wave ICs Integer optimisation: NoC design optimisation Challenges and opportunities

Conclusions

Southampton Seminar 50

Page 51: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Conclusions (1) Handling expensiveness is unavoidable for future (intelligent) EDA

tools in many applications.

In most present SAEAs, the surrogate modelling and the evolutionary search are loosely cooperated.

New SAEA frameworks (unconstrained / constrained continuous / discrete optimisation) are presented, showing significant improvements in terms of efficiency while keeping the high solution quality. Some computationally intractible EDA problems can therefore be solved.

Southampton Seminar 51

Page 52: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Conclusions (2) CI methods based EDA tools

is possible to have a large impact for electronic design (IC, MEMS, antenna, optical devices, energy systems, etc) in the coming future.

Engineers with a new knowledge structure are needed.

Promote this emerging multidisciplinary research and education.

Southampton Seminar 52

M. Fakhfakh, E. Cuautle,

P. Siarry

Computational Intelligence in Electronic Design Springer, 2015

Page 53: Computational Intelligence Techniques for Electronic Design … · 2015-02-26 · Southampton Seminar 10 Example: Analog IC Sizing (2) B. Liu, F. Fernández, G. Gielen, R. Lopez,

Acknowledgments

Sincere thanks to Prof. Georges Gielen, Prof. Francisco V. Fernandez, Prof. Alex Yakovlev, Dr. Patrick Degenaar, Prof. Qingfu Zhang, Prof. Guy Vandenbosch, Prof. Tom Dhaene, Prof. Vic Grout, Dr. Hao-ming Chao, Mr. Dixian Zhao, Mr. Ammar Karkar Mr. Noel Deferm, Dr. Brecht Machiels, Miss Ying He, Mr. Mengyuan Wu, Mr. Bohan Yang, Miss Borong Su, Miss Wan-ting Lo for their valuable help!

Southampton Seminar 53

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Thank you

Thank you!

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