Compilers for Embedded Systems

Ram, Vasanth, and VJInstructor : Dr. Edwin Sha

Synthesis and Optimization of High-Performance Systems

Outline

• Compiler – the bottleneck

• Memory Optimization Techniques

• Re-targetability

Embedded System Development

• Software Development• Hardware Development• Integration

Requirements of Good Software

Complexity

Perf

Requirements of Good Hardware

Complexity

Perf

Compilers

Software

Hardware

Bad Compiler

Complexity

Perf

Software

Hardware

Good Compiler

Complexity

Perf

Next…

• Compiler – the bottleneck

• Memory Optimization Techniques

• Re-targetability

Optimization Techniques

• Platform independent• Architecture specific• Memory address generation

Platform Independent Techniques

• Loop transformation• Data reuse• Processor partitioning

Architecture Specific Techniques

• Memory modeling optimization• Register allocation – graph coloring• Custom memory architecture

Memory Address Generation

• General compilers – generated addresses are periodic

• Embedded systems – address sequence might not be periodic

Next…

• Compiler – the bottleneck

• Memory Optimization Techniques

• Re-targetability

Retargetable Code Generation• Code must be applicable to a

range of different targets

• Two Levels• Portability• Target Independence

Why Retargetability?

• Processor architectures differ from application to application

• Designing compilers quickly and economically.

Approaches

• Interpretive Code Generation

• Pattern Matched Code Generation

Interpretive Code Generation

• Generate code for virtual machine and expand it to real target

• Disadvantage• Design a lot of virtual machines!• Not fully portable

Pattern Matched Code Generation

• Pattern matching (tree) replaces interpretation.

• Disadvantage• Creating pattern tree structures is

hard• No instructions may match pattern

tree!

Conclusion

• Efficient compilers – hard job.• Assembly code – increased time to

market• Lot of research in the field of code

generation for embedded systems.