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Abstract

we developed a new technique to simultaneously compress

& encrypt multiple images using a DCT and Chaotic

keyThe proposed method exploits the DCT properties to

achieve the compression and the encryption simultaneously.

First, to realize the compression, 8-point DCT applied to

several images are done. To this end, the spectral planeshould be divided into several areas and each of them

corresponds to the spectrum of one image. On the otherhand, Encryption is achieved using the multiplexing, a

specific rotation functions, encryption keys. Finally, many

simulations have been conducted. Obtained results

corroborate the good performance of our approach. We

should also mention that the recording of the multiplexed

and encrypted spectra is optimized using an adapted

quantification technique to improve the overall compression

rate.Keywords-component; formatting; style; styling; insert (keywords)

I. INTRODUCTION (HEADING 1)

Images form the significant part of data, particularly in remotesensing, biomedical and video conferencing applications [1].The use of and dependence on information and computerscontinue to grow, so too does our need for efficient ways ofstoring and transmitting large amounts of data. For example,someone with a web page or online catalog that uses dozens or

perhaps hundreds of images will certainly need to use someform of image compression to store those images. This is

because the amount of space required to hold unadulteratedimages can be prohibitively large in terms of cost. Fortunately,there are several methods of image compression availabletoday [2]. However, the digital pictures require far morecomputer memory and transmission time than that needed for

plain text. For real time applications, in order to handle hugeamount of data, the image compression schemes are

needed.need to create these components, incorporating the

applicable criteria that follow. Image compression is a

process intended to yield a compact representation of animage, thereby reducing the image storage / transmission

requirements. Generally, data compression is of two types:

reversible compression (lossless) and non-reversible (lossy)

compression. Reversible compression results in a reduction

of redundant data, but the reduction is in such a way that

redundancy can be subsequently restored into the data. Non-

reversible compression results in the reduction of

information itself in which the lost information can never be

recovered. The non-reversible scheme provides more

compression than its reversible counterpart [3].

The security of digital images is another importantissue that has been receiving considerable attention in therecent past. Recently, owing to advances in communicationtechnology, there has been strong interest in digital signaltransmission, for instance, in the ISDN networks, the HDTVsystems, and the distributed multimedia systems. Because therehas been fully developed in communication transmission andreceiving equipment, illegal data access has become more easyand prevalent in wireless and general communication networks.Hence, data security has become a critical and imperative issue.In order to protect valuable data from undesirable readers,many encryption techniques [I]-[6] have been proposed.

This paper is organized as follows: the description of the

proposed simultaneous compression and encryption method

is presented in section II. Section III is dedicated to theoptimization of the DCT architecture. Implementation

results using FPGA are illustrated in the last section before

conclusion.

I. ALGORITHMICSPECIFICATIONS

We proposed a new technique, based on our methods

presented in [3] and [6], which can carry out compression

and simultaneous encryption using Discrete Cosine

Transform (DCT) and Chaotic key kased algorithmAccording to a binary sequence generated from a chaotic system,the gray level ofeach pixel is XORed or XNORed bit-by-bit to oneof the two predetermined keys. The desirable result of theencrypted image being completely disordered can be obtained.

Moreover, its VLSI architectureis designed and the architecture ofintegrating thecompression and encryption scheme is also

proposed. Finally, simulation results are given.

A. Compression by Discrete Cosine Transform (DCT)

The choice of the DCT is justified by the use of the DCT in

many standards such as JPEG [7], MPEG [8] and ITU-T

H261 [9]. Moreover, we need fewer DCT coefficients than

DFT coefficients to get a good approximation to a typical

signal [10]. In fact, by applying the DCT, the most of the

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signal information tends to be concentrated in a few low-

frequency components. Consequently, the higher frequencycoefficients are small in magnitude and can be ignored in

the compression process.The DCT works by separating

images into parts of differing frequencies.During a step

called quantization,where compression actually occurs,lessimportant frequencies are discarded,hence the use of the

term lossy.Then,only the most important frequencies that

remain are used to retrieve the image in the decompression

process using IDCT.

1) Encoding System

There are four steps in DCT technique to encode or

compress the image

Step1. The image is broken into N*N blocks of pixels. Here

N may be 4, 8, 16,etc.

Step2. Working from left to right, top to bottom, the DCT

is applied to each block.

Step3. Each blocks elements are compressed through

quantization means dividing by some specific value.Step4. The array of compressed blocks that constitute the

image is stored in a drastically reduced amount of space.So first the whole image is divided into small N*N

blocks then DCT is applied on these blocks. After that for

reducing the storage space DCT coefficients [5] are

quantized through dividing by some value or by

quantization matrix. So that large value is become small and

it need small size of space. This step is lossy step. So

selection of quantization value or quantization matrix[10] is

affect the entropy and compression ratio. If we take small

value for quantization then we get the better quality or lessMSE(Mean Square Error) but less compression ratio. Block

size value also affects quality and compression ratio. Simply

the higher the block size higher the compression ratio but

with loss of more information and quality.2) Decoding System

Decoding system is the exact reverse process of encoding.

There are four steps for getting the originalimage not exact

but identical to original from compressed image.Step1. Load compressed image from disk

Step2. Image is broken into N*N blocks of pixels.

Step3. Each block is de-quantized by applying reverse

process of quantization.

Step4. Now apply inverse DCT on each block. Andcombine these blocks into an image which is identical to the

original image.

In this decoding process, we have to keep Ns value same as

it used in encoding process. Then we do de-quantization process by multiplying with quantization value or

quantization matrix. As earlier said that this is lossytechnique so output image is not exact copy of original

image but it is same as original image. So this process

efficiency is measure by compression ratio. Compression

ratio[3] is defined by ratio of storage bits of original image

and storage bits of compressed image.

cr=

Where n1 is number of bits to store original image and n2 is

number of bits to store compressed image.

B.Encryption/Decryption Algorithm

Let fdenote an image of size MxNpixels and fix,y), 0 xM-1,

0 yS

N-1, be the gray level off

at position (x, y). Theproposed encryption scheme is as follows.

1) The Chaotic Key-Based Algorithm (CKBA)

Step 1 : Determine the two keys, keyland key2, and the twoparameters, MandN, and set l=0.

Step 2: Determine a 1-D chaotic system and its initial point

x(0).Generate the chaotic sequence x(O), x( l ) , x(2),. . . ,x(MNI8-1) from the chaotic system and then create b(O), b(l), b(2)

,..., b(2MN-1) fromx(O), x(l), x(2) ,..., x(MN?8-1) by thegenerating scheme that O.b( 16n+O)b( 16n+l) b(16n+I3)b(16n+14)b( 16n+l5) is the binary representation of x(n)forn =0, 1, 2 ,...., (MN/8-1)Step 3: For x = 0 to M- 1

For y = 0 to N - 1

Switch ( 2xb(l) + b(l+l) )case 3: f(x , y) =f(x, y ) XOR keyl

case 2: f(x,y)=f(x,y)XNORkeyl

case 1 : f(x,y)=flx,y)XORkey2

case 0: f ( x , y) =f(x, y) XNOR key2

l=1+2;End

End

Step 4: The resultf is obtained and stop the algorithm.

II. PROPOSEDVLSIARCHITECTURE

The DCT is the heart of the proposed compression

and method. Therefore, an optimization of the whole proposed method requires a DCT optimization. In this

section, we present the modified DCT architecture in order

to allow an acceptable compression ratio and a relatively

high image quality.In literature, many fast DCT algorithms

are reported. In [11], the authors show that the theoretical

lower limit of 8-point DCT algorithm is 11 multiplications.

Since the number of multiplications of Loefflers algorithm[5] reaches the theoretical limit, we use this algorithm as the

reference to this work.

In [12] one realization based on Loeffler algorithm is

shown. A low power design is obtained with this algorithm.

In [13] use the recursive DCT algorithm and their design

requires less area than conventional algorithms. The authors

of [13] use Distributed Arithmetic (DA) multipliers and

show that N-point DCT can be obtained by computing N

N/2-point inner products instead of computing N N-point

inner products. In [14], a new DA architecture called NEDA

is proposed, aimed at reducing the cost metrics of power and

area while maintaining high speed and accuracy in digitalsignal processing (DSP) applications. Mathematical analysis

proves that DA can implement inner product of vectors in

the form of twos complement numbers using only

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additions, followed by a small number of shifts at the final

stage. Comparative studies show that NEDA outperformswidely used approaches such as multiply/accumulate

(MAC) and DA in many aspects. In this paper, we will not

optimize the arithmetic operators but we present a new

algorithm which makes dependency between thecompression ratio and the material complexity.

For encryption standard,according to a chaotic

binary sequence, the gray level of each pixel is XORed or

XNORed bit-by-bit to one of the two predetermined keys.

The block diagram of CKBA is shown in Fig. 1. From Fig.

1, pixels are XORed or XNORed bit-by-bit to keyl or key2

according to the two bits in the sequence. By the

transformation on each pixel, the desirable result of theencrypted image being completely disorder can be obtained.

Many combinations of keyl and key2 can result in very

disorderly image. The basic criterion to select keyl and key2

is based on the idea of CKBA that the gray level of eachpixel is XORed or XNORed bit-by-bit to keyl or key2.From

section A, the overall computational complexity is dominated by

Step 3. The operation numbers for Switch- Case statement,multiplication with 2, addition, and XOR or XNOR operation areMxNx1, MxNx~M, XNXS, and MXNx1, respectively. It is

obvious that the computational complexity is low. Besides, thesecurity problem is analyzed.

For example, consider the case ofM=256 and N =256.The number of all the possibilities is . Since the chaotic

binary sequence is unpredictable, it is very difficult to decrypt anencrypted image correctly even by making an exhaustive search.Hence, CKBA is one of guaranteed high security. In Fig. 1, thepixel-based operation is used to simplify the data access from the

image frame buffers. Moreover, both the data encryption unit(DEU) and the data decryption unit (DDU) are using the samehardware architecture.We adopt the concept of parallel processingsuch that the data encryption and decryption of eight pixels can beperformed at a time with the bit-serial, pixel-parallel (BSPP) styleof implementation. This architecture consists of 16 shift registers,8 parallel-to-serial (P/S) converters, 8 serial-toparallel (S/P)converters and 8 processing elements (PEs).

By adopting the BSPP style of implementation, the critical pathwill be located in the DEU and DDU, since that generating onechaotic bit string value can be used to encrypt and decrypt eightdata pixels. Therefore, we can both shorten the critical path andachieve the high hardware utilization efficiency of the proposeddesign by exploiting the BSPP style of implementation.Processingelements consists oftwo data multiplexers, one XOR gate, and oneinverter gate. Chaoctic Binary Sequence Grenerator is composedof two multipliers, one subtractor, one DFF, and one data

multiplexer. The computation time (denoted as T,,,, )to generate a

chaotic bit string value is assumed to be the time for twomultiplications and one data multiplexing. While, the cycle time

for the computation in DEU or DDU (denoted as TDEu) is

assumed to be the time for one P/S operation, one XNORoperation, two data multiplexing operations, and one S/P operation.Since that generating one chaotic bit string value can be used toencrypt and decrypteight data pixels, the critical path would be

T,,, ifT,,,, is smaller than 8 x TCIEU. However, ifT,,,, is largerthan 8 x TDEU, we can adopt suitable pipeline techniques tofurther reduce the time such that the critical path can be reduced.To summarize, the proposed hardware architecture is one of low

hardware cost, high computing speed, and high hardwareutilization efficiency.

III. VALIDATION

A. MethodologyA fixed point Matlab Simulink model has been established

to validate the proposed method. This step is very important

to validate the the algorithm structure before the material

implementation. Concerning the description language, we

decide to use VHDL rather than DIME-C and Mitrion-C

which produce less efficient hardware design. In fact,

DIMEC and Mitrion-C are much easier to program than

VHDL, but visibility to hardware details allowing

optimizations is lost due to abstraction [16]. In addition, the

VHDL standard language gives the choice of implementingtarget devices (FPGA family, CPLD, ASIC) at the end of

the implementation flow. It means that the models reportedhere are synthesized and may be implemented on arbitrary

technologies [17]. Simulation results of the VHDL model

are reported in Fig. 5 and Fig. 6 and show that original

images are rebuilt correctly with a PSNR average between

four images about 28 dB.

B. FPGA implementation

The original DCT Loeffler architecture and the

proposed done in this article have been implemented in the

same kind of FPGA boards, that is, sparton 3. In order toillustrate the differences in hardware consumption, the

FPGA implementation results are presented in Table 1.From this comparison we can notice that the proposed DCT

architecture and CKBA reduces the area consumption

(slices and Look Up Tables, LUTs) at a rate higher than 50

%. Furthermore, the throughput, expressed in Millions of

Samples per second (MS/s), presents a light increase

compared to the Loeffler architecture. The throughput of

206 MS/s allows the processing of more than 30 frames per

second. Finally, it should be pointed out that the modified

DCT and the proposed compression and encryption method

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have the same throughput:the proposed method is for sure

fully pipelined.

IV. SIMULATIONRESULTS

The picture used for simulation is shown in Fig. 2. It is the

original Lena picture of size 260 260. Fig. 4 is the lossy

decompressed Lena picture with block size 10. Thecompression ratio obtained is 16:1. Fig. 5 is the encrypted

Lena using chaotic key. Fig. is the decompressed lena

image.The software portion of this scheme was developedand tested using MATLAB for low and high dimensional

images. Then it is implemented in FPGA using Xilinx.

V. CONCLUSION

In this paper, the novel chaotic key-based algorithm forimage encryptioddecryption has been proposed and its VLSIarchitecture has been designed. The novel algorithm possesses thefollowing features: 1) low computational complexity, 2) highsecurity, and 3) no distortion. An optimized DCT algorithm is

proposed to reduce real time application requirements. The

encryption mechanism will not destroy the originalarchitecture..The presented VLSI Architecture possesses thefollowing advantages: 1) high hardware utilization efficiency, 2)low hardware cost, and 3) high computing speed.

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