COMPARISON OF SWITCHED-CAPACITOR LADDER AND CCD TRANSVERSAL FILTERS

R. W. Brodersen and T. C. Choi

I t INTRODUCTION

Switched-capacitor ladder f i l t e r s and CCD tr a n s v e r s a l f i l t e r s have developed i n t o two competitive approaches f o r implementing high p e r f o r ­mance f i l t e r s which can be f u l l y i n t e g r a t e d using MOS-LSI technology [1,2] I n some respects the two techniques are s i m i l a r since they are both analog sampled data f i l t e r s which make use of charge storage on capa c i t o r s . How­ever, i n most other aspects, they are fundamentally very d i f f e r e n t since CCD t r a n s v e r s a l f i l t e r s use only t r a n s f e r f u n c t i o n zeros to shape the frequency response, whereas the switched capacitor ladders are r e c u r s i v e f i l t e r s which make use of both poles and zeros. For some a p p l i c a t i o n s a t r a n s v e r s a l , a l l zero f i l t e r must be used, such as when tr u e l i n e a r phase i s required or i n matched f i l t e r i n g . On the other hand, a very narrow bandpass f i l t e r can be r e a l i z e d using a simple p a i r of high Q poles, which i s much more e f f i c i e n t than using a CCD tr a n s v e r s a l f i l t e r which would r e q u i r e a l a r g e number of zeros and th e r e f o r e many CCD stages f o r a narrow passband response.

I t i s not the i n t e n t i o n of t h i s paper to explore the t r a d e o f f s between the use of poles and zeros to implement a given t r a n s f e r f u n c t i o n , but r a t h e r to i n v e s t i g a t e the peak performance to be expected f o r a f r e ­quency response which can be reasonably r e a l i z e d ( i n terms of s i l i c o n area) by e i t h e r approach. The f i l t e r response w i l l be a 3.1 KHz lowpass f i l t e r which i s s i m i l a r t o t h a t r e q u ired f o r a n t i - a l i a s i n g i n a PCM t e l e ­phone system. The switched-capacitor implementation to be i n v e s t i g a t e d w i l l be a 5 pole, 4 zero e l l i p t i c f i l t e r and the CCD f i l t e r w i l l use the s p l i t electrode approach w i t h 64 stages. Both f i l t e r s w i l l be designed t o have a passband response of + .032 dB w i t h a stop-band r e j e c t i o n of 32 dB. The performance c h a r a c t e r i s t i c s of thses two f i l t e r s w i l l be com­pared a f t e r a b r i e f discussion i n the next s e c t i o n of the p a r t i c u l a r high performance implementations which are to be considered.

I I . CCD TRANSVERSAL FILTERS

I n the l a s t few years researchers have developed new techniques to implement CCD f i l t e r s which are optimized f o r d i f f e r i n g performance requirements. I n almost a l l cases, however, the basic s t r u c t u r e i s a tr a n s v e r s a l f i l t e r . The expression which describes the operations of an N stage f i l t e r i s

N-l V .(n) = T\ h VJ (n-m) (1) out *• *-L m I n v ' v '

m=0

where V (n) and V (n-m) are the nth and (n-m)th time sample of the

Department of E l e c t r i c a l Engineering and Computer Sciences, E l e c t r o n i c s Research Laboratory, U n i v e r s i t y of C a l i f o r n i a , Berkeley, C a l i f o r n i a 94720.

-268.

output and input s i g n a l s , r e s p e c t i v e l y . By t a k i n g the d i s c r e t e F o u r i e r

t r a n s f o r m of t h i s e x p r e s s i o n the t r a n s f e r f u n c t i o n of the f i l t e r can be

found

N-l -jtonT

HM - Z V c (2)

n=0 where T i s the sampling p e r i o d . As can be seen from t h i s equation, the

frequency response has a p e r i o d i c i t y equal to the sample r a t e , which

r e q u i r e s t h a t the input s i g n a l be b andlimited ( a n t l - a l i a s e d ) to avoid

s p u r i o u s responses. The d e s i g n problem of determining an optimum s e t of

c o e f f i c i e n t s which provides the c l o s e s t approximation to a d e s i r e d f r e ­

quency response has b a s i c a l l y been s o l v e d . There a r e s e v e r a l computer

programs t h a t a r e a v a i l a b l e which can v e r y e f f i c i e n t l y perform t h i s

t a s k [ 3 ] .

An an example of the t r a d e o f f s i n v o l v e d i n the design of t r a n s v e r s a l

f i l t e r s , the d e s i g n of a simple low pass f i l t e r w i l l be d i s c u s s e d . I f

o\ and öo r e p r e s e n t the d e s i r e d magnitude f o r the passband r i p p l e and

stopband r e j e c t i o n and Af i s the frequency width of the t r a n s i t i o n

between the passband and stopband r e g i o n s , then N the minimum number of

weighting c o e f f i c i e n t s to a c h i e v e t h i s response i s given by [4]

-10 log^c^y-is ( 3 )

N " 14 Af/f c

T h e r e f o r e , i f a v e r y sharp t r a n s i t i o n band i s r e q u i r e d ( r e l a t i v e to the

c l o c k r a t e ) , the number of weighting c o e f f i c i e n t s can be v e r y l a r g e .

F o r t u n a t e l y , l a r g e numbers of tap weights a r e r e a d i l y a c h i e v a b l e because

of the d e n s i t y of the CCD s t r u c t u r e .

I t i s apparent from the above d i s c u s s i o n t h a t i n order to a c h i e v e

the s h a r p e s t p o s s i b l e t r a n s i t i o n band i t i s d e s i r a b l e to have the band-

edge as near as p o s s i b l e to the sampling frequency. T h i s , however,

I n c r e a s e s the sharpness of the b a n d l i m i t i n g p r e f l i t e r which i s r e q u i r e d

to avoid a l i a s i n g of the input s i g n a l , when i t i s sampled a t the input

to the CCD. A design t r a d e o f f must t h e r e f o r e be made between the l e n g t h

of the CCD f i l t e r and the complexity of the a n t i - a l i a s i n g p r e f l i t e r .

For the 3.1 KHz lowpass under c o n s i d e r a t i o n a c h o i c e of 64 s t a g e s i m p l i e s

a c l o c k r a t e on the order of 32 KHz ( u s i n g Eq. ( 3 ) ) .

There has been e x t e n s i v e work i n v a r i o u s techniques f o r implementing

a t r a n s v e r s a l f i l t e r u s i n g charge t r a n s f e r d e v i c e s . I n many r e s p e c t s

the h i g h e s t performance has been obtained from the s p l i t e l e c t r o d e

annroach shown i n F i g . 1. ( A d d i t i o n a l c l o c k i n g e l e c t r o d e s f o r t r a n s ­

f e r r i n g the lïgnal charge a r e not shown [ 2 , 4 , 5 ] . ) The b a s i c s t r u c t u r e

i s a CCD delay l i n e which has one of the e l e c t r o d e s i n each s t a g e s p l i t

i n t o two or t h r e e p a r t s [ 3 ] . As charge t r a n s f e r s under these s e n s i n g

g a t e s , which a r e attached to p o s i t i v e and n e g a t i v e sense l i n e s the

HisDlacement charge i s sensed by the charge i n t e g r a t i n g o p e r a t i o n a l

a m p U f ï e r r L n n e c t e d to each sense l i n e . The v a l u e of the w e i g h t i n g

c o e f f i c i e n t i s r e a l i z e d d i r e c t l y as the s i z e of the p o r t i o n of the sense

Tall which extends over the channel; except for a s m a l l segment which

i s a l ays l e f t on the other s i d e of the channel to i n s u r e t h a t any edge

e f f e c t s due to f r i n g i n g f i e l d s a t the s i d e s of the channel w i l l be

e f f e c t s due to r r i n g g i s performed i n the t h i r d o p e r a t i o n a l

X l S - 5£h ™ between the two s e . s e Xines which

269.

S + Posi t ive Sense Line

S~ Negat ive Sense Line h < 0 h > 0 h > 0 h = 0

smal l smal l large

F i g . 1. D o u b l e - s p l i t - e l e c t r o d e t r a n s v e r s a l f i l t e r .

i s r e q u i r e d t o o b t a i n p o s i t i v e and negative w e i g h t i n g c o e f f i c i e n t s . An important advantage of t h i s "double s p l i t " approach i s t h a t small weight­i n g c o e f f i c i e n t s can be r e a l i z e d w i t h o u t l i m i t a t i o n s of e a r l i e r t e c h ­niques [ 5 ] . The b u f f e r e l e c t r o d e i n the center of the double s p l i t gates, S B, keeps the t o t a l capacitances of each sense gate constant. Also shown i n t h i s f i g u r e i s a more conventional s i n g l e s p l i t e l e c t r o d e gate which implements a l a r g e p o s i t i v e c o e f f i c i e n t since the s i n g l e s p l i t technique i s more e f f i c i e n t i n s i l i c o n area.

I I I . SWITCHED CAPACITOR FILTERS

A p o s s i b l e approach to m o n o l i t h i c f i l t e r s would be to attempt to i n t e g r a t e i n MOS technology conventional RC a c t i v e c i r c u i t s . However, t h i s i s not pos s i b l e because of the nec e s s i t y of ac c u r a t e l y d e f i n i n g resistance-capacitance products, which r e q u i r e s t h a t the absolute value of the r e s i s t o r s and capac i t o r s be w e l l c o n t r o l l e d . T y p i c a l v a r i a t i o n s i n an MOS process y i e l d v a r i a t i o n s of these parameters on the order of + 20%. Also the area r e q u i r e d to implement r e s i s t o r s and capac i t o r s which y T e l d RC products t h a t are needed f o r audio frequencies are p r o h i b i t i v e l y l a r g e .

A c i r c u i t t h a t performs the f u n c t i o n of a r e s i s t o r which when used w i t h c a p a c i t o r s t h a t do not have these disadvantages i s shown i n F i g . 2 ( a ) . The o p e r a t i o n of t h i s " r e s i s t o r " i s as f o l l o w s : the switch i s i n i t i a l l y i n the l e f t - h a n d p o s i t i o n so t h a t the ca p a c i t o r C i s charged to the vo l t a g e V,. The switch i s then thrown to the r i g h t and the c a p a c i t o r i s discharged to the vol t a g e V 2. The amount of charge which flows i n t o (or from) V 2 i s thus Q = C(V 2-V 1). I f the switch i s thrown back and f o r t h every T c seconds, then the cu r r e n t f l o w , i s i n t o V 2 w i l l be

c ( v 2 - V l )

270.

F i g . 2 ( a ) . A switched-capacitor r e s i s t o r . F i g . 2 ( b ) . The MOS implementation.

Thus the s i z e of an equivalent r e s i s t o r which would perform the same func­t i o n as t h i s c i r c u i t i s R = Tc/C. The MOS r e a l i z a t i o n of the c i r c u i t of Fi g . 2(a) i s shown i n F i g . 2 ( b ) . The two MOSFET1s are operated as switches which are pulsed w i t h a two phase nonoverlapping clock (<J> and <J>) at a frequency f c . The most important advantage of the switched capaci­t o r r e s i s t o r s I s the high accuracy of RC time constants t h a t can be obtained w i t h t h e i r use. I f a c a p a c i t o r C± which i s switched at a c l o c k r a t e of f c i s connected to a c a p a c i t o r C 2 the r e s u l t a n t time constant of t h i s RC network T r c i s approximately

RC f C. c 1

For a given clock r a t e the value of T r c i s t h e r e f o r e determined by a

r a t i o of c a p a c i t o r values which makes i t i n s e n s i t i v e to most processing

v a r i a t i o n s . The problem of implementing a c t i v e f i l t e r s i n MOS technology i s

thus reduced to the question of what k i n d of a c t i v e f i l t e r should be used. The f i l t e r c o n f i g u r a t i o n chosen i s the analog computer s i m u l a t i o n of the equations which describe a passive doubly-terminated RLC ladder. These f i l t e r s are c a l l e d " l e a p f r o g " or " a c t i v e ladder" f i l t e r s i n the a c t i v e f i l t e r c i r c u i t l i t e r a t u r e and are c l o s e l y r e l a t e d to wave d i g i t a l f i l t e r s i n the d i g i t a l s i g n a l processing l i t e r a t u r e .

The basic b u i l d i n g b l o c k of these f i l t e r s i s a d i f f e r e n t i a l i n t e g r a ­t o r and summer which i s shown i n F i g . 3(a) t h a t i s implemented i n the conventional way w i t h r e s i s t o r s and c a p a c i t o r s . The equations which describe t h i s c i r c u i t are

271.

Fig. 3(a). An RC integrator/summer. Fig. 3(b). The switched-capacitor implementation.

C 1 /RC

VOUT(ll)) " - C~ V l + " j ^ W (6)

I J

Straightforward su b s t i t u t i o n of the resistors by the c i r c u i t i n Fig. 2 would y i e l d a switched capacitor c i r c u i t that i s sensitive to p a r a s i t i c s , so an alternate method of re a l i z i n g the resistors which also makes i t possible to invert the sign of the signal i s used and i s shown i n Fig. 3(b) [7 - 9 ] . The c i r c u i t i n t h i s f i g u r e i s described by the following ^-transform equation

C C /C - —

V0UT ( Z ) " - é V l + f^ (* VV O) I 1-z

Appropriate interconnection of these sampled data integrators following the RLC prototype yields the parasi t i c free f i f t h order switched capaci­tor ladder shown i n Fig. 4. The capacitor r a t i o s which are used to implement t h i s f i l t e r are obtained by transforming the L and C values which can be obtained from standard tables [10]. The capacitor r a t i o s for a 3.1 KHz cutoff with a sample rate of 128 KHz are as follows:

C 2/C 1 = 8.470 C2/C4 = 2.042

C 6/C 5 = 5.043 C10 / C7 = 3 , 5 4 6

C10 / C9 = 1 4 , 7 0 7 C10 / C8 = 1 0 , 4 4 5

C 1 2 / C U = 6.874 C 1 5/G 1 3 - 3.791

C15 / C14 = 5 , 3 3 8 C 2 / C 3 = 7 , 4 7 0

C- JCn£ = 5.338 15 16

272.

F i g . 4. Switched-capacitor implementation of a f i f t h order e l l i p t i c lowpass.

IV. PERFORMANCE CHARACTERISTICS

A. Response Accuracy

I n both the CCD and switched-capacitor approaches the p r e c i s i o n c o e f f i c i e n t s which determine the frequency response are obtained from r a t i o s of capacitance areas. I n the case of the CCD's the capacitance area i s determined by s p l i t s i n the sense electrodes as shown i n F i g . 1. Since the outputs of the CCD f i l t e r s are sensed d i f f e r e n t i a l l y , edge e f f e c t s associated w i t h the CCD channel sides can be cancelled out. Also the e f f e c t of p a r a s i t i c capacitances on the sensing l i n e s which would degrade accuracy i s minimized i n the c i r c u i t of F i g . 1 by keeping the sense electrodes a t v i r t u a l grounds.

I n switched-capacitor f i l t e r s the capa c i t o r s are not always kept a t a v i r t u a l ground and since the s i g n a l i s not sensed d i f f e r e n t i a l l y , s p e c i a l c o n s i d e r a t i o n must be given to insure high accuracy i n the response. However, i t i s p o s s i b l e by t a k i n g a p p r o p r i a t e care i n l a y o u t of the ca p a c i t o r s (e.g. constant perimeter to area r a t i o ) as w e l l as proper c i r c u i t c o n f i g u r a t i o n s such as shown i n Figs. 3 and 4 to o b t a i n f i l t e r responses which are independent of p a r a s i t i c capacitances and edge e f f e c t s . Therefore by t a k i n g proper precautions i n both approaches extremely h i g h accuracy capacitor r a t i o s (and t h e r e f o r e f i l t e r c o e f f i ­c i e n t s ) can be achieved. The l i m i t i n g accuracy f o r both techniques i s probably then due to p h o t o l i t h o g r a p h i c q u a n t i z a t i o n . This tends to be more damaging to the CCD f i l t e r s because the transverse f i l t e r w e i g h t i n g c o e f f i c i e n t s vary over a wide range (from .001 to .2 i n our example) and thus a f i x e d q u a n t i z a t i o n i n t e r v a l w i l l r e s u l t i n l a r g e percentage e r r o r s f o r the smallest c o e f f i c i e n t s . The switched-capacitor i n t e g r a t o r r a t i o s v a r y over a much reduced range ( i n our example from 2 to 15) and since each p a i r of ca p a c i t o r s can be independently optimized the r a t i o e r r o r s

273.

are f r a c t i o n a l l y approximately constant, i . e . , there i s a constant per­centage error for a l l the c o e f f i c i e n t s .

The e f f e c t of tap weight quantization errors on CCD transversal f i l t e r s can be determined by defining a fixed c o e f f i c i e n t error ^ where

h' == h + A (8) m m m x ?

in which i s the desired weighting c o e f f i c i e n t and h' i s the actual value including process l i m i t a t i o n s . From Eqs. (1) and (8) we obtain

VOUT ( n ) " X VlN ( n- m ) + £ VlN ( n- m ) <9> m=0 m=0

which can be interpreted as two p a r a l l e l transversal f i l t e r s . One has the ideal response while the other has the values of the errors, Am, as weighting c o e f f i c i e n t s . Since these errors are i n general random the frequency response of the error f i l t e r s i s r e l a t i v e l y f l a t with an ampli­tude proportional to an rms average of the c o e f f i c i e n t errors. Thus these random errors r e s u l t i n a f r a c t i o n of the input signal i n the output which i s u n f i l t e r e d . This signal sets a lower l i m i t on the stop band re j e c t i o n ( t y p i c a l l y about -50 dB) as well as add r i p p l e to the passband region.

The analysis of the effect of quantization error on the response of a switched-capacitor ladder i s much more complex since these f i l t e r s are based on RLC prototype c i r c u i t s which are designed for maximum power transfer between the source and load. For those points where maximum power transfer exists the RLC prototype has zero s e n s i t i v i t y to f i r s t order variations i n the f i l t e r element values. Since there i s a one to one correspondence between the capacitor r a t i o s i n the switched-capacitor ladder and the RLC parameters the response exhibits very low s e n s i t i v i t y to errors i n the capacitor r a t i o s .

In Fig. 5(a)-(d), the designed response and that with a 1% weighting c o e f f i c i e n t error for both f i l t e r s are shown. The CCD transversal f i l t e r I s quantized with a quantizing i n t e r v a l equal to 1% of the largest c o e f f i ­cient value whereas the switched capacitor ladder i s assumed to have a constant 1% error for a l l the c o e f f i c i e n t s . In both cases, the f i l t e r s have a designed passband r i p p l e of 0.064 dB and a stopband r e j e c t i o n of 32 dB, with the lowpass cutoff at 3.1 KHz. With a 1% weighting c o e f f i c i e n t error, the CCD f i l t e r shows a passband r i p p l e of about 0.14 dB and a stopband r e j e c t i o n of only 25 dB. For the case of the switched-capacitor f i l t e r , the passband r i p p l e becomes 0.09 dB and the stopband r e j e c t i o n i s v i r t u a l l y unchanged, i.e. 32 dB. I n addition, the CCD f i l t e r shows a widening of the t r a n s i t i o n region whereas the switched-capacitor f i l t e r has no such tendencies. Thus, the switched-capacitor ladder exhibits a much lower s e n s i t i v i t y to c o e f f i c i e n t errors than the CCD f i l t e r .

B. Noise

A c r i t i c a l parameter i n many f i l t e r applications i s the noise per­formance. Tlvare are a v a r i e t y of noise sources i n a CCD which include the input voltage to charge conversion (which yields an rms noise of 64 yv f o r a 1 pf input capacitance); the surface state trapping i n the CCD channel on the order of 80 uv for a 64 stage CCD [ 6 ] ) , and the output amplifier noise. The wideband output c i r c u i t noise i s found by m u l t i ­plying the equivalent input noise of the op amp sensing signal charge (which for MOS op amps i s t y p i c a l l y on the order of 50 uv) by the noise '

274.

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F i g . 5 ( a ) . O v e r a l l r e s p o n s e o f CCD f i l t e r .

F i g . 5 ( b ) . O v e r a l l r e s p o n s e o f s w i t c h e d - c a p a c i t o r f i l t e r .

F i g . 5 ( c ) . Passband res p o n s e o f CCD f i l t e r .

F i g . 5 ( d ) . Passband res p o n s e o f s w i t c h e d - c a p c c i t o r f i l t e r .

g a i n o f t h e c i r c u i t . The n o i s e g a i n i s t h e t o t a l c a p a c i t a n c e seen a t t h e

op amp i n p u t d i v i d e d by t h e f e e d b a c k c a p a c i t o r w h i c h y i e l d s a r a t i o on t h e

o r d e r o f 5 f o r a lowpass f i l t e r o f t h e t y p e i n F i g . 1. S i n c e t h e r e a r e

two op amps (one on each sense l i n e ) t h a t c o n t r i b u t e e q u a l l y t o t h e n o i s e

t h e t o t a l RMS n o i s e , v r m s = 5 x /2 x 50 uv = 350 uv. S i n c e t h i s n o i s e i s

e f f e c t i v e l y sampled by t h e r e s e t t i n g s w i t c h , t h e r e l a t i o n s h i p between

n o i s e s p e c t r a l d e n s i t y u - n ( f ) v o l t s / H z 1/2 and rms n o i s e i s g i v e n by

fp/2

rms = 2 v ^ ( f ) d f .

275.

I f i t i s assumed t h a t the s p e c t r a l d e n s i t y of the noise i s w h i t e ( i n d e ­pendent of frequency) then the r e l a t i o n s h i p between v and v I s

rms n 1 1 / 2

v ( f ) = ~- v n f rms

c

For the f i l t e r response of F i g . 5(a) the c l o c k r a t e i s 32 KHz which y i e l d s a s p e c t r a l d e n s i t y U n = 2 yv//Hz. I f only the rms noise i n the 3.1 KHz passband i s considered then the expected noise of the CCD f i l t e r i s

vrms = (3.1 x I O 3 ) 1 ' ' 2 2 uv = 111 uv. This value i s c o n s i s t e n t w i t h the data taken on the double s p l i t e l e c t r o d e f i l t e r described by Ibrahim et a l . [ 5 ] .

A switched-capacitor f i l t e r has two primary noise sources; the t h e r ­mal noise due to the switch r e s i s t a n c e as i t charges and discharges the switched c a p a c i t o r s ; and the o p e r a t i o n a l a m p l i f i e r s . By making the switched c a p a c i t o r s s u f f i c i e n t l y l a r g e the thermal noise from the switches can be s u f f i c i e n t l y b a n d - l i m i t e d so t h a t i t i s n e g l i g i b l e com­pared to the op amp noise. Since the op amps are i n s i d e the f i l t e r , the op amp noise i s f i l t e r e d by the f i l t e r i t s e l f , w i t h v a r i o u s t r a n s f e r f u n c t i o n s depending on the placement w i t h i n the c i r c u i t . I f we assume, under worse case c o n d i t i o n s , t h a t the t r a n s f e r f u n c t i o n to the output from each a m p l i f i e r i s u n i t y , then f o r the f i v e op amp f i l t e r of F i g . 4 the t o t a l wideband noise w i l l be /5 x 50 uv = 112 uv. The noise i n the / 9

3.1 KHz passband i f the sample r a t e i s 128 KHz w i l l be (3.1 KHz/128 KHz) x 112 pv = 17 uv which i s s i g n i f i c a n t l y lower than the CCD f i l t e r noise. Even though there i s d e f i n i t e l y a noise advantage w i t h the use of switched-c a p a c i t o r f i l t e r s i t i s not as l a r g e as t h i s example would i n d i c a t e , be­cause of the frequency dependence of the noise i n MOS op amps. I n the above d i s c u s s i o n i t was assumed the op amp noise was white when i n f a c t throughout the low frequency range (< 5 KHz) the noise power has a 1/f dependence. This r e s u l t s i n a noise increase i n the 0 - 3 . 1 KHz band by a f a c t o r of three to four or more depending on the surface s t a t e d e n s i t y (which depends on the device processing).

I n summary there are two reasons why switched-capacitor f i l t e r s have lower noise: since the sample r a t e s are higher the s p e c t r a l d e n s i t y of the sampled noise i s lower v/hich r e s u l t s i n lower noise i n the f i l t e r passband; and the noise gain of each a m p l i f i e r i s only u n i t y compared w i t h a value around 5 f o r the CCD f i l t e r ( f o r t h i s example).

C. Op Amp Requirements

The requirements of the o p e r a t i o n a l a m p l i f i e r s are reduced f o r the switched c a p a c i t o r f i l t e r s i n comparison to the requirements of the op amps needed as charge i n t e g r a t o r s i n the CCD f i l t e r output i n F i g . 1. I n F i g . 6(a) the CCD op amp output waveform i s shown. This waveform a l t e r ­nates between a reference l e v e l when the charge i s not under the sense gate and the output s i g n a l l e v e l when the charge i s present. Therefore the op amp must have the c a p a b i l i t y t o slew and be able to s e t t l e w i t h f u l l v o l t a g e range swings every clock c y c l e . I t i s p o s s i b l e to design op amps to do t h i s a t 32 KHz clock r a t e s but i t r e q u i r e s power as w e l l as c o m p l i c a t i n g the op amp design.

I n F i g . 6(b) i s shown the switched c a p a c i t o r output which i n d i c a t e s the f i r s t order hold nature of the o u t p u t . The op amp i s only r e q u i r e d to f o l l o w the maximum frequency s i g n a l s the f i l t e r passes which i s 3.1 KHz f o r our example. The op amp performance i s t h e r e f o r e reduced which makes, i t p o s s i b l e to design i t f o r lower power and reduced area. I n the near

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PROCESS DEVELOPMENT

The C L and CCD technologies must be combined so th a t the best char­a c t e r i s t i c s of both are maintained. Since n-channel CCDs provide the highest speed, the lowest dark c u r r e n t generation and highest t r a n s f e r e f f i c i e n c y when f a b r i c a t e d i n a low de f e c t s t a r t i n g m a t e r i a l , i t i s necessary t o begin w i t h a p-type s t a r t i n g m a t e r i a l . The C L process w i l l also be f a b r i c a t e d i n the p-type s u b s t r a t e and the p-channel devices are formed i n n - w e l l s , v/hich are Implanted w i t h phosphorus and d r i v e n - i n dur­in g a l o n g , high temperature c y c l e . Since the C 2L process does not have f i e l d oxide, a major m o d i f i c a t i o n must be made to provide the d i e l e c t r i c i s o l a t i o n f o r the CCD. An iso p l a n a r (recessed) f i e l d oxide s t r u c t u r e w i l l be used to provide t h i s i s o l a t i o n . This i s o p l a n a r oxide can provide CCDs w i t h e x c e l l e n t c h a r a c t e r i s t i c s and can also be used t o provide minimum gate-geometry NMOS FETs. The C2L/CCD process i s then based on a C2 L

technology using d i e l e c t r i c i s o l a t i o n ( i s o p l a n a r oxide) to separate the C 2L p o r t i o n s of the chip from the NMOS/CCD s e c t i o n s , see Fig. 1.

CHIP DESIGN

Fig . 2 shows the t e s t chip which has been designed t o evaluate the C2L/CCD process. The main array ( o u t l i n e d by the w h i t e band i n the f i g u r e ) i s a 128-stage analog/binary c o r r e l a t o r which includes a two-phase CCD clo c k d r i v e r and a b i n a r y program r e g i s t e r clock d r i v e r on the chip » > . The r e s t of the chip i s devoted to t e s t c i r c u i t s which are used t o charac­t e r i z e the C2L/CCD process. A l l of the l o g i c c i r c u i t s use 6 u design r u l e s and have been simulated t o 30 MHz. A block diagram of one stage of the c o r r e l a t o r i s shown i n Fig. 3. This shows the l o c a t i o n of the NMOS/CCD sections of the chip which are i s o l a t e d from the C2L p o r t i o n s o f the chip by the is o p l a n a r oxide as shown i n F i g . 1. The CCD i s a two-phase b u r i e d n-channel CCD w i t h two l e v e l s of p o l y s i l i c o n and i o n implanted t r a n s f e r regions under the second p o l y s i l i c o n gates. T r a n s i s t o r s T71 through T74 are NMOS devices and t r a n s i s t o r s T75 through T87 are n-channel or p-channel C 2L devices. T r a n s i s t o r s T75 t o T80 form a s e t / r e s e t l a t c h which can be i s o l a t e d from the code program r e g i s t e r by T81. This allows the program r e g i s t e r t o be loaded w h i l e c o r r e l a t i o n s are being performed w i t h the previous code which has been latched-up. Clocks <f>A and <f)B are generated on chip by the program r e g i s t e r c l o c k d r i v e r c i r c u i t shown i n Fig. 2. A l l clock phases r e q u i r e d f o r the CCD are generated i n the CCD clo c k d r i v e r c i r c u i t except the i n p u t strobe phase. The i n p u t strobe has not been generated on-chip since the best i n p u t technique has not been determined f o r high speed CCDs. Since there i s no conceptual problem i n the design of a given i n p u t c i r c u i t , the open-ended design on the present chip allows the optimum technique t o be determined and Implemented.

CIRCUIT SIMULATIONS

The c i r c u i t s have been simulated using a CAD program which uses the Frohmann-Bentchkowsky model as mo d i f i e d by J. E. Meyer. Since no previous data was a v a i l a b l e f o r the C 2L model parameters as used i n the i n t e g r a t e d C2L/CCD process, they were estimated from previous work on C 2L c i r c u i t designs. However, a f t e r the f i r s t run was made the thresholds f o r the n-channel devices had to be adj u s t e d , and the second run provided the a c t u a l model parameters which were then used to v e r i f y the o p e r a t i o n o f the C2L/CCD c i r c u i t s . Figure 4 shows the c u r r e n t v o l t a g e c h a r a c t e r i s t i c s o f

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several o f the FETs which were used i n the chip design. Fig. 4a and 4b show p-channel devices and Fig. 4c shows an n-channel device w i t h 6 y gate l e n g t h s . The devices shown i n F i g . 4a and 4c were the u n i t c e l l devices used i n both the CCD clock d r i v e r and the program r e g i s t e r d r i v e r c i r c u i t s . Although the 6 y gate l e n g t h devices were used I n the o r i g i n a l , Fig. 4d shows a 4 u gate l e n g t h p-channel device which was t e s t e d i n a l a t e r v e r s i o n of the clock d r i v e r c i r c u i t s and w i l l be discussed below. The parameters shown i n the f i g u r e s are M: m o b i l i t y , VT: t h r e s h o l d v o l t a g e , SL: slope of the cur r e n t i n the s a t u r a t i o n r e g i o n , C: m o b i l i t y f a l l o f f due t o e l e c t r i c f i e l d , and N: n-channel or P: p-channel devices. Fig. 5 compares the r e s u l t s of the d e f a u l t values w i t h those obtained using the a c t u a l C^L/CCD model parameters. The f i g u r e shows CAD simula­t i o n s of the CCD clock d r i v e r c i r c u i t ($i and $2)> t n e d e f a u l t s i m u l a t i o n f o r $2 i s shown by the dashed l i n e and the s i m u l a t i o n r e s u l t s obtained from the a c t u a l C2L/CCD model parameters i s shown by the s o l i d l i n e s .

POWER CONSIDERATIONS

One of the l i m i t i n g f a c t o r s i n an i n t e g r a t e d high speed CCD device i s the power generated by the p e r i p h e r a l c i r c u i t s i n d r i v i n g the gate capacitance presented by the CCD t r a n s f e r gates. At frequencies below about 100 MHz t h i s power i s r e a c t i v e power and can be estimated by CV^f. For the 128-stage CCD i n the analog/binary c o r r e l a t o r each phase of the CCD has about 40 pF. At 50 MHz the power i s around 200 raW w i t h a 10 v o l t peak to peak clock swing. I f the program r e g i s t e r i s i n c l u d e d , the t o t a l power at 50 MHz o f 100% e f f i c i e n t d r i v e r s w i l l be on the order of 750 mW. Although t h i s i s not excessive i t w i l l degrade the c h a r a c t e r i s t i c s of the CCD due t o the temperature r i s e i n the chip and f o r longer arrays i t w i l l be even worse. An acceptable a l t e r n a t i v e w i t h bigger arrays or a t higher speeds i s t o take the f i n a l d r i v e r stages o f f chip since most of the power i s generated i n these l a s t stages. This w i l l impose a d d i t i o n a l design problems of phase delays but these problems should be f a i r l y easy to overcome, and i t i s much simpler from the system standpoint t o add a t r a n s l a t e r / b u f f e r stage than i t i s t o design a l l the r e s t of the l o g i c . The goal i n t h i s development i s to be able to generate a l l the l o g i c on chip and as many of the p e r i p h e r a l s as p o s s i b l e .

RESULTS

The C 2L p e r i p h e r a l c i r c u i t s on the chip have operated to as hi g h as 50 MHz as shown i n Figure 6. This f i g u r e shows a photomicrograph o f the program r e g i s t e r clock c i r c u i t and output waveforms obtained from i t at 20 to 50 MHz. The 50 MHz waveform was obtained from a program r e g i s t e r which had 4 y gates and since the l i m i t of the pulse generator used i n t h i s t e s t was 50 MHz i t i s expected t h a t t h i s s t r u c t u r e w i l l operate a t higher r a t e s . The peak t o peak v o l t a g e has decreased i n t h i s photo because the c i r c u i t was o r i g i n a l l y designed w i t h 6 y gates t o operate a t 30 MHz, However, a u n i t c e l l approach was used i n i t s design so t h a t the p o l y s i l i c o n gate could be changed e a s i l y t o 5, 4, or 3 y gate s i z e s . I n a design f o r 4 y a t 50 MHz the f i n a l output stage would be increased i n s i z e t o provide the f u l l swing. The CCD clock d r i v e r s also have been operated a t the designed 30 MHz w i t h 6 y gates. A t e s t CCD which was i n c l u d e d on the c hip has been operated a t 20 MHz w i t h a t r a n s f e r i n e f f i c i e n c y of about 2 x l 0 ~ 5 . However, the f u l l analog/binary c o r r e l a t o r has not been tested but i t i s expected t h a t i t w i l l operate a t 30 MHz w i t h a charge t r a n s f e r i n e f f i c i e n c y on the order of l x l 0 " 4 .

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