compal_la-3071p_r1.0_schematics.pdf

AA

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number Rev

Date: Sheet o fLA-3071P 1.0Cover Sheet

1 59Friday, May 12, 2006

Compal Electronics, Inc.

COMPAL P/N :PCB NO :

COMPAL CONFIDENTIALMODEL NAME : HAU30

Crockett Schematics Document

uFCBGA Mobile Yonah-ULV

REV : 1.0 (DELL: A00)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

LA-3071P

PCB P/N: DA800004H1LBOM NO. 43140131L01

DA800004H1L

Intel Calistoga-GMS + ICH7M

2006-5-12

Part Number DescriptionDA800004H1L PCB 00B LA-3071P REV1 M/B

MB PCB

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PS_ID_IN

PWR_ID

PQ_G

-DCIN_JACK

PS_ID

+DCIN_JACK

+DC_IN_SS

+5V_ALW

+DOCK_DC_IN

+3.3V_ALW

+5V_ALW+5V_ALW

+PWR_SRC+3.3V_RTC_LDO_1

PS_ID_IN

PS_ID

PS_ID_DISABLE#

PS_ID_IN

Title

Size Document Number R ev

Date: Sheet o f

0.4

+DCIN

1 10Friday, May 12, 2006


LA-3071PAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS


NOTE: "THE POINT LOCATEDAT PS MODULE

THE POINT

+DC_IN Source

PS_ID Detector

+3.3VX Source

P

R

4

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

P

D

3

S

M

2

4

_

S

O

T

2

3

@

2 3

1

P

C

2

0

.

0

1

U

_

0

4

0

2

_

2

5

V

7

K

~

D

1

2

MIC5235-3.3BM5_SOT23-5~D

PU10

IN1

G

N

D

2

OUT 5

NC 4EN3

P

R

1

0

4

7

K

_

0

4

0

2

_

5

%

~

D

1

2

PC1422.2U_0603_6.3V6K~D

1

2

P

D

1

D

A

2

0

4

U

_

S

O

T

3

2

3

~

D

23

1

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4

0

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7

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~

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1

2

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1

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4

7

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8

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5

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7

k

1

2

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C

3

0

.

1

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6

0

3

_

2

5

V

7

K

~

D

1

2

PR6100_0402_5%~D@

1 2

G

D S

PQ1FDV301N_SOT23

2

1 3

P

R

7

1

5

K

_

0

4

0

2

_

1

%

~

D

1

2

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4

3

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5

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4

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~

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2

P

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1

2

.

2

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_

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0

2

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5

%

~

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1

2

P

R

8

2

4

0

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_

0

4

0

2

_

5

%

~

D

1

2

PL1BLM11B102S 0603~D

12

P

D

2

D

A

2

0

4

U

_

S

O

T

3

2

3

~

D

@

23

1

PR20_0402_5%~D@1 2

PL2FBM-L11-453215-900LMAT_1812~D

1 2

P

C

5

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

P

C

6

0

.

0

1

U

_

0

4

0

2

_

2

5

V

7

K

~

D

@

1

2

PL3FBM-L11-453215-900LMAT_1812~D

1 2

P

R

9

4

.

7

K

_

0

6

0

3

_

5

%

~

D

1

2

PQ3SI4825DY_SO8~D

3 65

78

2

4

1

PJDCIN

FOX_JPD113E-LB103-7F

SINGAL 5

DC+_1 1

DC+_2 2

DC-_2 4

GND27

GND49

GND38

GND16

DC-_1 3

CB

EPQ2PMBT3904_SOT23~D

2

3

1

PR333_0402_5%~D 1 2

P

R

5

1

0

K

_

0

4

0

2

_

1

%

~

D

1

2

AA

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title


Date: Sheet o fLA-3071P 1.0Block Diagram

2 59Friday, May 12, 2006


Clock Generator

uFCBGA CPU

INTEL

DMI

H_D#(0..63)H_A#(3..31)

Compal confidentialModel : HAU30

AMP & INT.Speaker

Pentium-M

Block Diagram

Azalia Codec

Power On/OffSW & LED

System Bus

INTEL

Memory BUS(DDR2)

FSB 400/533 MHz

+1.5V_RUN 100MHz

+1.8V_SUS 400/533MHz

48MHz

ATA100

MDC

998pin BGA

SLG84450VTR

STAC9200

Azalia I/F

Calistoga-GMS

ICH7-M

RJ11

HeadPhone &MIC Jack

PATA HDD+3.3V_HDD +VDDA

+5V_SUS +3.3V_RUN

+1.8V_SUS+1.5V_RUN

+1.05V_VCCP

+VCC_CORE+1.05V_VCCP

+3.3V_RUN

BANK 2, 3DDRII-DIMM X1

+0.9V_DDR_VTT+1.8V_SUS

Cable

+3.3V_SUS

479pin

DC/DC Interface

CPU ITP Port

+FAN1_VOUT Yonah-2M ULV

+3.3V_RUN+2.5V_RUN

+3.3V_RUN

VCORE (IMVP-6)

1.5V/1.05V

CHARGER

1.8V/0.9VBATT IN

DC IN

3V/5V/15V

GUARDIANEMC4000

Thermal

+3.3V_SUS

FAN

Power Sequence


652pin BGA

pg 7,8pg 18

pg 18pg 6pg 7

pg 10,11,12,13,14

pg 22,23,24,25

pg 48

pg 26 pg 27

pg 34

pg 49

pg 50

pg 45

pg 46

pg 47pg 42,43pg 44

pg 45

pg 28 pg 28

pg 15

+3.3V_ALWpg 41

Int.KBD &Stick

SMSC KBC

+3.3V_ALW+RTC_CELLMEC5004

pg 40

pg 41

SPI

LPC BUS+3.3V_RUN33MHz

SMSC SIO

+5V_RUN

+3.3V_ALW

Touch Pad

ECE5018pg 39

USB[1]

USB Ports X1+5V_SUS pg 33USB[6] REAR

HUB USB[1]

HUB USB[2]

pg 40pg 37FIR

DOCKINGBUFFER

pg 37

DOCKING PORT

pg 38 pg 31,32

PCI BUS

CardBus & 1394 & SDR5C843 CSP208

+3.3V_RUN 33MHzIDSEL:AD17(PIRQB,C,D#,GNT2#,REQ2#)

+3.3V_RUN+3.3V_SUS

HUB USB[2]USB[0]

Mini Card2+3.3V_RUN

WLANMini Card 1+3.3V_RUN

PCI Express BUS

+1.5V_RUN+1.5V_RUN pg 29

GIGA Enthernet

+3.3V_LAN

+3.3V_RUN/ +1.5V_RUN 100MHz

pg 36

BCM5752WWANpg 36

HUB USB[1]

USB[7]

Bluetooth+3.3V_RUN

HUB USB[4]

Stick

INT MIC+5V_SUS

+1.05V_VCCP

+3.3V_RUN+3.3V_SUS+1.5V_RUN

pg 34

SPI

+5V_RUN

+3.3V_RUN

pg 16,17

DDRII 512MB on Board+0.9V_DDR_VTT+1.8V_SUS

pg 19LVDSLVDS CONNRGB

pg 20DVODVI Bridge SI1362

CRT CONNpg 21

TV

DVI

PWR USB X1+5V_SUSUSB[5] REAR

SD card SLOT

1394 CONNCard Bus SLOT

IDSEL:AD24(PIRQA#,GNT0#,REQ0#)

pg 30

RJ45

LAN SWITCHPI3L500E

pg 30

Transformerpg 30

+3.3V_LAN

+2.5V_LOMpg 30

+3.3V_LAN+3.3V_LAN

SIM Cardpg 36+SIM_PWR

+DOCK_PWR_SRC+3.3V_RUN+2.5V_LOMpg 32+SD_VCC

pg 31pg 32

+3.3V_RUN+1.8V_RUN

+LCDVDD+GFX_PWR_SRC

pg 33DH_PORT_PWRSRC

USB Ports X1+5V_SUS pg 33

USB[4] REAR

ST M25P80

+2.5V_RUNpg 18

Smart Card+5V_RUN pg 35OZ77C6

HUB_USB[3]

SLOT

pg 51

pg 35pg 41Fingerprint

+3.3V_RUN

USB_BIO

+5V_RUN

+1.05V_VCCP

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Z4304

+PBATT

Z4305Z4306

Z4307

+VCHGR

+PBATT

+3.3V_ALW

+3.3V_ALW

PBAT_SMBDAT PBAT_PRES#

PBAT_ALARM#

PBAT_SMBCLK

Title


Date: Sheet o f

0.4

Battery Conn

2 10Friday, May 12, 2006





SUYIN_200028MR009G502ZLTOP view

9

8

7

6

5

4

3

2

1

Battery Connector

ESD Diodes

P

C

8

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

R

1

1

1

0

K

_

0

4

0

2

_

1

%

~

D

1

2

PJBAT1SUYIN200277MR009G508ZR~D

BATT1+ 9

SMB_CLK 7SMB_DAT 6

BATT_PRES# 5SYSPRES# 4

BATT2- 1GND10GND11

BATT2+ 8

BATT_VOLT 3BATT1- 2

PD5DA204U_SOT323~D@

23

1

PD4DA204U_SOT323~D@

23

1

PD6DA204U_SOT323~D@

23

1

PR15100_0402_5%~D

1 2

PD7DA204U_SOT323~D@

23

1

PR12100_0402_5%~D

1 2 PR14100_0402_5%~D

1 2

PL4FBM-L11-453215-900LMAT_1812~D

1 2

P

C

7

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

PR13100_0402_5%~D

1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet o fLA-3071P 1.0Index and Config.

3 59Friday, May 12, 2006


PIRQ

B,C,D

+1.05V_VCCP

PM TABLE

ON

ON

AD17

OFF

PCI DEVICE

TABLE

CARD BUS

IDSEL

S0

TABLE

2

PCI

ON

ON

S3

USB

ON

OFF

ON

+3.3V_SUS

OFF

+5V_SUS+5V_ALW

S1

S5 S4/AC don't exist

+1.8V_RUN

+VCC_CORE

REQ#/GNT#

+5V_RUN

ON

powerplane

+3.3V_RUN

S5 S4/AC

ON

ON

+3.3V_ALW

State

OFFOFF

OFF

+1.5V_RUN

0

4,6

7

USB PORT# DESTINATION

PWR USB

1 USB Hub (5018)

Docking

Blue tooth2

Tolerance0.1U_0402_6.3VXX

Ceramic Capacitors :

Temperature CharacteristicsRated VoltagePackage SizeValue

CHA

Capacitor Spec Guide:

1

SL

CODE

COG SJ9

B

+-3%

CODE

Symbol F

+40,-20%+-20%

4

G

+20,-10%

X

UK

5

B

Z

C

+-0.05PF

Y5V

Temperature Characteristics:

Y5P

CK

V

+-0.1PF

X5R

A

Z5U

BJ

+100,-0%

Y5U X7R

P

+-30%

C

SH8

H

CJ

+30,-10%

K

+-5%

7

Q

+80,-20%

6

+-0.5PF +-1PF

Z5V

+-10%

J

+-0.25PF

Tolerance:

+-2%

N

D

Z5P2

UJ

D E F G

H I J

30Symbol

X6SNPO

KX5S

M

ValuePackage SizeRated VoltageToleranceLow ESR Mark : 45 m ohm

10U_D2_10VX_R45

Tantalum or Polymer Capacitors :+0.9V_DDR_VTT

@XX : Depop componentNOTE1:

+1.8V_SUS



1

2

USB HUB DESTINATION

4

3

PC Card BayMini 1(WWAN)

Mini 2(WLAN)

N/A

+2.5V_RUN

REAR

SMART CARD

5

DOCKING AD24 0 A

USB HUB onOZ77C6LN

DESTINATION

DP_HUB Fingerprint

+15V_SUS

3 N/A

+3.3V_SRC

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TPS51120_VFB2

+5V_SUSP_L

TPS51120_VO1

TPS51120_VFB1

+3.3V_SRCP_L

+5V_SUSP

TPS51120_DRVL2

TPS51120_CS2

+

1

5

V

S

TPS51120_DRVL1

+15VS_L

TPS51120_LL2

TPS51120_LL1

TPS51120_VO2TPS51120_CS1

+3.3V_SRCP

TPS51120_DRVH1

TPS51120_DRVH2

T

P

S

5

1

1

2

0

_

S

K

I

P

#

+15VP

+3.3V_SRCP

+5V_SUSP

+15VP

+5V_SUS

+3.3V_SRC

+15V_SUS

+PWR_SRC

GNDA_DCDC1

+3.3V_RTC_LDO

+3.3V_SRCP

+3.3V_RTC_LDO

+3.3V_SRCP

+3.3V_SRCP

+VCC_TPS51120

+5V_ALW

+DC1_PWR_SRC

+VCC_TPS51120

GNDA_DCDC1

GNDA_DCDC1

GNDA_DCDC1

GNDA_DCDC1

+3.3V_ALW

+VCC_TPS51120

+5V_SUSP

GNDA_DCDC1

+VCC_TPS51120

GNDA_DCDC1

+VCC_TPS51120

+3.3V_RTC_LDO

+3.3V_ALW

+3.3V_RTC_LDO_1

THERM_STP#

SUS_ON

SUS_ONSUSPWROK_5V

AUX_EN

ALWON

RUN_ON

RUN_ENABLE

Title


Date: Sheet o f

0.4

+3.3V/+5V/+15V

3 10Friday, May 12, 2006





5 Volt +/- 5%Design Current:3.63AMaximum current: 5.191 AOCP: 6.35A

DC/DC +3V/ +5V/ +15V

Place these CAPsclose to FETs3.3 Volt +/- 5%

Design Current: 6.5 AMaximum current: 9.1A OCP: 10.95A

15 Volt Maximum Current: 10mA

3.3V OCP Fsw=440 KHZRds_on_MAX=15m; Itrip_MIN=8.5uA;L=2.7uHDelta_I=Vout/L * 1/Fsw * (1-Vout/Vin) =3.3/2.7u * 1/440K *(1-3.3/19)=2.3AIvalley_MIN= Itrip*Rtrip/Rds_on=8.5u*14.7K/15m=8.33AIvalley= Itrip*Rtrip/Rds_on=10u*14.7K/15m=9.8AIocp_MIN=8.33+2.3/2=9.48AIocp=9.8+2.3/2=10.95A

Place these CAPsclose to FETs

32 QFN 5X5

5V OCP Fsw=290 KHZRds_on_MAX=20m; Itrip_MIN=8.5uA;L=4.7uHDelta_I=Vout/L * 1/Fsw * (1-Vout/Vin) =5/4.7u * 1/290K *(1-5/19)=2.7AIvalley_MIN= Itrip*Rtrip/Rds_on=8.5u*10K/20m=4.25AIvalley= Itrip*Rtrip/Rds_on=10u*10K/20m=5AIocp_MIN=4.25+2.7/2=5.6AIocp=5+2.7/2=6.35A

P

C

3

0

1

0

U

_

0

8

0

5

_

6

.

3

V

5

K

~

D

1

2

P

R

4

1

2

0

0

K

_

0

4

0

2

_

1

%

~

D

@

1

2

P

C

9

2

.

2

U

_

1

2

0

6

_

2

5

V

7

M

~

D

1

2

P

R

1

5

7

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

PJP5

PAD-OPEN 4x4m

@1 2

P

Q

5

S

I

4

8

0

0

D

Y

-

T

1

_

S

O

8

~

D

3

6 578

2

4

1

P

Q

6

S

I

4

8

1

0

B

D

Y

_

S

O

8

~

D

3

65 7 8

2

4

1

PR1360_0402_5%~D@

12

PJP2

PAD-OPEN 4x4m

@1 2

P

C

3

3

4

.

7

U

_

1

2

0

6

_

1

0

V

7

K

~

D

1

2

P

R

2

4

0

_

0

4

0

2

_

5

%

~

D

@

1

2

PJP12

PAD-OPEN 4x4m

@1 2

P

R

1

5

9

2

.

2

M

_

0

4

0

2

_

5

%

~

D

1

2

P

C

1

1

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

P

C

1

7

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

PR2710K_0402_5%~D

12

P

C

1

4

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

P

D

1

8

B

A

T

5

4

C

W

_

S

O

T

3

2

3

~

D

32

1

P

R

2

2

0

_

0

4

0

2

_

5

%

~

D

@

1

2

PR160_0805_5%~D

1 2

P

C

1

3

4

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

@

1

2

P

C

2

6

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

PJP4

PAD-OPEN 4x4m

@1 2

PR34

0_0402_5%~D@ 1 2

G

DS

PQ9SI2301BDS-T1-E3 _SOT23~D

2

13P

Q

4

S

I

4

8

0

0

D

Y

-

T

1

_

S

O

8

~

D

3

65 7 8

2

4

1

P

C

1

5

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

C

1

6

2

.

2

U

_

1

2

0

6

_

2

5

V

7

M

~

D

1

2

P

R

3

8

0

_

0

4

0

2

_

5

%

~

D

1

2

G

DS

PQ8SI2301BDS-T1-E3 _SOT23~D@

2

13

P

R

1

3

8

0

_

0

8

0

5

_

5

%

~

D

@

1

2

G

D

S

PQ11RHU002N06_SOT323

2

1

3

P

C

1

2

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

P

R

2

9

0

_

0

4

0

2

_

5

%

~

D

1

2

P

R

4

0

4

.

7

K

_

0

4

0

2

_

5

%

~

D

1

2

PL72.7U_SIL1055R-2R7PF_9A

1 2

P

C

1

0

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

C

2

0

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

P

C

1

8

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

P

R

3

2

0

_

0

4

0

2

_

5

%

~

D

@

1

2

P

R

1

3

7

1

0

K

_

0

8

0

5

_

5

%

~

D

1

2

P

C

1

9

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

PL5FBM-L11-453215-900LMAT_1812~D

1 2

PR133

0_0603_5%~D

12

P

C

2

4

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

PR3010K_0402_5%~D

12

+

P

C

2

5

3

3

0

U

_

D

3

L

_

6

.

3

V

M

_

R

2

5

~

D

1

2

P

R

3

1

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

PR1620_0402_5%~D@

12

P

C

1

3

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

P

C

2

9

1

0

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

PC220.1U_0603_25V7K~D

12

P

Q

7

F

D

S

6

6

9

0

A

S

_

N

L

_

S

O

8

~

D

3

6 578

2

41

P

R

2

5

1

0

K

_

0

4

0

2

_

1

%

~

D

1

2

G

D

SPQ10RHU002N06_SOT323 @

2

1

3

PR1610_0805_5%~D

@

12

P

R

2

3

0

_

0

4

0

2

_

5

%

~

D

1

2

P

R

1

9

0

_

0

4

0

2

_

5

%

~

D

@

1

2

PC1180.1U_0603_25V7K~D

12

P

C

1

2

0

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

@

1

2

P

D

1

0

R

B

7

1

7

F

_

S

O

T

3

2

3

~

D

@

32

1

PD21BAT54CW_SOT323~D

@

3 2

1

S

GD

PQ24FDC655BN_NL_SSOT-6~D

3

6 2

4

5 1

P

R

1

3

5

0

_

0

4

0

2

_

5

%

~

D

1

2

PU7SN74AHC1G32DCKR_SSOP5~D

I02

I11O 4

P

5

G

3

P

R

2

8

0

_

0

4

0

2

_

5

%

~

D

@

1

2

P

C

3

2

0

.

0

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

PR200_0603_5%~D

1 2

P

R

2

1

0

_

0

4

0

2

_

5

%

~

D

@

1

2

P

D

9

E

C

1

1

F

S

2

_

S

O

D

1

0

6

~

D

2

1

P

C

3

1

1

0

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

@

1

2

PR39

0_0402_5%~D@1 2

P

R

2

6

1

4

.

7

K

_

0

4

0

2

_

1

%

~

D

1

2

P

D

8

M

M

B

Z

5

2

4

5

B

_

S

O

T

2

3

~

D

1

2 3

PJP3

PAD-OPEN 4x4m

@1 2

PR1600_0402_5%~D@

1

2

PR361K_0402_5%~D

12

PL64.7U_SDT-1204P-4R7D-122GP_20%

1

4

3

2

PR180_0603_5%~D

1 2

PR175.1_0603_5%~D

12

P

C

2

7

1

0

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

+

P

C

2

3

3

3

0

U

_

D

3

L

_

6

.

3

V

M

_

R

2

5

~

D

1

2

P

C

2

8

1

0

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

PR37

0_0402_5%~D @1 2

PC210.1U_0603_25V7K~D

1 2

PR35

0_0402_5%~D @1 2

PU1

TPS51120

VIN22

V5FILT20

EN59

VBST213

DRVH214

LL215

DRVL216

VO28

VFB26

EN212EN129

VREG319

S

K

I

P

S

E

L

3

2

PGOOD2 11PGOOD1 30

GND 5

PGND217

TONSEL 31VREF2 4

CS2 18CS1 23

VFB1 3

VO1 1

PGND1 24

DRVL1 25

LL1 26

DRVH1 27

VBST1 28

VREG5 21

EN310

P

A

D

3

3

COMP1 2COMP2 7

C

B

E

PQ252N2222_SOT23~D

2

31

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet o fLA-3071P 1.0Power Rail

4 59Friday, May 12, 2006


+5V_ALW

+5V_SUS

BATTERY

+PWR_SRC

+3.3V_SRC

+3.3V_ALW

+3.3V_RUN

ADAPTER

S

U

S

_

O

N

R

U

N

_

O

N

+5V_RUN VDDA

A

U

D

I

O

_

A

V

D

D

_

O

N

(

O

p

t

i

o

n

)

+15V_SUS

+2.5V_RUN

TPS51120

EMC4000

R

U

N

_

O

N

PL8

L47

793475

FDS4435 +GFX_PWR_SRCRUN_ON

SI4800



SI3456

E

N

A

B

_

3

V

L

A

N

+3.3V_LAN

ALWON

ALWON

SI4800

S

U

S

_

O

N

+VCC_CORE

R

U

N

P

W

R

O

K

+VCCP

SI3456

+1.5V_RUN

R

U

N

_

O

N

SC483

+1.8V_SUS

R

U

N

_

O

N

R

U

N

P

W

R

O

K

AD3207 SC480

+1.8V_RUN

R

U

N

P

W

R

O

K

S

U

S

P

W

R

O

K

_

5

V

+0.9V_DDR_VTT

AA

B

B

C

C

D

D

1 1

2 2

3 3

4 4

+DC2_PWR_SRC

+1.5V_RUN_P

+1.05V_VCCP_P

GNDA_DC2A

+1.05V_VCCP_P

+5V_SUS

GNDA_DC2A

+1.5V_RUN_P

GNDA_DC2B

GNDA_DC2A

GNDA_DC2B

+PWR_SRC

GNDA_DC2B

+3.3V_RUN

+1.05V_VCCP

+1.5V_RUN

+3.3V_RUN1.05V_RUN_PWRGD

1.5V_RUN_PWRGD

RUN_ON

Title


Date: Sheet o f

0.4

+1.5VRUNP /+VCCP_1P05VP

4 10Friday, May 12, 2006




DELL CONFIDENTIAL/PROPRIETARYRef Des SC483 TPS52483--------------------------------- PR56 30.0K 15.0K PR58 15.0K 15.0K PR55 16.5K 11.8K PR57 15.0K 29.4K

1.05V +/- 5%Thermal Design Current: 3.36AMaximum Current:4.8A MIN_OCP:5.2A

1.5V +/- 5%Thermal Design Current: 2.5AMaximum Current: 3.6AMIN_OCP: 3.7A

Use PR56 and PR58 forVoltage Margining.

BOM Structure Description----------------------------------------------- @ Do Not Populate 4@ Populate for Semtech - SC483 Only 5@ Populate for Ti - TPS51483 Only

Use PR55 and P57 forVoltage Margining.

Place these CAPsclose to FETs Place these CAPs

close to FETs

Create new P/N

PR5212.7K_0402_1% 1 2

PR500_0603_5%~D

12

FDS6994S_SO8~DPQ12

G22D2 8

S13D1 5

S21D2 7

G14D1 6

P

D

2

0

M

M

B

D

4

1

4

8

W

-

7

-

F

_

S

O

D

3

2

3

~

D

1

2

P

C

5

3

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

@

1

2

PL93.3uH_PCMC063T-3R3MN_6A_20%

12

+

P

C

4

9

3

3

0

U

_

D

2

E

_

2

.

5

V

M

_

R

9

1

2

P

C

4

5

1

U

_

0

6

0

3

_

6

.

3

V

6

M

1

2

P

R

4

6

1

0

_

0

4

0

2

_

5

%

1

2

PC480.1U_0603_25V7K~D

12

PR5815K_0402_1%

12

P

R

4

3

1

M

_

0

4

0

2

_

5

%

~

D

1

2

P

C

3

5

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

P

C

4

0

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

PC1410.1U_0603_25V7K~D

@

1 2

S

C

4

8

3

/

T

P

S

5

1

4

8

3

PU2

SC1485ITSTR-TPS51483_TSSOP28

PGND11

DL12

VDDP13

ILIM14

LX15

DH16

BST17

EN/PSV2 8

TON2 9

VOUT2 10

VCCA2 11

FBK2 12

PGOOD2 13

AGND2 14

PGND2 15

DL2 16

VDDP2 17

ILIM2 18

LX2 19

DH2 20

BST2 21

EN/PSV122

TON123

VOUT124

VCCA125

FBK126

PGOOD127

AGND128

PR518.45K_0402_1% 1 2

P

R

4

4

7

5

0

K

_

0

4

0

2

_

1

%

~

D

1

2

PL8FBM-L11-453215-900LMAT_1812~D

1 2

PC470.1U_0603_25V7K~D

12P

C

3

7

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

R

6

0

1

K

_

0

4

0

2

_

1

%

~

D

1

2

PR5310K_0402_1%~D 5@ 1 2

PR621K_0402_1%~D

1 2

PJP7

PAD-OPEN 4x4m

@1 2

FDS6994S_SO8~DPQ13

G2 2D28

S1 3D15

S2 1D27

G1 4D16

P

C

4

4

1

U

_

0

6

0

3

_

6

.

3

V

6

M

1

2

P

R

5

7

1

5

K

_

0

4

0

2

_

1

%

~

D

1

2

P

C

4

3

1

0

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

C

5

0

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

@

1

2

PR48499K_0402_1%5@

1 2

PJP6

PAD-OPEN 4x4m

@1 2

P

C

3

6

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

P

C

5

4

8

2

P

_

0

4

0

2

_

5

0

V

8

J

1

2

P

R

5

6

3

0

K

_

0

4

0

2

_

1

%

1

2

PR490_0603_5%~D

12

P

R

1

4

0

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

+

P

C

5

1

3

3

0

U

_

D

2

E

_

2

.

5

V

M

_

R

9

1

2

P

C

5

5

1

8

P

_

0

4

0

2

_

5

0

V

8

J

1

2

PR1390_0402_5%~D@

1 2

PR549.09K_0603_1%~D5@ 1 2

P

C

3

8

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

R

6

1

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

P

C

4

1

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

P

R

5

5

1

6

.

5

K

_

0

4

0

2

_

1

%

1

2

PD17BAT54A-7-F_SOT23~L

32

1

P

C

4

6

1

0

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

PJP8

PAD-OPEN 4x4m

@1 2

P

R

4

5

1

0

_

0

4

0

2

_

5

%

1

2

PR63

0_0603_5%~D

12

P

C

3

9

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

PR64

0_0603_5%~D

12

PR47453K_0402_1%~D5@

12

P

C

4

2

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

P

C

3

4

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2


12

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet o fLA-3071P 1.0SMBUS TOPOLOGY

5 59Friday, May 12, 2006


CLK GEN.

Macallan IV

ICH7-M

DAT_SMB +3.3V_ALW

CLK_SMB

GUARDIAN

ICH_SMBDATA

+3.3V_SUSICH_SMBCLK

SIO

PBAT_SMBCLK

PBAT_SMBDAT +3.3V_ALWBATTERYCONN

CHARGER


DIMM1

DDR II 512M ON Board


+3.3V_SUS

2N7002

2N7002

+3.3V_RUN

2.2K 2.2K 2.2K 2.2K

CLK_SCLK

CLK_SDATA

10K

SMBUS Address [A0]

SMBUS Address [A2]

195

197

B22

C22

17

16

5

6

7

8

SMBUS Address [D2]

SMBUS Address [2F]

+3.3V_ALW

8.2K8.2K

100

100

SMBUS Address [16]

SMBUS Address [12]

3

4

910

8

7

WWAN

SMBUS Address [TBD]

3032

WLAN

3032

SMBUS Address [TBD]

SBAT_SMBDAT111

112+3.3V_ALW

+3.3V_ALW

SMBUS Address [58]5

6SBAT_SMBCLKInverter INV

8.2K 8.2K

10K 10K

SMBUS Address [C4, 72, 70, 48]DOCK_SMB_CLK

+5V_ALW10

+5V_ALW

DOCKING9 DOCK_SMB_DAT39

40

5752MLOM

C8C7

SMBUS Address [C8]

SMBUS Address [5A]Power USBDOG house

10K

+3.3V_ALW

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+PWR_SRC

+1.8V_SUSP

+0.9V_DDR_VTT+0.9V_DDR_VTTP

+DDR_PWR_SRC

+DDR_PWR_SRC

+5V_SUS

+1.8V_SUSP

+5V_SUS

+0.9V_DDR_VTTP

+1.8V_SUSP

+1.8V_SUSP

+1.8V_SUSP

+5V_SUS

GNDA_DDR

+1.8V_SUSP

GNDA_DDR

GNDA_DDR

GNDA_DDR

GNDA_DDR

GNDA_DDRGNDA_DDR

GNDA_DDR

+1.8V_SUS

GNDA_DDR

RUN_ON

SUSPWROK_5V

SUSPWROK_1P8V V_DDR_MCH_REF

Title


Date: Sheet o fLA-3071P 0.4

+1.8VSUSP/ +0.9V_DDR_VT

5 10Friday, May 12, 2006



TPS5111620 QFN 4 X 4

PAD

NOTE: Component Values Shown for SEMTECH SC480 ONLY. For Texas Instruments TPS51116, Please USE Reference BOM.

NOTE: For Test purposes only

.9 Volt +/- 5%Design Current:1.05AMaximum current:1.5A

1.8 Volt +/- 5%Design Current:3.5AMaximum current:4.9A MIN_OCP:5A


Create new P/N

P

C

7

0

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

P

C

7

1

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

PL11FBM-L11-453215-900LMAT_1812~D

1 2

P

C

7

3

0

.

1

U

_

0

4

0

2

_

1

0

V

7

K

~

D

1

2

P

C

6

5

1

0

U

_

0

8

0

5

_

6

.

3

V

5

K

~

D

@

1

2

PJP10PAD-OPEN 4x4m

@

1 2

PR74100_0402_5%~D 1 2

PR77

17.4K_0603_1%~D @1

2

P

R

7

0

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

PD13RB751V-40_SOD323~D

2 1

PR690_0402_5%~D1 2

P

C

1

3

2

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

@

1

2

P

C

5

9

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

P

C

5

7

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

PR750_0402_5%~D1 2

P

C

5

8

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

P

C

6

2

0

.

1

U

_

0

4

0

2

_

1

0

V

7

K

~

D

1

2

P

C

6

7

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

@

1

2

FDS6994S_SO8~DPQ14

G2 2D28

S1 3D15

S2 1D27

G1 4D16

P

R

7

3

0

_

0

4

0

2

_

5

%

~

D

@

1

2

PU3SC480ITSTR_MLPQ24~D

PGND21

VTTS2

VSSA3

TON4

REF5

VCCA6

N

C

7

V

T

T

E

N

1

0

F

B

9

L

X

2

0

D

L

1

9

PGND1 18

PGND1 17

ILIM 16

VDDP 15

VDDP 14

N

C

1

2

E

N

/

P

S

V

1

1

V

D

D

Q

S

8

PGD 13

V

T

T

I

N

2

3

V

T

T

2

4

B

S

T

2

2

D

H

2

1

PAD 25

+

P

C

6

0

2

2

0

U

_

D

2

_

4

V

M

~

D

1

2

P

C

6

3

1

0

U

_

0

8

0

5

_

6

.

3

V

5

K

~

D

1

2

PJP9

PAD-OPEN 4x4m

@1 2

P

R

6

6

1

2

.

4

K

_

0

4

0

2

_

1

%

~

D

1

2

PJP11

PAD-OPEN 43X79

@1 2

P

R

6

7

1

M

_

0

4

0

2

_

5

%

~

D

1

2

P

C

7

2

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

P

C

6

9

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

@

1

2

+

P

C

1

3

3

2

2

0

U

_

D

2

_

4

V

M

~

D

1

2

PR76

27.4K_0603_1%~D@

1

2

P

C

6

6

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

P

C

6

4

1

0

U

_

0

8

0

5

_

6

.

3

V

5

K

~

D

1

2


12

P

C

6

8

1

0

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

R

7

2

1

0

_

0

4

0

2

_

1

%

~

D

1

2

P

R

7

1

1

0

_

0

4

0

2

_

1

%

~

D

1

2

P

R

6

5

0

_

0

6

0

3

_

5

%

~

D

1

2

P

C

1

1

9

1

8

P

_

0

4

0

2

_

5

0

V

8

J

@

1

2

P

R

6

8

1

0

K

_

0

4

0

2

_

1

%

~

D

@

1

2

P

C

5

6

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_ITP#

CLK_CPU_ITP

CLK_CPU_ITP#

CPU_ITP

H_STP_CPU#

H_STP_PCI#

CLK_MCH_BCLK#MCH_BCLK#

CPU_BCLK

CLK_CPU_BCLK#CPU_BCLK#

CLK_CPU_BCLK

+CK_VDD_A

+CK_VDD_MAIN

CLK_XTAL_IN

FSA

CLK_CPU_BCLK#

CLK_CPU_BCLK

CLK_MCH_BCLK

CLK_MCH_BCLK#

CLK_CPU_ITP#

CLK_CPU_ITP

CLK_PCIE_LOM#

CLK_PCIE_LOM

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICH#

CLK_PCIE_ICH

ICH_SMBDATA

ICH_SMBCLK

CLK_SDATA

CLK_SCLK

FSC

CLK_ICH_48M FSA

CLK14M_REFCLK_ICH_14MCLK_SIO_14M

CLK_ENABLE#

CLKIREF

CLK_SDATA

CLK_SCLK

FCTSEL1

FCTSEL1

CLK_PCIE_MINI2#

CLK_PCIE_MINI2

CLK_MCH_BCLKMCH_BCLK

PCIE_MINI2

CLK_PCIE_MINI2#

CLK_PCIE_MINI2

PCIE_MINI2#

CLK_PCI_SIO

CLK_PCI_ICH PCI_ICH

CLK_SMCARD_48M

CLK_PCI_5004

PCIE_ICH

PCIE_ICH#

CLK_PCIE_ICH

CLK_PCIE_ICH#

PCIE_MINI1

PCIE_MINI1#

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

+CK_VDD_REF

+CK_VDD_48

+CK_VDD_48+CK_VDD_A +CK_VDD_REF

CLK_XTAL_OUT

MCH_DREFCLK# DOT96#

DOT96MCH_DREFCLK

DOT96_SSC

DOT96_SSC#

DREF_SSCLK#

DREF_SSCLK

MCH_DREFCLK#

MCH_DREFCLK

CLK_PCIE_LOMPCIE_LOM

CLK_PCIE_LOM#PCIE_LOM#

MCH_3GPLL CLK_MCH_3GPLL

CLK_MCH_3GPLL#MCH_3GPLL#

CLK_PCI_LOM PCI_LOM

CLK_PCI_PCCARD PCI_PCCARD

PCI_DOCKCLK_PCI_DOCK

CLK_SD_48M

+CK_VDD_MAIN

+CK_VDD_MAIN2

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

H_STP_CPU#

H_STP_PCI#

CLK_MCH_BCLK#

CLK_MCH_BCLK

CLK_CPU_BCLK#

CLK_CPU_BCLK

CLK_CPU_ITP

CLK_CPU_ITP#

CLK_ICH_14MCLK_SIO_14M

CLK_PCIE_MINI2

CLK_PCIE_MINI2#

CLK_PCI_SIO

CLK_PCI_ICH

CLK_SMCARD_48M

CLK_PCI_5004

CLK_ICH_48M

CLK_PCIE_ICH#

CLK_PCIE_ICH

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

MINI2CLK_REQ#

MINI1CLK_REQ#

MCH_DREFCLK

MCH_DREFCLK#

CPU_MCH_BSEL1CPU_MCH_BSEL2

CLK_PCIE_LOM

CLK_PCIE_LOM#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_3GPLLREQ# CLK_PCI_LOM

CLK_PCI_PCCARD

CLK_PCI_DOCK

LOM_CLKREQ#

CLK_SD_48M

ICH_SMBDATA CLK_SDATA

CPU_MCH_BSEL0

CLK_ENABLE#

DREF_SSCLK

DREF_SSCLK#

ICH_SMBCLK CLK_SCLK

Title


Date: Sheet o fLA-3071P 1.0Clock Generator

6 59Friday, May 12, 2006


Place crystal within500 mils of CK410

31

G S

2N7002

2

D

1

*

CLKSEL2 CLKSEL0CLKSEL1FSC FSB FSA CPU

MHzSRCMHz

PCIMHz

266133200166333100400

100100100100100100100

33.333.333.333.333.333.333.3

0 0 000

00

0

000

0

111 1

1111 1

11

CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

0

0

0

1

Place near each pinW>40 milPlace near CK410+



Reserve

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0

1

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

60ohm,500mA,0.1ohm

60ohm,500mA,0.1ohm

R19 49.9_0402_1%~D

1 2

R15 2.2_0603_5%~D

1 2R16 49.9_0402_1%~D

1 2

R34 39_0402_5%~D

1 2

R66 10K_0402_5%~D

1 2

R62 33_0402_5%~D

1 2

R41 15_0402_5%~D

1 2

X114.31818MHz_20P_1BX14318CC1A~D

1

2

C1527P_0402_50V8J~D

12

R30 0_0402_5%~D

1 2

R39 56_0402_5%~D

1 2

R29 33_0402_5%~D

1 2

R18 49.9_0402_1%~D

1 2

R6710K_0402_5%~D@

1

2

C

1

1

0

.

0

4

7

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2

R48 56_0402_5%~D

1 2

C80.1U_0402_16V4Z~D

1

2

R61 33_0402_5%~D

1 2

R561 8.2K_0402_5%~D@12

R51 475_0402_1%~D

1 2

R24 33_0402_5%~D

1 2

R1 49.9_0402_1%~D

12

R14 49.9_0402_1%~D 1 2

R43 33_0402_5%~D

1 2

R50 33_0402_5%~D

1 2

R21 49.9_0402_1%~D

1 2

C50.1U_0402_16V4Z~D

1

2

R605 39_0402_5%~D

12

R55 10K_0402_5%~D

1 2

R26 33_0402_5%~D

1 2

R44 33_0402_5%~D

1 2

C6430.1U_0402_16V4Z~D

1

2

R12 49.9_0402_1%~D

1 2

R49 33_0402_5%~D

1 2

R7110K_0402_5%~D

1

2

R54 33_0402_5%~D

1 2

R20 49.9_0402_1%~D

1 2

R63 10K_0402_5%~D

1 2

R38 56_0402_5%~D

1 2

C1627P_0402_50V8J~D

12

U1

SLG84450VTR_QFN72~D

VDDSRC1VDDSRC49

VDDSRC65

VDDPCI30VDDPCI36

VDD4840

VDDCPU12

VDDREF18

USB_48MHz/FSLA41

FSLB/TEST_MODE45

X219

X120

GNDPCI31

PCICLK232

REF0/FSLC/TEST_SEL23

SMBDAT17

SMBCLK16

ITP_EN/PCICLK_F037

IREF9

CPU_STOP# 24

CPUT1 11

CPUC1 10

CPUT_ITP/SRCT10 6

PCICLK333

PCICLK4/FCTSEL134

CPUC0 13

CPUT0 14

PCI_SRC_STOP# 25

GNDA 8

VDDA 7

GNDPCI35

CPUC_ITP/SRCC10 5

GNDREF21

GNDCPU15

GNDSRC4

GND4842

GNDSRC68

DOTT_96MHz/27MHz43

DOTC_96MHz/27MHz(SS)44

Vtt_PwrGd#/PD39

REF122SRCT7 66

SRCC7 67

SRCT8 70

SRCC8 69

SRCT9 3

SRCC9 2

SRCC1 51

LCD100/96/SRC0_T 47

SRCT2 52

SRCT4 58

SRCT1 50

CLKREQ4# 57

SRCC2 53

SRCC5 61

SRCC4 59

SRCT5 60

LCD100/96/SRC0_C 48

SRCC3 56

SRCT3 55

SRCT6 63

SRCC6 64

CLKREQ6# 62

CLKREQ8# 71

CLKREQ9# 72

CLKREQ1# 46

CLKREQ5# 29

CLKREQ3# 28

CLKREQ2# 26

CLKREQ7# 38

VDDSRC54

PCICLK127

THRM_PAD73

THRM_PAD76

THRM_PAD74THRM_PAD75

R56 8.2K_0402_5%~D

12

R11 49.9_0402_1%~D

1 2

R46 10K_0402_5%~D

1 2

R28 33_0402_5%~D

1 2

C30.1U_0402_16V4Z~D

1

2

R70 33_0402_5%~D 1 2

C110U_0805_10V4Z~D

1

2

R6910K_0402_5%~D

1

2

L2BLM18PG600SN1_0603~D

1 2

R68 33_0402_5%~D 1 2

R31 33_0402_5%~D

1 2

R22 49.9_0402_1%~D 1 2

R3 49.9_0402_1%~D

12

R32 39_0402_5%~D

12

R

4

2

.

2

K

_

0

4

0

2

_

5

%

~

D

1

2

C40.1U_0402_16V4Z~D

1

2

R45 33_0402_5%~D

1 2

C6

0.1U_0402_16V4Z~D

1

2

R25 1_0603_5%~D

1 2

R36 39_0402_5%~D

12

R37 56_0402_5%~D

1 2

R52.2K_0402_5%~D

1

2

R33 33_0402_5%~D

1 2

C

1

4

0

.

0

4

7

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2

R7 49.9_0402_1%~D

12

R17 49.9_0402_1%~D

1 2

C

1

0

4

.

7

U

_

0

6

0

3

_

6

.

3

V

6

M

~

D

1

2G

D S

Q22N7002W-7-F_SOT323~D

2

1 3

C90.1U_0402_16V4Z~D

1

2

R7210K_0402_5%~D@

1

2

G

D S

Q12N7002W-7-F_SOT323~D

2

1 3

R65 33_0402_5%~D

1 2

R40 15_0402_5%~D

1 2

R35 39_0402_5%~D

12

R27 2.2_0603_5%~D

1 2

R23 49.9_0402_1%~D 1 2

C20.1U_0402_16V4Z~D

1

2 R6 49.9_0402_1%~D

12

R13 49.9_0402_1%~D 1 2

R53 33_0402_5%~D

1 2

L1BLM18PG600SN1_0603~D

1 2

R42 33_0402_5%~D

1 2

R9 49.9_0402_1%~D

1 2

R10 49.9_0402_1%~D

1 2

C

1

2

4

.

7

U

_

0

6

0

3

_

6

.

3

V

6

M

~

D

1

2

R8 49.9_0402_1%~D

12

R52 10K_0402_5%~D

1 2

C710U_0805_10V4Z~D

1

2

R64 33_0402_5%~D

1 2

R47 10K_0402_5%~D

1 2

C

1

3

0

.

0

4

7

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2

R2 49.9_0402_1%~D

12

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_FERR#

H_ADSTB#0

H_D#52

H_D#20

H_REQ#2

H_D#10

H_D#5

H_D#49

H_D#3

H_REQ#0

H_D#39

H_D#57

H_D#29

H_IGNNE#

H_D#34

H_D#14

H_BNR#

H_DSTBP#0

H_D#51

H_D#22

H_DEFER#

H_INIT#

H_REQ#1

H_D#50

H_D#48

H_D#0

H_RS#0

H_DSTBN#1

H_D#58

H_D#28

ITP_BPM#2

H_BPRI#

H_ADS#

ITP_BPM#3

H_RS#1

H_DSTBP#1

H_D#46

H_D#41

H_D#12

H_IERR#H_HITM#

H_DSTBN#0

H_D#47

H_D#37

H_INTR

H_DSTBN#2

H_D#9

H_D#7

H_REQ#4

H_D#31

H_D#13

ITP_DBRESET#

H_DRDY#

H_A20M#

H_D#27

H_D#25

H_D#4

H_DSTBP#2

H_D#56

H_D#35

H_D#59

H_D#63

H_D#45

H_D#24

H_D#30

H_D#55

H_D#40

H_D#19

H_D#62

H_D#44

H_D#23

H_D#2

H_D#8

H_D#6

H_D#54

H_D#33

H_D#18

H_D#16

H_D#61

H_D#43

H_D#1

H_D#26

H_DSTBN#3

H_D#53

H_D#32

H_D#11

H_DSTBP#3

H_D#38

H_D#36

H_D#17

H_D#15

H_NMI

H_D#60

H_D#42

H_D#21

H_BR0#

H_LOCK#

H_DPSLP#

H_HIT#

H_ADSTB#1

H_THERMTRIP#

H_DBSY#

H_RS#2

H_RESET#

ITP_BPM#1

H_REQ#3

H_SMI#H_STPCLK#

ITP_TCK

ITP_TRST#

TEST1TEST2ITP_TMS

H_CPUSLP#

ITP_TDOITP_TDI

ITP_BPM#5

H_DPWR#ITP_BPM#4

CPU_PROCHOT#

H_THERMTRIP#

H_TRDY#

CLK_CPU_BCLKCLK_CPU_BCLK#

ITP_BPM#0

ITP_TDO

ITP_TDO

ITP_TDI

ITP_TRST#

ITP_TCK

ITP_DBRESET#

H_RESET#

H_RESET#

H_THERMDAH_THERMDC

TEST2

H_DPRSTP#

ITP_BPM#5

ITP_TMS

ITP_TCK

ITP_TCK

ITP_DBRESET#

ITP_BPM#0

CLK_CPU_ITP#CLK_CPU_ITP

ITP_TRST#ITP_TMSITP_TDI

ITP_BPM#5

ITP_BPM#4

ITP_BPM#2

ITP_BPM#3

ITP_BPM#1

CPU_PROCHOT#TEST1

H_A#26

H_A#14

H_A#24

H_A#16

H_A#11

H_A#18

H_A#3

H_A#8

H_A#27

H_A#30

H_A#20

H_A#12

H_A#28

H_A#22

H_A#7

H_A#13

H_A#17

H_A#6H_A#5

H_A#10

H_A#15

H_A#31

H_A#9

H_A#19

H_A#25

H_A#21

H_A#23

H_A#4

H_A#29

+1.05V_VCCP

+3.3V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_THERMTRIP#

H_THERMDA

H_THERMDC

H_ADS#

H_REQ#[0..4]

H_BPRI#H_BNR#

H_HITM#

H_BR0#

H_HIT#

H_D#[0..63]

H_DPSLP#

H_RESET#

H_DRDY#

H_ADSTB#0

H_DSTBP#[0..3]

H_ADSTB#1

H_DSTBN#[0..3]

H_DINV#0

H_DINV#2

H_DBSY#

H_DINV#1

H_IGNNE#

H_INTR H_NMI

H_DINV#3

H_INIT#

ITP_DBRESET#

H_A20M#

H_STPCLK# H_SMI#

H_CPUSLP#

H_DPWR#H_DPRSTP#

H_TRDY#

CLK_CPU_BCLKCLK_CPU_BCLK#

CLK_CPU_ITP#CLK_CPU_ITP

H_DEFER#

H_LOCK#

H_RS#[0..2]

CPU_PROCHOT#

H_PWRGOOD

H_FERR#

H_A#[3..31]

Title



Yonah-ULV in mFCPGA479

7 59Friday, May 12, 2006


H_THERMDA, H_THERMDC routing together.Trace width / Spacing = 10 / 10 mil



This shall place near CPU

For Yonah B0

C

1

7

0

.

1

U

_

0

4

0

2

_

1

6

V

4

Z

~

D

1

2

R579 1K_0402_5%~D@1 2

R84 51_0402_5%~D1 2

R78 150_0402_1%~D

1 2

J2

MOLEX_52435-2891_28P~D@

TDI1TMS2TRST#3NC14TCK5NC26TDO7BCLKN8BCLKP9GND010FBO11RESET#12BPM5#13

BPM4#15

BPM3#17

BPM2#19

BPM1#21

BPM0#23DBA#24DBR#25VTAP26VTT027VTT128

GND114

GND216

GND318

GND420

GND522

G

N

D

7

3

0

C182200P_0402_50V7K~D

@

1

2

R80 22.6_0402_1%~D

1 2R81 27.4_0402_1%~D

1 2

R8256_0402_5%~D

1 2

R76 39_0402_5%~D

1 2

R73 150_0402_1%~D

1 2

C

6

3

3

0

.

1

U

_

0

4

0

2

_

1

6

V

4

Z

~

D

1

2

R575 54.9_0402_1%~D@1 2

R468 75_0402_5%~D

1 2

ADDR GROUP

CONTROL

HOST CLK

MISC

DATA GROUP

THERMALDIODE

LEGACY CPU

YONAH-ULVU2A

Yonah-ULV_1.06G SC_UFCBGA479~D1@

A3#J4A4#L4A5#M3A6#K5A7#M1A8#N2A9#J1A10#N3A11#P5A12#P2A13#L1A14#P4A15#P1A16#R1A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5A23#U2A24#R4A25#T5A26#T3A27#W3A28#W5A29#Y4A30#W2A31#Y1

REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L5

ADSTB0#L2ADSTB1#V4

BCLK0A22BCLK1A21

ADS#H1BNR#E2BPRI#G5BR0#F1DEFER#H5DRDY#F21HIT#G6HITM#E4IERR#D20LOCK#H4RESET#B1

RS0#F3RS1#F4RS2#G3TRDY#G2

BPM0#AD4BPM1#AD3BPM2#AD1BPM3#AC4

DBR#C20DBSY#E1DPSLP#B5

DPWR#D24PRDY#AC2PREQ#AC1PROCHOT#D21

PWRGOODD6SLP#D7TCKAC5TDIAA6TDOAB3TEST1C26TEST2D25TMSAB5TRST#AB6

THERMDAA24THERMDCA25THERMTRIP#C7

D0# E22D1# F24D2# E26D3# H22D4# F23D5# G25D6# E25D7# E23D8# K24D9# G24

D10# J24D11# J23D12# H26D13# F26D14# K22D15# H25D16# N22D17# K25D18# P26D19# R23D20# L25D21# L22D22# L23D23# M23D24# P25D25# P22D26# P23D27# T24D28# R24D29# L26D30# T25D31# N24D32# AA23D33# AB24D34# V24D35# V26D36# W25D37# U23D38# U25D39# U22D40# AB25D41# W22D42# Y23D43# AA26D44# Y26D45# Y22D46# AC26D47# AA24D48# AC22D49# AC23D50# AB22D51# AA21D52# AB21D53# AC25D54# AD20D55# AE22D56# AF23D57# AD24D58# AE21D59# AD21D60# AE25D61# AF25D62# AF22D63# AF26

DINV0# J26DINV1# M26DINV2# V23DINV3# AC20

DSTBN0# H23DSTBN1# M24DSTBN2# W24DSTBN3# AD23DSTBP0# G22DSTBP1# N25DSTBP2# Y25DSTBP3# AE24

A20M# A6FERR# A5

IGNNE# C4INIT# B3

LINT0 C6LINT1 B4

STPCLK# D5SMI# A3

DPRSTP#E5

R74 51_0402_5%~D

1 2

R7722.6_0402_1%~D

1 2

R79 680_0402_5%~D

1 2

R83 56_0402_5%~D 1 2

R75 54.9_0402_1%~D 1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M

A

X

8

7

3

1

_

C

S

S

P

MAX8731_DHI

ACAV_IN

ACAV_IN

M

A

X

8

7

3

1

_

D

A

C

MAX8731_CSIN

GNDA_CHGR

MAX8731_CCI

MAX8731_CCS

MAX8731_CSIP

MAX8731_LDO

MAX8731_LDO

MAX8731_REF

MAX8731_ACOK

MAX8731_VCC

N657586

MAX8731_ACIN

MAX8731_LX

MAX8731_BSTB

M

A

X

8

7

3

1

_

C

S

S

N

MAX8731_CCV

MAX8731_REF

+VCHGR_L

MAX8731_IINP

MAX8731_IINP

GND

MAX8731_DLO

+CHRG_IN

+VCHGR

+DC_IN_SS

+VCHGR

GNDA_CHGR

+VCHGR

GNDA_CHGR

+PWR_SRC

GNDA_CHGR

+DC_IN_SS

GNDA_CHGR

GNDA_CHGR

+5V_ALW

+5V_ALW +3.3V_ALW

+5V_ALW

+5V_ALW

GNDA_CHGR

+5V_ALW

GNDA_CHGR

GNDA_CHGR

GNDA_CHGR

PBAT_SMBCLK

ACAV_IN

PBAT_SMBDAT

ADAPT_OC

ADAPT_TRIP_SELTitle


Date: Sheet o f

0.4

Charger

7 10Friday, May 12, 2006





Smart Charger


+DC_IN discharge path

Maximum Battery Charge current = 3.15Awhen system off, S3, S4.

Need double confirm

Need modify


Battery Type:4cell: Charging Voltage=17.325V;Charging Current =1.6A6cell: Charging Voltage=12.975V;Charging Current =3.15A9cell:Charging Voltage=12.975V;Charging Current =3.15A

ADAPTER(W)TRIP CURRENT (A) PR142 PR145 PR148 PR1546590130150

3.174.436.447.44

4.32M 301K 56.2K 27.4K NA976K 49.9K 13.3K 9.31K 38.3K

33.2K66.1K

15K10K

33.2K20K649K

976K 13.3K13K

Table1PR147

G

D

SP

Q

2

6

R

H

U

0

0

2

N

0

6

_

S

O

T

3

2

3

2

1

3

P

R

1

5

8

1

K

_

0

6

0

3

_

1

%

~

D

1

2

PR11910K_0402_1%~D

12

PC981U_0805_25V4Z~D

12P

C

1

1

6

0

.

0

1

U

_

0

4

0

2

_

2

5

V

7

K

~

D

1

2

PR1250_0603_5%~D

1 2

P

C

1

2

9

0

.

0

1

U

_

0

4

0

2

_

2

5

V

8

K

1

2

P

Q

2

3

S

I

4

8

1

0

B

D

Y

_

S

O

8

~

D

3

65 7 8

2

4

1

P

R

1

4

4

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

P

C

1

4

0

0

.

0

1

U

_

0

4

0

2

_

5

0

V

7

K

~

D

@

1

2

P

R

1

1

7

1

0

K

_

0

4

0

2

_

1

%

~

D

1

2

P

C

1

1

1

2

2

0

P

_

0

6

0

3

_

5

0

V

8

J

~

D

1

2

PR155100_0402_5%~D

1 2

P

C

1

0

5

0

.

1

U

_

0

6

0

3

_

2

5

V

7

K

~

D

1

2

PR1281_0603_5%~D

1 2

P

C

1

1

3

0

.

0

1

U

_

0

4

0

2

_

2

5

V

7

K

~

D

1

2

P

C

1

0

3

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

P

C

1

2

2

0

.

1

U

_

0

6

0

3

_

2

5

V

7

M

~

D

1

2

PC1040.01U_0402_25V7K~D

12

P

C

9

7

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

PR1424.32M_0402_1%1 2

PC991U_0603_10V6K~D

1 2

PR131

0_0603_5%~D

12

P

C

1

0

0

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

PU9ALM393DR_SO8~D

IN+3

IN-2O 1

P

8

G

4

PR12310K_0402_1%~D

1 2

PL15FBM-L11-453215-900LMAT_1812~D

1 2

P

C

1

1

4

1

U

_

0

6

0

3

_

1

0

V

6

K

~

D

1

2

PU6

MAX8731_TQFN28~D

DHI 24

CSIP 18

LX 23

FBSA 15

SDA9

IINP8

G

N

D

1

DCIN22

ACIN2

VDD11

SCL10

ACOK13

BATSEL14

BST 25

FBSB 16

CCS4

LDO 21

VCC 26

C

S

S

P

2

8

CSIN 17

PGND 19

DLO 20

CCV6

CCI5

C

S

S

N

2

7

REF3

DAC7

GND12

PR120100K_0402_1%~D

12

PL165.6U_HMU1356-5R6_8.8A_20%~D 2 1

P

R

1

2

7

3

3

_

0

6

0

3

_

1

%

~

D

1

2

P

C

1

0

8

0

.

1

U

_

0

8

0

5

_

5

0

V

7

M

~

D

1

2

P

C

1

1

5

0

.

1

U

_

0

4

0

2

_

1

0

V

7

K

~

D

1

2

P

R

1

4

9

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

P

C

1

1

0

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

PR1460_0402_5%1 2

P

C

1

3

0

1

0

0

P

_

0

4

0

2

_

5

0

V

8

J

1

2

P

R

1

3

0

4

.

7

K

_

0

4

0

2

_

5

%

~

D

1

2

P

R

1

2

1

3

6

5

K

_

0

4

0

2

_

1

%

~

D

1

2

G

D

S


2

1

3

1

S

S

3

5

5

_

S

O

D

3

2

3

~

D

P

D

1

9

2

1

P

R

1

4

5

3

0

1

K

_

0

4

0

2

_

1

%

~

D

1

2

P

C

1

1

2

0

.

0

1

U

_

0

4

0

2

_

2

5

V

7

K

~

D

1

2

P

Q

2

2

I

R

F

7

8

2

1

_

S

O

8

~

D

3

65 7 8

2

4

1

P

C

1

0

1

0

.

1

U

_

0

6

0

3

_

2

5

V

7

M

~

D

1

2

P

C

1

2

6

0

.

0

1

U

_

0

4

0

2

_

2

5

V

8

K

1

2

P

C

1

3

9

0

.

0

1

U

_

0

4

0

2

_

5

0

V

7

K

~

D

@

1

2

P

C

1

1

7

0

.

1

U

_

0

4

0

2

_

1

0

V

7

K

~

D

1

2

P

C

1

0

2

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

PC1071U_0603_10V6K~D

1 2

PR1160.01_2512_1%~D

4

2

1

3

PC1060.1U_0402_10V7K~D

12

P

R

1

1

8

4

7

0

K

_

0

4

0

2

_

5

%

~

D

1

2

G

D

S


2

1

3

P

D

1

5

R

B

7

5

1

V

-

4

0

_

S

O

D

3

2

3

~

D

2

1

PR12449.9K_0402_1%~D

12

PU9BLM393DR_SO8~D

IN+5

IN-6O 7

P

8

G

4

P

R

1

4

7

5

6

.

2

K

_

0

4

0

2

_

1

%

1

2

PQ18SI4835BDY_SO8~D

3 65

78

2

4

1

PR1260_0402_5%~D

1 2

P

C

1

0

9

1

0

U

_

1

2

0

6

_

2

5

V

6

M

~

D

1

2

P

C

1

2

1

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

R

1

4

3

1

0

0

K

_

0

4

0

2

_

1

%

~

D

1

2

P

R

1

3

2

1

0

K

_

0

4

0

2

_

1

%

~

D

1

2

P

C

1

3

5

0

.

0

1

U

_

0

6

0

3

_

2

5

V

7

M

~

D

@

1

2

P

C

1

2

8

1

0

0

P

_

0

4

0

2

_

5

0

V

8

J

1

2

PR12215.8K_0402_1%~D

12

P

C

1

3

8

3

3

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

P

C

1

2

5

1

0

P

_

0

4

0

2

_

5

0

V

8

J

~

D

1

2

PR1290.01_2512_1%~D

4

2

1

3

P

R

1

4

8

2

7

.

4

K

_

0

4

0

2

_

1

%

1

2

P

C

1

2

7

1

0

0

P

_

0

4

0

2

_

5

0

V

8

J

1

2

P

C

1

3

1

0

.

0

1

U

_

0

4

0

2

_

2

5

V

8

K

1

2

P

R

1

5

4

1

5

4

K

_

0

4

0

2

_

1

%

@

1

2

PQ19SI4835BDY_SO8~D

365

78

2

4

1

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSSSENSE

VCCSENSE

VSSSENSE

COMP0

VID3

VID6VID5

VID2

VID4

VID1

VCCSENSE

COMP1

H_PSI#

COMP2

VID0

COMP3

+1.05V_VCCP

+VCC_CORE

+1.05V_VCCP

V_CPU_GTLREF

V_CPU_GTLREF

+1.5V_RUN

+VCC_CORE

+VCC_CORE

H_PSI#

VID0VID1VID2VID3VID4VID5VID6

VCCSENSEVSSSENSE

CPU_MCH_BSEL0CPU_MCH_BSEL1CPU_MCH_BSEL2

Title



Yonah-ULV in mFCBGA479

8 59Friday, May 12, 2006


Resistor placed within0.5" of CPU pin.Traceshould be at least 25mils away from anyother toggling signal.

R_B

R_A

Layout close CPU PIN AD26



0.5 inch (max)

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

0 0

0 1

CPU_BSEL0

1

1

Length match within 25 mils

Layout close CPUVCCSENSE/VSSSENSEtrace width 18mil,space 7mil, forother signal 15mil

Close to U2.B26

POWER, GROUND

YONAH-ULV

U2C


VCCAE18VCCAE17VCCAB15VCCAA15VCCAD15VCCAC15VCCAF15VCCAE15VCCAB14VCCAA13VCCAD14VCCAC13VCCAF14VCCAE13VCCAB12VCCAA12VCCAD12VCCAC12VCCAF12VCCAE12VCCAB10VCCAB9VCCAA10VCCAA9VCCAD10VCCAD9VCCAC10VCCAC9VCCAF10VCCAF9VCCAE10VCCAE9VCCAB7VCCAA7VCCAD7VCCAC7VCCB20VCCA20VCCF20VCCE20VCCB18VCCB17VCCA18VCCA17VCCD18VCCD17VCCC18VCCC17VCCF18VCCF17VCCE18VCCE17VCCB15VCCA15VCCD15VCCC15VCCF15VCCE15

VSS K1VSS J2VSS M2VSS N1VSS T1VSS R2VSS V2VSS W1VSS A26VSS D26VSS C25VSS F25VSS B24VSS A23VSS D23VSS E24VSS B21VSS C22VSS F22VSS E21VSS B19VSS A19VSS D19VSS C19VSS F19VSS E19VSS B16VSS A16VSS D16VSS C16VSS F16VSS E16VSS B13VSS A14VSS D13VSS C14VSS F13VSS E14VSS B11VSS A11VSS D11VSS C11VSS F11VSS E11VSS B8VSS A8VSS D8VSS C8VSS F8VSS E8VSS G26VSS K26VSS J25VSS M25VSS N26VSS T26VSS R25VSS V25VSS W26VSS H24VSS G23VSS K23VSS L24VSS P24VSS N23VSS T23VSS U24VSS Y24VSS W23VSS H21VSS J22VSS M22VSS L21VSS P21VSS R22VSS V22VSS U21VSS Y21

VCCB14VCCA13VCCD14VCCC13VCCF14VCCE13VCCB12VCCA12VCCD12VCCC12VCCF12VCCE12VCCB10VCCB9VCCA10VCCA9VCCD10VCCD9VCCC10VCCC9VCCF10VCCF9VCCE10VCCE9VCCB7

VCCF7VCCA7

R

9

4

5

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

R88 100_0402_1%~D 1 2

P

O

W

E

R

,

G

R

O

U

N

G

,

R

E

S

E

R

V

E

D

S

I

G

N

A

L

S

A

N

D

N

C

YONAH-ULV

U2B


PSI#AE6

GTLREFAD26

VCCSENSEAF7

VCCAB26

VCCAB20VCCAA20VCCAF20VCCAE20VCCAB18VCCAB17VCCAA18VCCAA17VCCAD18VCCAD17VCCAC18VCCAC17VCCAF18VCCAF17

RSVDT22

RSVDV3RSVDB2RSVDC3

VSS AB26VSS AA25VSS AD25VSS AE26VSS AB23VSS AC24VSS AF24VSS AE23VSS AA22VSS AD22VSS AC21VSS AF21VSS AB19VSS AA19VSS AD19VSS AC19VSS AF19VSS AE19VSS AB16VSS AA16VSS AD16VSS AC16VSS AF16VSS AE16VSS AB13VSS AA14VSS AD13VSS AC14VSS AF13VSS AE14VSS AB11VSS AA11VSS AD11VSS AC11VSS AF11VSS AE11VSS AB8VSS AA8VSS AD8VSS AC8VSS AF8VSS AE8VSS AA5VSS AD5VSS AC6VSS AF6VSS AB4VSS AC3VSS AF3VSS AE4VSS AB1VSS AA2VSS AD2VSS AE1VSS B6VSS C5VSS F5VSS E6VSS H6VSS J5VSS M5VSS L6VSS P6VSS R5VSS V5VSS U6VSS Y6VSS A4VSS D4VSS E3VSS H3VSS G4VSS K4VSS L3VSS P3VSS N4VSS T4VSS U3VSS Y3VSS W4VSS D1VSS C2VSS F2VSS G1RSVDB25

VSSSENSEAE7

VCCPK6VCCPJ6VCCPM6VCCPN6VCCPT6VCCPR6VCCPK21VCCPJ21VCCPM21VCCPN21VCCPT21VCCPR21VCCPV21VCCPW21VCCPV6VCCPG21

VID0AD6VID1AF5VID2AE5VID3AF4VID4AE3VID5AF2VID6AE2

BSEL0B22BSEL1B23BSEL2C21

COMP0R26COMP1U26COMP2U1COMP3V1

RSVDC23RSVDC24RSVDAA1RSVDAA4RSVDAB2RSVDAA3RSVDM4RSVDN5RSVDT2

RSVDD2RSVDF6RSVDD3RSVDC1RSVDAF1RSVDD22

VCCE7

C

2

0

1

0

U

_

0

8

0

5

_

6

.

3

V

6

M

~

D

1

2

R

9

1

2

7

.

4

_

0

4

0

2

_

1

%

~

D

1

2

R

9

3

2

7

.

4

_

0

4

0

2

_

1

%

~

D

1

2

C

1

9

0

.

0

1

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2

R871K_0402_1%~D

1

2 R89 100_0402_1%~D 1 2

R

9

2

5

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

R902K_0402_1%~D

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCC_CORE

+VCC_CORE

+VCC_CORE

+1.05V_VCCP

+VCC_CORE

+VCC_CORE

Title



CPU Bypass

9 59Friday, May 12, 2006


High Frequence Decoupling

7mOhmPS CAP

ESR

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_SWNG1

H_SWNG0

H_VREF

V_DDR_MCH_REF

H_A#28

H_A#15

H_SWNG1

H_XRCOMP

H_D#16

H_D#10

H_A#16

H_D#62

H_D#60

H_D#19

H_D#7

H_D#0

H_A#20

H_A#17

H_A#13

H_SWNG0

H_D#53

H_D#39H_D#38

H_D#32

H_D#13

M_OCDOCMP0

H_A#8

H_D#59

H_D#27

H_D#20

H_A#26

H_A#19

H_D#58

H_D#48

H_D#46

H_D#40

H_D#8

H_D#44

H_D#12

H_D#3

H_D#1

H_A#7

H_YSCOMP

H_D#43

H_D#35

H_D#31

H_D#25H_D#24

H_A#22

H_D#61

H_D#56

H_D#21

H_D#11

H_D#6

H_A#27

H_A#6

H_A#3

H_D#37

H_D#33

H_D#30

H_D#63

H_D#51

H_D#9

H_D#2

SMRCOMPN

H_A#25

H_D#50

H_D#41

H_D#36

H_D#23

H_D#4

H_A#12H_A#11

H_D#54

H_D#42

M_OCDOCMP1

H_A#18

H_A#10

H_D#52

H_D#45

H_D#28

H_D#22

H_A#14

H_XSCOMP

H_D#29

H_A#21

H_D#47

H_D#34

H_D#18

H_A#31H_A#30H_A#29

H_A#24H_A#23

H_D#55

H_D#49

H_D#17

H_D#15

M_ODT0

H_A#9

H_A#5H_A#4

H_D#57

H_D#26

H_D#14

H_D#5

H_YRCOMP

M_CLK_DDR1M_CLK_DDR0

M_CLK_DDR#0M_CLK_DDR#1

PM_EXTTS#0

ICH_PWRGD



M_ODT3M_ODT2

PM_EXTTS#1

PM_EXTTS#0

H_DSTBP#0

H_DSTBP#2H_DSTBP#3

H_DSTBN#3

H_DSTBP#1

H_DSTBN#1H_DSTBN#0

H_DSTBN#2

H_DBSY#H_DEFER#

H_DPWR#H_DRDY#

H_HIT#H_HITM#H_LOCK#

H_RS#0

H_RS#2H_RS#1

H_REQ#0

H_REQ#4

H_REQ#2H_REQ#3

H_REQ#1

H_CPUSLP#H_TRDY#

H_RESET#H_VREF

H_BNR#H_BPRI#H_BR0#

H_VREFH_ADSTB#1H_ADSTB#0H_ADS#

V_DDR_MCH_REF

SMRCOMPP

CPU_MCH_BSEL0CPU_MCH_BSEL1CPU_MCH_BSEL2CFG3CFG5

CFG5

CPU_MCH_BSEL0

THERMTRIP_MCH#

DMI_MTX_IRX_N0DMI_MTX_IRX_N1

DMI_MRX_ITX_N0DMI_MRX_ITX_N1

DMI_MTX_IRX_P0DMI_MTX_IRX_P1

DMI_MRX_ITX_P0DMI_MRX_ITX_P1

PLTRST_R#

DDR_CKE0DDR_CKE1DDR_CKE2_DIMMADDR_CKE3_DIMMA

DDR_CS3_DIMMA#DDR_CS2_DIMMA#DDR_CS1#

M_OCDOCMP1M_OCDOCMP0

CFG6

PM_EXTTS#1

M_ODT1

DDR_CS0#

+1.8V_SUS

+3.3V_RUN

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_D#[0..63]

CLK_MCH_BCLK# CLK_MCH_BCLK

H_CPUSLP#

V_DDR_MCH_REF

MCH_DREFCLK MCH_DREFCLK#

ICH_PWRGD

MCH_ICH_SYNC#

CLK_3GPLLREQ#

PM_BMBUSY#

THERMTRIP_MCH#

PLTRST#

H_REQ#[0..4]

H_DPWR# H_DRDY#

H_DSTBP#[0..3]

H_DSTBN#[0..3]

H_HIT# H_HITM# H_LOCK#

H_RS#[0..2]

H_BPRI#

CFG19

CPU_MCH_BSEL0 DMI_MRX_ITX_N0DMI_MRX_ITX_N1DMI_MRX_ITX_P0DMI_MRX_ITX_P1

CPU_MCH_BSEL1 CPU_MCH_BSEL2

DDR_CKE0

DDR_CKE3_DIMMADDR_CKE2_DIMMA

DDR_CS3_DIMMA#DDR_CS2_DIMMA#

DDR_CS0#

H_A#[3..31]

H_ADS# H_ADSTB#0 H_ADSTB#1

H_BNR#

H_BR0# H_RESET#

H_DBSY# H_DEFER# H_DINV#0

H_DINV#2 H_DINV#1

H_DINV#3

H_TRDY#

DMI_MTX_IRX_N0DMI_MTX_IRX_N1DMI_MTX_IRX_P0DMI_MTX_IRX_P1





M_ODT0

M_ODT2M_ODT3

DREF_SSCLK# DREF_SSCLK

PM_EXTTS#0 PM_EXTTS#1

Title



Calistoga(1 of 5)

10 59Friday, May 12, 2006


Layout Note:H_XRCOMP & H_YRCOMP trace widthand spacing is 10/20

Layout Note:Route as shortas possible



Stuff R111 & R112 for A1 Calistoga

(DMI Lane Reversal)CFG19

Calistoga-GMS not have CFG4,CFG[7..18],CFG[20]Need to double check

*Low = DMI x 2High = DMI x 4CFG5

Strap Pin Table

Low = NormalOperation (Default):Lane number in OrderHigh = Reverse Lane

R

1

0

5

2

0

0

_

0

4

0

2

_

1

%

~

D

1

2

C

5

3

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

T2PAD~D

C

5

2

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

R

1

0

4

5

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

R101 80.6_0402_1%~D

1 2

C

F

G

/

R

S

V

D

D

M

I

P

M

D

D

R

2

M

U

X

I

N

G

C

L

K

Calistoga-GMS_FCBGA998~D

U3B

DMI_RXN_0Y29DMI_RXN_1Y32DMI_RXP_0Y28DMI_RXP_1Y31

DMI_TXN_0V28DMI_TXN_1V31DMI_TXP_0V29DMI_TXP_1V32

SM_CK_0AF33SM_CK_1AG1

SM_CK_2AJ1SM_CK_3AM30

SM_CK#_0AG33SM_CK#_1AF1

SM_CK#_2AK1SM_CK#_3AN30

SM_CKE_0AN21SM_CKE_1AN22SM_CKE_2AF26SM_CKE_3AF25

SM_CS#_0AG14SM_CS#_1AF12SM_CS#_2AK14SM_CS#_3AH12

SM_OCDCOMP_0AJ21SM_OCDCOMP_1AF11

SM_ODT_0AE12SM_ODT_1AF14SM_ODT_2AJ14SM_ODT_3AJ12

SM_RCOMPNAN12SM_RCOMPPAN14SM_VREF_0AA33SM_VREF_1AE1 D_REFCLKN A27

D_REFCLKP A26D_REFSSCLKN J33D_REFSSCLKP H33

THRMTRIP# J15PWROK AB29RSTIN# W27

PM_BMBUSY# G21PM_EXTTS#_0 F26

CFG_0 C18CFG_1 E18CFG_2 G20

CFG_5 J20CFG_6 J18

PM_EXTTS#_1 H26

RESERVED8 F18

CLKREQ# J22

CFG_3 G18

PM_ICHSYNC# E31

RESERVED9 A3

RESERVED7 C17

RESERVED1 K32RESERVED2 K31

R

1

0

Documents

compal_la-3071p_r1.0_schematics.pdf