Combining High Level Synthesis and Floorplan Together

EDA Lab, Tsinghua University

Jinian Bian

Outlines

Background Combining High Level Synthesis

and Floorplan together The evolution of Combing HLS and

Floorplan The Basic Structure of Combining HLS

and Floorplan Conclusion and our future work

Background The progress of manufactory

technique for silicon chips has been slowed down under traditional design methodology

High performance / Low cost / Low power should be achieved by a more refined design, which means we need more powerful EDA tools

Background The traditional EDA methodology has

been challenged The interconnect takes up most of resources:

including area resource, delay resource, and power resource, etc.

The traditional design flow may cause a long design time, low design quality, even design failure under nanometer design environment

High performance / Low cost / Low power should be achieved by a more refined design, which means we need more powerful EDA tools

Traditional Design Flow

High Level Synthesis

Floorplan

HLS Optimize OK?

FP Optimize OK?

Chip Optimize OK?

N

Y

N

Y

N

Problems

High Level Synthesis and Floorplan are based on different Optimization Model

No Interconnect Information in High Level Synthesis

No Behavior Information in Floorplan May cause a long design time, low

design quality, even design failure

Forgoing Optimized Flow

High Level Synthesis

Meet Constraints?

Fast Floorplan

HLS & Fast FP

Optimized OK?

Final Floorplan

Chip Optimized OK?

N

Y

Y

N

Y

Y

N

Y

Forgoing optimized Flow High level synthesis using floorplan to get s

ome physical information; Re-synthesis after floorplanning to optimize

the design.But, Long loop time ； The estimation of Interconnect Information

may far from final Chip ； Floorplan is passive.

Optimized Design Flow

Interconnect Information can be got through a fast floorplan tool

The estimation of Interconnect Information may far from final Chip

Proposed New Design Flow

High Level Synthesis FloorplanQ/A

The Chip

Controller

Proposed Design Flow High Level Synthesis and Floorplan can communic

ate with each other The functionality of High Level Synthesis and Floor

plan are both enhanced The result of allocation and scheduling can be restructure

d by Floorplan The Information of Interconnect can be retrieved easily The optimization of HLS and FP are based on a same esti

mation model Evolutional synthesis and floorplanning, to guaran

tee quicker astringency

预 处 理

系统行为描述 系统约束

电路优化结果：包括优化的电路逻辑和优化的电路模块布局规划

与布图规划 结合的高层 次综合

面向高层次综合的物理信息估计参数化

功能单元库

约束和行为信息驱动的布图规划

面向模块物理信息估计的快速布图规划和布局

?满足基本约束

No

布图规划后增量式高层次再综合

再综合后增量式布图规划

Target Design Flow

The main loop from High Level Synthesis and Floorplan can be avoid

The optimizations of High Level Synthesis and Floorplan are consistent

Can achieve a shorter running time of tools and a better quality of circuits

To Achieve the “Target Design Flow”

1. High Level Synthesis Oriented Physical Information Estimation

2. Floorplan Aware High Level Synthesis

3. Behavior Aware Floorplan4. High Level Synthesis and Floorplan

Oriented Parameterized Functional Unit Library

1. High Level Synthesis Oriented Physical Information Estimation

HLS oriented high level physical information model and estimation technology

Physical Information Estimation oriented fast floorplan and placement

1.1 HLS oriented physical information model and estimation technology of a module

To create HLS oriented physical information model ， through studying the existing information of physical design and IP core

To study the relationship of logic struction vs. physical information (interconnect, power, conjestive, etc.) before phsical design

1.2 quick floorplanning technique to estimate physical information

To get physical information with different accurate

Techniques: Partitioning and clustering Quick floorplanning algorithm Placement information in a module

2. Floorplan Aware High Level Synthesis

Floorplan aware High Level Synthesis Pre-partition before floorplan Interconnect aware HLS Analysis and Information retrieval of the

result of Floorplan Constraints generation for Floorplan Incremental High Level Synthesis

after Floorplan

Floorplan Aware High Level Synthesis

Constraints from HLS to floorplan boundary constraints, adjacent constraints, separation constraints, delay constraints of each net, alternative modules for each functional unit, area constraints, etc.

Constraints from floorplan to HLS delay constraints for each functional unit, area constraints for each functional unit, etc.

High Level Physical Information Estimation

Scheduling and Allocation

Floorplan

Floorplan Constraints Generation

FeedBack: HLS Constraints Generation

Delay ConstraintIn HLS

Adjacent ConstraintIn Floorplan

Allocation ConstraintIn HLS

2.1. HLS techniques combined with floorplanning HLS algorithm considering physical

info. of every module and the interconnect information between modules

Get information from a module library with functionality and performance parameters and justify the design result

Technology mapping and functional unit assignment

2.2 floorplanning constraint generation after HLS To transfer the information, requests and c

onstraints of HLS to floorplanning E.g. group information, adjacent relationshi

p, critical paths, etc.

2.3 Re-synthesis after floorplanning

Adjust functional unit assignment and binding without florplan result to enhance the performance .

Adjust schedule result to change the timing constraint

To enhance the layout result.

3. Behavior Aware Floorplan

Behavior aware Floorplan Partition and Clustor based on

behavior information Floorplan under uncertain data

Floorplan can change the result of allocation from HLS

Incremental Floorplan after High Level Resynthesis

3.1. Constraints and behavior driven floorplanning To satisfy the circuit functionality and

timing constaints Behavior constraints are as a guidanc

e for floorplanning

3.2. floorplanning technique with incomplete information including ：

Undetermined module shapes or areas Undetermined pins ， Undetermined module numbers

Possible solutions Soft-module floorplanning techniques Shape-alterable polygons Unit and module mixed Etc.

3.3. Incremental floorplanning after synthesis

To keep the basic structure and to keep the parameter unchanged.

4. HLS and Floorplan Oriented Parameterized FU Library

Functional Unit Interface for both High Level Synthesis and Floorplan Provide prototype and instance of

each functional unit Fast Estimation of physical

information for un-stored functional unit

Conclusion and future work

The main frame of Combining High Level Synthesis and Floorplan

The structure of the parameterized functional unit library

Conclusion and future work

Floorplan aware High Level Synthesis

Floorplan under uncertain conditions

Constraints and feedback generation and transfer between High Level Synthesis and Floorplan

Thank You!