Combinational logic circuits author :Ansari M.A.

3.1 Standard Boolean expression: Sum of product (SOP), product of sum(POS),min-term and max-term conversion between SOP a d POS forms, realization using NAND/NOR gates.

3.2 k-map reduction technique for Boolean expression.: Minimization of Boolean function upto 4 variables, (SOP & POS form).

3.3. Design of arithmetic circuits and code convertor using k-map : Half and full adder, Half and full subtractor, Grey to binary and binary to grey (up to 4 bits) 3.4 Arihtmatic circuits: (IC 7483) adder, subtractor and BCD adder, 3.5 Encoder,/Decoder : Basic of encoder, decoder, comparision, (IC 7447) bcd to 7 segment decoder/driver, 3.6: Multiplexer , Demultiplexer

The digital systems in general are classified into two categories namely,

1. Combinational logic circuits 2. Sequential logic circuit.

Compare combinational and sequential circuits (four points).

Standard representation for logical functions: Boolean expressions / logic expressions / logical functions are expressed in

terms of logical variables. Logical variables can have value either ‘0’ or ‘1’. The

logical functions can be represented in one of the following forms.

- Sum of Products form (SOP form)

- Product of Sums form (POS form)

Sum of Products (SOP) form: In this form, Boolean expression is defined by sum of product terms.

In SOP,each AND term may be a single variable or a product of multiple variables are ORed

together.

Example 1:

𝑌 = 𝐴𝐶 + 𝐴 𝐶 + Expanded form of Boolean expression in which each term contains all

the Boolean variables in it is called as canonical form. It is also called as standard sum of

products form.

Product of Sums (POS) form: In this form, Boolean expression is defined by product of sum terms.

Various OR terms are ANDed together.

Example 1:

𝑌 = (𝐴 + 𝐶). ( + 𝐶). 𝐴 Expanded form of Boolean expression in which each term contains all the

Boolean variables in it is called as canonical form. It is also called as

standard product of sums form.

Define Minterm and Maxterm : ( 2marks) Minterm: Each individual term in the canonical SOP form is called as minterm.

CANONICAL SOP 𝑌 = A 𝐶 + 𝐴 𝐶 + 𝐴 𝐶 minterm

Maxterm: Each individual term in the canonical POS form is called as maxterm.

CANONICAL POS 𝑌 = (𝐴 + +C) . (𝐴 + + 𝐶 ) .(𝐴 + + 𝐶 )

Maxterm

Minterm and maxterm for 3 variables

Variables Minterm (mi) Maxterm (Mi)

A B C

0 0 0 𝐴 𝐶 =m0 A+B+C=M0 0 0 1 𝐴 C=m1 A+B+ 𝐶 =M1 0 1 0 𝐴 B 𝐶 =m2 A+ + C=M2 0 1 1 𝐴 BC=m3 A+ + 𝐶 =M3 1 0 0 A 𝐶 =m4 𝐴 +B+C=M4 1 0 1 A C =m5 𝐴 +B+ 𝐶 =M5 1 1 0 AB 𝐶 =m6 𝐴 + +C=M6 1 1 1 ABC=m7 𝐴 + + 𝐶 =M7

Write simple example of Boolean expression for SOP and POS.

k-map (Karnaugh map): It is a technique used for simplification to reduce the Boolean algebra.

1. It is a graphical method of simplifying a Boolean equation. 2. The information contained in a truth table or available in the SOP or POS form can be represented on

a k-map.

3. K-map can be written for 2,3,4… upto 6 variables.

k-map structure : A two-variable K-map can be drawn with various possibilities. Two possibilities are shown in figure.

A three-variable K-map can be drawn with various possibilities

ways of representing a 3-variable K-map

A four-variable K-map can be drawn with various possibilities.

Two ways of representing a 4-variable K-map

Explain the rules to simplify Boolean equation using K-map (any two). Rules

to simplify Boolean equation using K-map: 1. Enter a „1‟ on the K-map for each fundamental product that produces a „1‟ in the truth table.

Enter „o‟ case „o‟ else where.

2. Encircle the octet, quads, pairs remember to roll and overlap to get the largest group possible. 3. If any isolated „1‟ remains encircle each.

4. Eliminate any redundant group.

5. Write the Boolean expression by „o‟ ring the product corresponding to encircled groups.

Representation SOP on K-map: If the given Boolean expression is not in standard SOP form, it should be first converted to standard SOP form. Then its minterms are written.

For each minterm in the expression, ‘1’ is written in the corresponding cell in the K-map and

the remaining cells are marked as ‘0’.

Example 1:

Represent following Boolean expression by K-map.

𝑌 = 𝐶 + 𝐴 𝐶 + 𝐴 𝐶 The above expression is in SOP form. It is a function of three variables A, B and C. As

each term is not containing all the variables, it is not in standard SOP form. So,

converting it into standard SOP form,

𝑌(𝐴, , 𝐶) = . 𝐶 + 𝐴 . . 𝐶 + 𝐴. . 𝐶 = (𝐴 + 𝐴 ). . 𝐶 + 𝐴 . . 𝐶 + 𝐴. . 𝐶 𝑌(𝐴, , 𝐶) = 𝐴. . 𝐶 + 𝐴 . . 𝐶 + 𝐴 . . 𝐶 + 𝐴. . 𝐶 1 1 1 0 1 1 0 0 0 1 1 0

m7 m3 m0 m6

(𝐴, , 𝐶) = Σ (0,3,6,7)

Representation POS on K-map:-

If the given Boolean expression is not in standard POS form, it should be

first converted to standard POS form. Then its maxterms are written. For each

maxterm in the expression, ‘0’ is written in the corresponding cell in the K-map

and the remaining cells are marked as ‘1’.

Example 1:

Represent following Boolean expression by K-map.

𝑌 = (𝐴 + ) + (𝐴 + + 𝐶 ) + (𝐴 + + 𝐶 ) The above expression is in POS form. It is a function of three

variables A, B and C. As each term is not containing all the variables, it is not in

standard POS form. So, converting it into standard POS form,

𝑌(𝐴, , 𝐶) = (𝐴 + ) + (𝐴 + + 𝐶 ) + (𝐴 + + 𝐶 ) = (𝐴 + + 𝐶. 𝐶 ) + (𝐴 + + 𝐶 ) + (𝐴 + + 𝐶 ) = (𝐴 + + 𝐶) + (𝐴 + + 𝐶 ) + (𝐴 + + 𝐶 ) + (𝐴 + + 𝐶 ) 𝑌(𝐴, , 𝐶) = (𝐴 + + 𝐶) + (𝐴 + + 𝐶 ) + (𝐴 + + 𝐶 ) 0 0 0 0 0 1 1 1 1

M0 M1 M7

(𝐴, , 𝐶) = Π(0,1,7)

Simplify the following equation using K-map and realize it using logic gates Y =

𝜮m(1, 5, 7, 9, 11, 13, 15).

Minimize the following equation using K-map i) F(A,B,C,D) = 𝝅 M (4,6,11,14, 15) ii) F(A,B,C,D) = Σm (1.3,7,11, 15)+d(0,2,5) i) F(A,B,C,D) = 𝝅 M (4,6,11,14, 15

ii) F(A,B,C,D) = Σm (1.3,7,11, 15)+d(0,2,5)

Minimize the following expression using K-Map.

ƒ(A, B, C, D) = Σm (0, 1, 2, 4, 5, 7, 8, 9, 10)

Convert F(A,B,C)= Σm(1,4,5,6,7) in standard POS form.

Design Half adder using k-map and basic gates.

Describe the function of full Adder Circuit using its truth table, K-Map simplification

and logic diagram.( Diagram- 1M,Truth table-1M, K-map- 1M,Logic diagram-1 M) A full adder is a combinational logic circuit that performs addition between three bits, the two input bits A

and B, and carry C from the previous bit.

Block diagram :

Truth Table :

State the difference between Half and Full adder. Half adder is a circuit that adds 2 binary bits.

A full adder is a circuit the adds 3 bits (2 bits along with carry).

Explain working of full substractor with circuit diagram. A full substractor is used for performing multibit substraction where the borrow from the previous bit

position is available. This circuit has three inputs An (minuend), Bn (subtrahend) and Bn-1 (borrow from

previous stage) and two outputs Difference (Dn) and Borrow (Cn).

Design a full adder using half adder. 4 (Designing - 4 marks) Full Adder is a combinational circuit that performs the addition of three bits (two significant bits and previous

carry). It consists of three inputs and two outputs, two inputs are the bits to be added, the third input

represents the carry form the previous position.

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will half adder will

be used to add A and B to produce a partial Sum. The second half adder logic can be used to add CIN to the Sum

produced by the first half adder to get the final S output. If any of the half adder logic produces a carry, there

will be an output carry. Thus, COUT will be an OR function of the half-adder Carry outputs.

Design one digit BCD Adder using IC 7483

What is MUX & De-MUX :

De-MUX : A de-multiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. At a time , only one output line is selected by the select lines and the input

is routed to the selected output line.

State application of MUX and De-MUX.

Application of MUX: 1. Implementing multi output combinational logic circuit

2. Multiplexer allow the process of transmitting different type of data such as audio, video at the same time

using a single transmission line.

3. In telephone network, multiple audio signals are integrated on a single line for transmission with the help

of multiplexers.

5. Multiplexers are used to implement huge amount of memory into the computer, at the same time reduces

the number of copper lines required to connect the memory to other parts of the computer circuit.

6. Multiplexer can be used for the transmission of data signals from the computer system of a satellite or

spacecraft to the ground system using the GPS (Global Positioning System) satellites.

Application of De-MUX: 1. Decoder

2. Demultiplexer is used to connect a single source to multiple

destinations.

3. In an ALU circuit, the output of ALU can be stored in multiple registers or storage units with the help of

demultiplexer.

4. Serial data from the incoming serial data stream is given as data

input to the demultiplexer at the regular intervals.

Necessity of Multiplexer: It reduces the number of wires required to pass data from source to

destination.

For minimizing the hardware circuit.

For simplifying logic design.

In most digital circuits, many signals or channels are to be transmitted,

and then it becomes necessary to send the data on a single line

simultaneously.

Reduces the cost as sending many signals separately is expensive and

requires more wires to send.

Define and draw the logical symbol of demultiplexer.

Demultiplexer: It is a combinational logic circuit which has only one input, n outputs and m select lines

Realize the logic function of the truth table given below using a multiplexer.

Design 8:1, MUX using 2:1 MUX and 4:1 MUX. (Diagram 4M)

Implement the following logic expression using 16 : 1 MUX Y = Σ m (0, 3, 5, 6, 7, 10, 13).

Design 1:8 De Mux using basic gates. (Truth Table 2M, circuit diagram 2M) Depending on the combination of the select inputs S2 S1 S0 the data input Din is connected to one of the eight outputs. For example if S2 S1 S0=1 1 0 then Din is connected

to output Y6.

The truth Table

The circuit diagram of 1:8 demultiplexer

Draw 8: 1 multiplexer using basic logic gates.

Design 1:4 demultiplexer using 1:2 demultiplexer. 1:4 demultiplexer using

1:2 demultiplexer:

Design 16 : 1 multiplexer using 8 : 1 multiplexer (Note: Any other correct diagram may

also be considered)

Draw 16:1 MUX tree using 4:1 MUX.

Implement 1 : 16 demultiplexer using 1 : 8 demultiplexer.

Obtain an 1:8 demultiplexer using 1:4 demultiplexer.

Draw block diagram of decimal to BCD encoder and write its truth table.

Draw BCD to seven segment decoder using IC 7447 and give function of each

pin.

The 74LS47 display decoder receives the BCD code and generates the necessary signals to activate the

appropriate LED segments responsible for displaying the number of pulses applied. As the 74LS47 decoder is

designed for driving a common-anode display, a LOW (logic-0) output will illuminate an LED segment while a

HIGH (logic-1) output will turn it “OFF”. For normal operation, the LT (Lamp test), BI/RBO (Blanking

Input/Ripple Blanking Output) and RBI (Ripple Blanking Input) must all be open or connected to logic-1

(HIGH). The functions of the pins are:

LT (Lamp test): This is used to check the segments of LED. If it is connected to logic 0 all the segments of the display connected to the decoder will be ON. For normal decoding this terminal is to be connected to logic

1 level.

RBI (Ripple Blanking Input): It is to be connected to logic 1 for normal decoding operations. If it is connected to logic 0 the segment outputs will generate data for normal 7 segment decoding of all BCD inputs

except zero. Whenever the BCD input correspond to zero, the 7 segment display switches off. This is used for

blanking out leading zeros in multi digit displays.

BI (Blanking input): If it is connected to 0 level, the display is switched off irrespective of BCD inputs. That is used for conserving power in multiplexed displays.

RBO (Ripple Blanking output): This output which is normally at logic 1 goes to logic 0 during the zero blanking interval. This is used for cascading purpose and is connected to RBI of succeeding stages.

Define encoder. Write the number of IC used as decimal to BCD encoder. (Definition 1M, Number 1M) Encoder is a combinational circuit which is designed to accept an n i/p digital word & converts it into m bit another digital word. IC 74147-Decimal to BCD encoder.

Digital comparator : Describe block diagram of digital comparator and write truth table of 2 bit comparator. Digital comparator is a combinational circuit which compares two numbers, A and B; and evaluates their relative

magnitudes.

The outcome of the comparison is given by three binary variables which indicate whether

A = B or A > B or A < B.

Depending on the result of comparison one of these outputs will go high.