COE 1502Design Synthesis

Synthesis Theory

Idea:– “Compile” VHDL into a cell-level netlist

A netlist is a graph– Vertices represent cells (such as gates, latches, etc.)– Edges represent interconnection wires

To do this, we need– VHDL– A technology cell library

– Place-and-route netlist onto FPGA/ASIC To do this, we need

– Netlist– CLB specification and routing matrix (FPGA)

Output is FPGA routing bitmap

Netlists

Leonardo Spectrum’s output format is a text EDIF netlist Example:

port

port

port

OR2

AND2

port

A

B

C

D

E

instance OR2 as ix1instance AND2 as ix3

ix1 A B Dix3 D C E

Note that AND2 and OR2 are technology cells

Netlists

Actual Leonardo output:

(edif example (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2003 01 23 17 13 48) (program "LeonardoSpectrum Level 3" (version "2002b.21")) (author "Exemplar Logic Inc"))) (external PRIMITIVES (edifLevel 0) (technology (numberDefinition )) (cell OR2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p0 "in[0]") (direction INPUT)) (port (rename p1 "in[1]") (direction INPUT)) (port out (direction OUTPUT))))) (cell AND2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p2 "in[0]") (direction INPUT)) (port (rename p3 "in[1]") (direction INPUT)) (port out (direction OUTPUT))))))

(library alu (edifLevel 0) (technology (numberDefinition )) (cell example (cellType GENERIC) (view struct (viewType NETLIST) (interface (port A (direction INPUT)) (port B (direction INPUT)) (port C (direction INPUT)) (port E (direction OUTPUT))) (contents (instance ix1 (viewRef INTERFACE (cellRef OR2 (libraryRef PRIMITIVES )))) (instance ix3 (viewRef INTERFACE (cellRef AND2 (libraryRef PRIMITIVES )))) (net A (joined (portRef A ) (portRef p0 (instanceRef ix1 )))) (net B (joined (portRef B ) (portRef p1 (instanceRef ix1 )))) (net C (joined (portRef C ) (portRef p3 (instanceRef ix3 )))) (net E (joined (portRef E ) (portRef out (instanceRef ix3 )))) (net D (joined (portRef out (instanceRef ix1 )) (portRef p2 (instanceRef ix3 )))))))) (design example (cellRef example (libraryRef alu ))))

ALU Wrapper

Your ALU design must be placed into a wrapper before you perform synthesis

– The ALU wrapper is located in the COELib library Wrapper shares a signal namespace with its wrapper and the signals

on the Wild-One card Copy the wrapper to your ALU library

– Your ALU is already instantiated inside Your job:

– Wire up desired signals to 32 output buffers (which will be visible on the logic analyzer for testing)

– Topmost buffer corresponds to LSB on LA (wire downward)– Suggestion: bring out ALUOp, 8 bits of A, B, and R, and Overflow, Zero,

RST, and PCLK One you do this, generate a netlist for the wrapper using Leonardo

– Use the tutorial on the website

ALU Wrapper

Your ALU

Registers from host

Lad bus interfacel

AnalyzerData

host (out) reg

ALU Wrapper – wildfire card

Your ALU in pe0

pe1

Daughter card connectors

PCI interface

Memory

ALU Wrapper

Da

ug

hte

r card

con

ne

ctor

PCI host interface (LAD Bus

FPGA

TO

PE

1D

RA

M

Pinout wrapper

ALU wrapper

ALU

Preparing for Synthesis

Copy the wrapper design from COElib to your project lib

Make sure that the ALU instance in the wrapper maps to your design

Wrapper file

Running synthesis

Xilinx Synthesis setup windows

Synthesisoutput

Place-and-route

Once we have the netlist, we need to build the FPGA configuration file

– GOAL: map netlist onto FPGA by writing to CLBs and perform routing

– CLBs use registered lookup tables, so cells need to be translated into SRAM cells

Place and Route Xilinx environment

More setup windows

Start place and route

SetupPropertiesand run

Convert output to bin file

promgen –u 0 pe.bit –p bin -w

Placing and Routing

Place and route the design…– Open a command window using Start | Run | cmd– Change to your project directory– run promgen –u 0 pe.bit –p bin -w

Host interface