Coa 5

7/31/2019 Coa 5

1/14

http://

csetub

e.co

.nr/

Lecture planCode & name of subject: 141403 computer organization and architecture

Unit no: 5

Accessing I/O DevicesInterface to CPU and Memory

Interface to one or more peripherals

Generic Model of IO Module

http://csetube.co.nr/
http://csetube.co.nr/http://csetube.co.nr/

7/31/2019 Coa 5

2/14

http://

csetub

e.co

.nr/


Unit no: 5

Interface for an IO Device:

CPU checks I/O module device status I/O module returns statusIf ready, CPU requests data transfer I/O module gets data from deviceI/O module transfers data to CPU

Programmed I/O

CPU has direct control over I/OSensing statusRead/write commands

Transferring data

CPU waits for I/O module to complete operationWastes CPU timeCPU requests I/O operationI/O module performs operation

I/O module sets status bitsCPU checks status bits periodicallyI/O module does not inform CPU directly

I/O module does not interrupt CPUCPU may wait or come back later

Under programmed I/O data transfer is very like memory access (CPU viewpoint)Each device given unique identifier

IO interface circuits:

->task of connecting an IO device to a computer system is greatly eased


7/31/2019 Coa 5

3/14

http://

csetub

e.co

.nr/


Unit no: 5

By the use of standard ICs known as IO interfacing circuits.

-->the simplest interface circuits is a one-word, addressable register that

Serves as an I/o port.

most basic IO interface circuits are programmable circuits intended toAct as serial or parallel ports .serial ports accommodate many types of slow peripheral

Devices ranging from secondary memory units to network connections.

I/O Mapping

Memory mapped I/O

Devices and memory share an address spaceI/O looks just like memory read/writeNo special commands for I/O

Large selection of memory access commands available

Isolated I/OSeparate address spacesNeed I/O or memory select lines

Special commands for I/O

Interrupt driven and programmed I/O require active CPU intervention (All datamust pass through CPU)

Transfer rate is limited by processor's ability to service the device

CPU is tied up managing I/O transfer

Additional Module (hardware) on bus DMA controller takes over bus from CPU for I/O

Waiting for a time when the processor doesn't need bus Cycle stealing seizing bus from CPU

Transfer of control through the use of interrupts


7/31/2019 Coa 5

4/14

http://

csetub

e.co

.nr/


Unit no: 5

An interrupt is an asynchronous signal indicating the need for attention or asynchronous event in software indicating the need for a change in execution.

A hardware interrupt causes the processor to save its state of execution and beginexecution of an interrupt handler. Software interrupts are usually implemented as

instructions in the instruction set, which cause a context switch to an interrupt handler

similar to a hardware interrupt.

Interrupts are a commonly used technique for computer multitasking, especially in

real-time computing. Such a system is said to be interrupt-driven.

An act ofinterruptingis referred to as an interrupt request (IRQ).

When there is an interrupt, continuation of the execution of the current program is

meaningless.

Execution of the Current program needs to be stopped

In a computer system, there are many sources of interrupts

Needs to prepare interrupt processing routines for each source of interrupts

Source of interrupt needs to be identified

Needs to initiate execution of the interrupt processing routine associatedwith the identified interrupt

When the interrupt is resolved, the interrupted program needs to be continued for the

efficiency reason

Needs to resume execution of the interrupted program.


7/31/2019 Coa 5

5/14

http://

csetub

e.co

.nr/


Unit no: 5

Vectored interrupts

In a computer, a vectored interrupt is an I/O interrupt that tells the part of the computer

that handles I/O interrupts at the hardware level that a request for attention from an I/Odevice has been received and and also identifies the device that sent the request.

A vectored interrupt is an alternative to a polled interrupt , which requires that theinterrupt handler poll or send a signal to each device in turn in order to find out which

one sent the interrupt request.

PCI interrupts

Devices are required to follow a protocol so that the interrupt lines can be shared. The

PCI bus includes four interrupt lines, all of which are available to each device. However,

they are not wired in parallel as are the other PCI bus lines.

PCI bridges (between two PCI buses) map the four interrupt traces on each of theirsides in varying ways.The result is that it can be impossible to determine how a PCIdevice's interrupts will appear to software.

PCI interrupt lines are level-triggered. This was chosen overedge-triggering in order togain an advantage when servicing a shared interrupt line, and for robustness: edge

triggered interrupts are easy to miss.

PCI Express does not have physical interrupt lines at all. It uses message-signaled

interrupts exclusively.

pipeline interrupt

Interrupt: Hardware signal to switch processor to new instruction stream.

When interrupt occurs, state of interrupted process is saved, including PC, registers,

and memory

Interrupt is precise if the following three conditions hold:

All instructions preceding u have been executed, and have modified the state correctly

All instructions following u are unexecuted, and have not modified the

state If the interrupt was caused by an instruction, it was caused by instruction

u, which is either completely executed (e.g.: overflow) or completely

unexecuted (e.g: VM page fault).


7/31/2019 Coa 5

6/14

http://

csetub

e.co

.nr/


Unit no: 5

Precise interrupts are desirable if software is to fix up error that caused interrupt and

execution has to be resumed

Easy for external interrupts, could be complex and costly for internal

Imperative for some interrupts (VM page faults, IEEE FP standard)

Direct Memory Access (DMA)

Polling or interrupt driven I/O incurs considerable overhead

Multiple program instructions

Saving program state

Incrementing memory addresses

Keeping track of word count

Transfer large amounts of data at high speed without continuous intervention by theprocessor

Special control circuit required in the I/O device interface, called a DMA controller

DMA controller keeps track of memory locations, transfers directly to memory (via thebus) independent of the processor

Single Bus, Detached DMA controller

Each transfer uses bus twice I/O to DMA then DMA to memory

CPU is suspended twice

Single Bus, DMA controller integrated into I/O module

Controller may support one or more devices

Each transfer uses bus once DMA to memory CPU is suspended once

Operation of a DMA transfer


7/31/2019 Coa 5

7/14

http://

csetub

e.co

.nr/


Unit no: 5

DMA ControllerPart of the I/O device interfaceDMA Channels

Performs functions that would normally be carried out by the processorProvides memory address

Bus signals that control transferKeeps track of number of transfers

Under control of the processor

Buses, Bus control, bus interfacing, Bus arbitration

Buses:A bus is a subsystem that transfers data between components inside a

computer, or between computers.

Multiple devices communicating over a single set of wires

Only one device can talk at a time or the message is garbled Each line or wire of a bus can at any one time contain a single binary digit. Over

time, however, a sequence of binary digits may be transferred

These lines may and often do send information in parallel A computer system may contain a number of different buses


7/31/2019 Coa 5

8/14

http://

csetub

e.co

.nr/


Unit no: 5

Bus Interconnection

A bus is a communication pathway connecting two or more device. A key characteristic of a bus is that it is a shared transmission medium. A bus consists of multiple pathways or lines.

Each line is capable of transmitting signal representing binary digit (1 or 0

A sequence of bits can be transmit across a single line. Several lines can be used to transmit bits simultaneously (in parallel).

A bus that connects major components (CPU,Memory,I/O) is called System Bus. The most common computer interconnection structures are based on the use of

one or more system buses.

Bus interfacing Synchronous occurrence of events on the bus is determined by a clock

(Clock Cycle or Bus Cycle) which includes line upon

Asynchronous occurrence of one event follows and depends on the previous event

Bus arbitration Centralized bus controller (Arbiter), hardware device,is responsible for

allocating time on the bus (daisy chain)


7/31/2019 Coa 5

9/14

http://

csetub

e.co

.nr/


Unit no: 5

Distributed access control logic in each module act together to share bus

INTERFACE CIRCUITS

Circuitry required connecting an I/O device to a computer bus

Provides a storage buffer for at least one word of data.

Contains status flag that can be accessed by the processor.

Contains address-decoding circuitry

Generates the appropriate timing signals required by the bus control scheme.

Performs format conversions

Ports

Serial port

Parallel port


7/31/2019 Coa 5

10/14

http://

csetub

e.co

.nr/


Unit no: 5

Figure . An example of a computer system using different interface

standards.


7/31/2019 Coa 5

11/14

http://

csetub

e.co

.nr/


Unit no: 5

PCI (Peripheral Component Interconnect)

PCI stands for Peripheral Component Interconnect

Introduced in 1992

It is a Low-cost bus

It is Processor independent

It has Plug-and-play capability

PCI bus transactions

PCI bus traffic is made of a series of PCI bus transactions. Each transaction is madeup of an address phase followed by one or more data phases. The direction of the data

phases may be from initator to target (write transaction) or vice-versa (read transaction), butall of the data phases must be in the same direction. Either party may pause or halt the data

phases at any point. (One common example is a low-performance PCI device that does notsupport burst transactions, and always halts a transaction after the first data phase.)

Any PCI device may initiate a transaction. First, it must request permission from a

PCI bus arbiter on the motherboard. The arbiter grant permission to one of the requesting

devices. The initiator begins the address phase by broadcasting a 32-bit address plus a 4-bitcommand code, then waits for a target to respond. All other devices examine this address andone of them responds a few cycles later.

64-bit addressing is done using a 2-stage address phase. The initiator broadcasts the

low 32 address bits, accompanied by a special "dual address cycle" command code. Deviceswhich do not support 64-bit addressing can simply not respond to that command code. Thenext cycle, the initiator transmits the high 32 address bits, plus the real command code. Thetransaction operates identically from that point on. To ensure compatibility with 32-bit PCI

devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order

address bits are all zero.While the PCI bus transfers 32 bits per data phase, the initiator

transmits a 4-bit byte mask indicating which 8-bit bytes are to be considered significant. In

particular, a masked write must affect only the desired bytes in the target PCI device.

Arbitration

Address phase Address phase timing

Data phases

Ending transactions

Table 4.3. Data transfer signals on the PCI bus.


7/31/2019 Coa 5

12/14

http://

csetub

e.co

.nr/


Unit no: 5

SCSI Bus Defined by ANSI X3.131

Small Computer System Interface

50, 68 or 80 pins

Max. transfer rate 160 MB/s, 320 MB/s.

SCSI Bus Signals


7/31/2019 Coa 5

13/14

http://

csetub

e.co

.nr/


Unit no: 5

USB - Universal Serial Bus

Speed

Low-speed(1.5 Mb/s)

Full-speed(12 Mb/s)

High-speed(480 Mb/s)

Port Limitation

Device Characteristics

Plug-and-play


7/31/2019 Coa 5

14/14

http://

csetub

e.co

.nr/


Unit no: 5

Universal Serial Bus Tree

Structure

USB (Universal Serial Bus) is a specification to establish communicationbetween devices and a host controller (usually personal computers). USB is

intended to replace many varieties of serial and parallel ports. USB can connect

computer peripherals such as mice, keyboards, digital cameras, printers, personalmedia players, flash drives, and external hard drives. For many of those devices,

USB has become the standard connection method. USB was designed for personal

computers[citation needed], but it has become commonplace on other devicessuch as smartphones, PDAs and video game consoles, and as a power cord

between a device and an AC adapter plugged into a wall plug for charging. As of

2008, there are about 2 billion USB devices sold per year, and approximately 6

billion total sold to date.


Documents

Coa 5