CO-II B.tech (IT)-Notes-register Transfer Lang. & Microoperation-PDF (1)

7/17/2019 CO-II B.tech (IT)-Notes-register Transfer Lang. & Microoperation-PDF (1)

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1

Chapter 7Chapter 7Henry Hexmoor Henry Hexmoor

Registers and RTLRegisters and RTL



REGISTER TRANSFER AND ICR!!"ERATI!NS

# Register Trans$er Lang%age

# Register Trans$er

# &%s and emory Trans$ers

# Arithmeti' i'rooperations

# Logi' i'rooperations

# Shi$t i'rooperations

# Arithmeti' Logi' Shi$t (nit



SI"LE DIGITAL S)STES

• Com*inationa+ and se,%entia+ 'ir'%its 'an *e %sed to 'reate simp+edigita+ systems-

• These are the +o./+e0e+ *%i+ding *+o's o$ a digita+ 'omp%ter-

• Simp+e digita+ systems are $re,%ent+y 'hara'teri2ed in terms o$ – the registers they 'ontain3 and

– the operations that they per$orm-

• Typi'a++y3

– 4hat operations are per$ormed on the data in the registers

– 4hat in$ormation is passed *et.een registers



ICR!!"ERATI!NS 516

Register Transfer Language

• The operations on the data in registers are 'a++edmi'rooperations-

• The $%n'tions *%i+t into registers are examp+es o$mi'rooperations – Shi$t

– Load – C+ear

– In'rement

–



ICR!!"ERATI!N 586

An e+ementary operation per$ormed 5d%ringone '+o' p%+se63 on the in$ormation storedin one or more registers

R←

$5R3 R6

$9 shi$t3 +oad3 '+ear3 in'rement3 add3 s%*tra't3 'omp+ement3

and3 or3 xor3

AL(5$6

Registers5R6 1 '+o' 'y'+e




!RGANI:ATI!N !F A DIGITAL S)STE

/ Set o$ registers and their $%n'tions

/ i'rooperations set

Set o$ a++o.a*+e mi'rooperations pro0ided *y the organi2ation o$ the 'omp%ter

/ Contro+ signa+s that initiate the se,%en'e o$mi'rooperations 5to per$orm the $%n'tions6

• De$inition o$ the 5interna+6 organi2ation o$ a 'omp%ter




REGISTER TRANSFER LE;EL


• ;ie.ing a 'omp%ter3 or any digita+ system3 in this .ay is'a++ed the register trans$er +e0e+

• This is *e'a%se .e<re $o'%sing on – The system<s registers

– The data trans$ormations in them3 and – The data trans$ers *et.een them-



REGISTER TRANSFER LANG(AGE


• Rather than spe'i$ying a digita+ system in .ords3 a spe'i$i'notation is %sed3 register transfer language

• For any $%n'tion o$ the 'omp%ter3 the register trans$er+ang%age 'an *e %sed to des'ri*e the 5se,%en'e o$6

mi'rooperations

• Register trans$er +ang%age – A sym*o+i' +ang%age

– A 'on0enient too+ $or des'ri*ing the interna+ organi2ation o$ digita+

'omp%ters – Can a+so *e %sed to $a'i+itate the design pro'ess o$ digita+ systems-



DESIGNATI!N !F REGISTERS


• Registers are designated *y 'apita+ +etters3 sometimes$o++o.ed *y n%m*ers 5e-g-3 A3 R1=3 IR6

• !$ten the names indi'ate $%n'tion9 – AR / memory address register

– "C / program 'o%nter

– IR / instr%'tion register

• Registers and their 'ontents 'an *e 0ie.ed and represented invarious ways

– A register 'an *e 0ie.ed as a sing+e entity9

– Registers may a+so *e represented sho.ing the *its o$ data they 'ontain

AR





REGISTER TRANSFER

Register Transfer

• Copying the 'ontents o$ one register to another is a registertrans$er

• A register trans$er is indi'ated as

R8 ← R1

– In this 'ase the 'ontents o$ register R1 are 'opied 5+oaded6 intoregister R8

– A sim%+taneo%s trans$er o$ a++ *its $rom the so%r'e R1 to the

destination register R83 d%ring one '+o' p%+se – Note that this is a non/destr%'ti0e i-e- the 'ontents o$ R1 are not

a+tered *y 'opying 5+oading6 them to R8



REGISTER TRANSFER

Register Transfer

• A register trans$er s%'h as

R= ← R>

Imp+ies that the digita+ system has

– the data +ines $rom the so%r'e register 5R>6 to the destinationregister 5R=6

– "ara++e+ +oad in the destination register 5R=6

– Contro+ +ines to per$orm the a'tion



C!NTR!L F(NCTI!NS

Register Transfer

• !$ten a'tions need to on+y o''%r i$ a 'ertain 'ondition is tr%e

• This is simi+ar to an i$ statement in a programming +ang%age• In digita+ systems3 this is o$ten done 0ia a control signal 3 'a++ed

a control function

– I$ the signa+ is 13 the a'tion taes p+a'e

• This is represented as9

"9 R8 ← R1

4hi'h means i$ " 13 then +oad the 'ontents o$ register R1 intoregister R83 i-e-3 i$ 5" 16 then 5R8

←

R16

R i T f



HARD4ARE I"LEENTATI!N !F C!NTR!LLED TRANSFERS

Imp+ementation o$ 'ontro++ed trans$er

"9 R8 ← R1

&+o' diagram

Timing diagram

C+o'

Register Transfer

Trans$er o''%rs here

R8

R1

Contro+Cir'%it

Load"

n

C+o'

Load

t t1

• The same '+o' 'ontro+s the 'ir'%its that generate the 'ontro+ $%n'tion and the destination register • Registers are ass%med to %se positive-edge-triggered $+ip/$+ops

R i t T f



SI(LTANE!(S !"ERATI!NS

Register Transfer

• I$ t.o or more operations are to o''%r

sim%+taneo%s+y3 they are separated .ith 'ommas

"9 R= ← R>3 AR ← IR

• Here3 i$ the 'ontro+ $%n'tion " 13 +oad the 'ontentso$ R> into R=3 and at the same time 5'+o'63 +oad the'ontents o$ register IR into register AR

R i t T f



&ASIC S)&!LS F!R REGISTER TRANSFERS

Capita+ +etters Denotes a register AR3 R8

n%mera+s"arentheses 56 Denotes a part o$ a register R85@/763 R85L6

Arro.←

Denotes trans$er o$ in$ormation R8←

R1

Co+on 9 Denotes termination o$ 'ontro+ $%n'tion "9

Comma 3 Separates t.o mi'ro/operations A← &3 & ← A

Sym*o+s Des'ription Examp+es

Register Transfer

R i t T f



C!NNECTING REGISTRS

Register Transfer

• In a digita+ system .ith many registers3 it is impra'ti'a+ to

ha0e data and 'ontro+ +ines to dire't+y a++o. ea'h registerto *e +oaded .ith the 'ontents o$ e0ery possi*+e otherregisters

• To 'omp+ete+y 'onne't n registers n5n/16 +ines

• !5n86 'ost – This is not a rea+isti' approa'h to %se in a +arge digita+ system

• Instead3 tae a di$$erent approa'h

• Ha0e one 'entra+i2ed set o$ 'ir'%its $or data trans$er the*%s

• Ha0e 'ontro+ 'ir'%its to se+e't .hi'h register is theso%r'e3 and .hi'h is the destination

Bus and Memory Transfers



&(S AND &(S TRANSFER

&%s is a path5o$ a gro%p o$ .ires6 o0er .hi'h in$ormation is

trans$erred3 $rom any o$ se0era+ so%r'es to any o$ se0era+ destinations-

From a register to *%s9 &(S←

R

1 8 = B 1 8 = B 1 8 = B 1 8 = B

Register A Register & Register C Register D

& C D1 1 1

B x1(J

& C D8 8 8

B x1(J

& C D= = =

B x1(J

& C DB B B

B x1(J

B/+ine *%s

x

yse+e't

@ @ @ @

Register A Register & Register C Register D

&%s +ines





TRANSFER FR! &(S T! A DESTINATI!N REGISTER

Three/State &%s &%$$ers

&%s +ine .ith three/state *%$$ers

Reg- R@ Reg- R1 Reg- R8 Reg- R=

&%s +ines

8 x B

De'oder

Load

D@ D1 D8 D=2

.Se+e't E 5ena*+e6

!%tp%t )A i$ C1High/impeden'e i$ C@

Norma+ inp%t A

Contro+ inp%t C

Se+e't

Ena*+e

@18=

S@

S1

A@&@

C@

D@

&%s +ine $or *it @





&(S TRANSFER IN RTL


• Depending on .hether the *%s is to *e mentionedexp+i'it+y or not3 register trans$er 'an *e indi'ated aseither

or

• In the $ormer 'ase the *%s is imp+i'it3 *%t in the +atter3 it isexp+i'it+y indi'ated

R8←

R1

&(S ← R13 R8 ← &(S




E!R) 5RA6


• emory 5RA6 'an *e tho%ght as a se,%entia+ 'ir'%its'ontaining some n%m*er o$ registers

• These registers ho+d the words o$ memory

• Ea'h o$ the r registers is indi'ated *y an address

• These addresses range $rom @ to r/1

• Ea'h register 5.ord6 'an ho+d n *its o$ data

• Ass%me the RA 'ontains r 8 .ords- It needs the$o++o.ing

– n data inp%t +ines

– n data o%tp%t +ines

– address +ines

– A Read 'ontro+ +ine – A 4rite 'ontro+ +ine

data inp%t +ines

data o%tp%t +ines

n

n

address +ines

Read

4rite

RA%nit




E!R) TRANSFER


• Co++e'ti0e+y3 the memory is 0ie.ed at the register +e0e+ as ade0i'e3 -

• Sin'e it 'ontains m%+tip+e +o'ations3 .e m%st spe'i$y .hi'haddress in memory .e .i++ *e %sing

• This is done *y indexing memory re$eren'es

• emory is %s%a++y a''essed in 'omp%ter systems *yp%tting the desired address in a spe'ia+ register3 theMemory Address Register 5MAR 3 or AR 6

• 4hen memory is a''essed3 the 'ontents o$ the AR getsent to the memory %nit<s address +ines

ARemory

%nit

Read

4rite

Data inData o%t




E!R) READ


• To read a 0a+%e $rom a +o'ation in memory and +oad it intoa register3 the register trans$er +ang%age notation +oos+ie this9

• This 'a%ses the $o++o.ing to o''%r – The 'ontents o$ the AR get sent to the memory address +ines

– A Read 5 16 gets sent to the memory %nit

– The 'ontents o$ the spe'i$ied address are p%t on the memory<s o%tp%tdata +ines

– These get sent o0er the *%s to *e +oaded into register R1

R1←

KAR




E!R) 4RITE


• To .rite a 0a+%e $rom a register to a +o'ation in memory+oos +ie this in register trans$er +ang%age9

• This 'a%ses the $o++o.ing to o''%r – The 'ontents o$ the AR get sent to the memory address +ines

– A 4rite 5 16 gets sent to the memory %nit

– The 0a+%es in register R1 get sent o0er the *%s to the data inp%t +ineso$ the memory

– The 0a+%es get +oaded into the spe'i$ied address in the memory

KAR←

R1




S(AR) !F R- TRANSFER ICR!!"ERATI!NS


A←

& Trans$er 'ontent o$ reg- & into reg- A

AR← DR5AD6 Trans$er 'ontent o$ AD portion o$ reg- DR into reg- AR

A←

'onstant Trans$er a *inary 'onstant into reg- A

A&(S ← R13 Trans$er 'ontent o$ R1 into *%s A and3 at the same time3

R8←

A&(S trans$er 'ontent o$ *%s A into R8

AR Address register DR Data register

KR emory .ord spe'i$ied *y reg- R

E,%i0a+ent to KAR

DR←

emory read operation9 trans$ers 'ontent o$

memory .ord spe'i$ied *y AR into DR ← DR emory write operation9 trans$ers 'ontent o$

DR into memory .ord spe'i$ied *y AR

Arithmetic Microoperations



ICR!!"ERATI!NS

• Comp%ter system mi'rooperations are o$ $o%r types9

/ Register trans$er mi'rooperations

/ Arithmeti' mi'rooperations

/ Logi' mi'rooperations

/ Shi$t mi'rooperations





ARITHETIC ICR!!"ERATI!NS

S%mmary o$ Typi'a+ Arithmeti' i'ro/!perations


R= ← R1 R8 Contents o$ R1 p+%s R8 trans$erred to R=

R= ← R1 / R8 Contents o$ R1 min%s R8 trans$erred to R=

R8←

R8< Comp+ement the 'ontents o$ R8

R8←

R8< 1 8Ms 'omp+ement the 'ontents o$ R8 5negate6

R=←

R1 R8< 1 s%*tra'tion

R1←

R1 1 In'rement

R1←

R1 / 1 De'rement

• The *asi' arithmeti' mi'rooperations are – Addition – S%*tra'tion – In'rement – De'rement

• The additiona+ arithmeti' mi'rooperations are – Add .ith 'arry – S%*tra't .ith *orro. – Trans$erLoad – et'-




&INAR) ADDER S(&TRACT!R INCREENTER

FA

B0 A0

S0

C0FA

B1 A1

S1

C1FA

B2 A2

S2

C2FA

B3 A3

S3

C3

C4

&inary Adder/S%*tra'tor

FA

B0 A0

S0

C0C1FA

B1 A1

S1

C2FA

B2 A2

S2

C3FA

B3 A3

S3C4

M

&inary In'rementer

HA

x y

C S

A0 1

S0

HA

x y

C S

A1

S1

HA

x y

C S

A2

S2

HA

x y

C S

A3

S3C4

&inary Adder





ARITHETIC CIRC(IT

S1S@

@18=

Bx1(J

J@

)@

C@

C1

D@FA

S1S@@18=

Bx1(J

J1

)1

C1

C8

D1FA

S1S@@

18=

Bx1

(J

J8

)8

C8

C=

D8FA

S1S@@18=

Bx1(J

J=

)=

C=

CB

D=FA

Co%t

A@

&@

A1

&1

A8

&8

A=

&=

@ 1

S@S1Cin

S1 S@ Cin ) !%tp%t i'rooperation@ @ @ & D A & Add

@ @ 1 & D A & 1 Add .ith 'arry

@ 1 @ &< D A &< S%*tra't .ith *orro.

@ 1 1 &< D A &< 1 S%*tra't

1 @ @ @ D A Trans$er A

1 @ 1 @ D A 1 In'rement A

1 1 @ 1 D A / 1 De'rement A

1 1 1 1 D A Trans$er A

p

Logic Microoperations



L!GIC ICR!!"ERATI!NS

g p

• Spe'i$y *inary operations on the strings o$ *its in registers

– Logi' mi'rooperations are *it/.ise operations3 i-e-3 they .or on theindi0id%a+ *its o$ data

– %se$%+ $or *it manip%+ations on *inary data

– %se$%+ $or maing +ogi'a+ de'isions *ased on the *it 0a+%e

• There are3 in prin'ip+e3 1 di$$erent +ogi' $%n'tions that 'an*e de$ined o0er t.o *inary inp%t 0aria*+es

• Ho.e0er3 most systems on+y imp+ement $o%r o$ these – AND 5∧63 !R 5∨63 J!R 5⊕63 Comp+ementN!T

• The others 'an *e 'reated $rom 'om*ination o$ these

@ @ @ @ @ 1 1 1@ 1 @ @ @ 1 1 11 @ @ @ 1 @ 1 11 1 @ 1 @ 1 @ 1

A & F@ F1 F8 F1= F1B F1>




LIST !F L!GIC ICR!!"ERATI!NS

• List o$ Logi' i'rooperations

/ 1 di$$erent +ogi' operations .ith 8 *inary 0ars-

/ n *inary 0ars O $%n'tions8 8n

• Tr%th ta*+es $or 1 $%n'tions o$ 8 0aria*+es and the

'orresponding 1 +ogi' mi'ro/operationsBoolean

Function

Micro-

OperationsName

x @ @ 1 1

y @ 1 @ 1

g p

@ @ @ @ F@ @ F ← @ C+ear @ @ @ 1 F1 xy F

←

A∧

& AND@ @ 1 @ F8 xyM F ← A∧ &<@ @ 1 1 F= x F ← A Trans$er A@ 1 @ @ FB xMy F ← A<∧ &@ 1 @ 1 F> y F ← & Trans$er &@ 1 1 @ F x

⊕

y F←

A⊕

& Ex'+%si0e/!R@ 1 1 1 F7 x y F

←

A∨

& !R

1 @ @ @ F? 5x y6M F ←

A ∨ &6< N!R1 @ @ 1 FP 5x ⊕ y6M F ← 5A ⊕ &6< Ex'+%si0e/N!R1 @ 1 @ F1@ yM F ← &< Comp+ement &1 @ 1 1 F11 x yM F ← A ∨ &1 1 @ @ F18 xM F

←

A< Comp+ement A1 1 @ 1 F1= xM y F

←

A<∨

&1 1 1 @ F1B 5xy6M F

←

5A∧

&6< NAND1 1 1 1 F1> 1 F ← a++ 1Ms Set to a++ 1Ms




HARD4ARE I"LEENTATI!N !F L!GIC ICR!!"ERATI!NS

@ @ F A∧

& AND

@ 1 F A ∨ & !R

1 @ F A⊕ & J!R

1 1 F A< Comp+ement

S1 S@ !%tp%t µ/operation F%n'tion ta*+e

g p

&

A

S

S

F

1

@

i

i

i@

1

8

=

B J 1(J

Se+e't




A""LICATI!NS !F L!GIC ICR!!"ERATI!NS

• Logi' mi'rooperations 'an *e %sed to manip%+ate indi0id%a+*its or a portions o$ a .ord in a register

• Consider the data in a register A- In another register3 &3 is *itdata that .i++ *e %sed to modi$y the 'ontents o$ A

– Se+e'ti0e/set A ← A & – Se+e'ti0e/'omp+ement A

←

A⊕

&

– Se+e'ti0e/'+ear A←

A # &<

– as 5De+ete6 A←

A # &

– C+ear A ← A⊕ &

– Insert A ← 5A # &6 C

– Compare A←

A⊕

&

– - - -




SELECTI;E SET

• In a se+e'ti0e set operation3 the *it pattern in & is %sed to set 'ertain *its in A

1 1 @ @ At

1 @ 1 @ &

1 1 1 @ At1 5A←

A &6

• I$ a *it in & is set to 13 that same position in A gets set to 13other.ise that *it in A eeps its pre0io%s 0a+%e




SELECTI;E C!"LEENT

• In a se+e'ti0e 'omp+ement operation3 the *it pattern in & is%sed to complement 'ertain *its in A

1 1 @ @ At

1 @ 1 @ &

@ 1 1 @ At1 5A ← A ⊕ &6

• I$ a *it in & is set to 13 that same position in A gets

'omp+emented $rom its origina+ 0a+%e3 other.ise it is%n'hanged




SELECTI;E CLEAR

• In a se+e'ti0e '+ear operation3 the *it pattern in & is %sed toclear 'ertain *its in A

1 1 @ @ At

1 @ 1 @ &

@ 1 @ @ At1 5A ← A ⋅ &<6

• I$ a *it in & is set to 13 that same position in A gets set to @3

other.ise it is %n'hanged




ASQ !"ERATI!N

• In a mas operation3 the *it pattern in & is %sed to clear 'ertain *its in A

1 1 @ @ At

1 @ 1 @ &

1 @ @ @ At1 5A ← A ⋅ &6

• I$ a *it in & is set to @3 that same position in A gets set to @3

other.ise it is %n'hanged




CLEAR !"ERATI!N

• In a '+ear operation3 i$ the *its in the same position in A and& are the same3 they are '+eared in A3 other.ise they are setin A

1 1 @ @ At

1 @ 1 @ &

@ 1 1 @ At1 5A←

A ⊕ &6




INSERT !"ERATI!N

• An insert operation is %sed to introd%'e a spe'i$i' *it patterninto A register3 +ea0ing the other *it positions %n'hanged

• This is done as

– A mas operation to '+ear the desired *it positions3 $o++o.ed *y

– An !R operation to introd%'e the ne. *its into the desiredpositions

– Examp+e

» S%ppose yo% .anted to introd%'e 1@1@ into the +o. order$o%r *its o$ A9 11@1 1@@@ 1@11 @@@1 A 5!rigina+6

11@1 1@@@ 1@11 1@1@ A 5Desired6

» 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask

1101 1000 1011 0000 A (Intermediate)

0000 0000 0000 1010 Added bits

1101 1000 1011 1010 A (Desired)

hift Microoperations



L!GICAL SHIFT

• In a +ogi'a+ shi$t the seria+ inp%t to the shi$t is a @-

• A right +ogi'a+ shi$t operation9

• A +e$t +ogi'a+ shi$t operation9

• In a Register Trans$er Lang%age3 the $o++o.ing notation is %sed – shl $or a +ogi'a+ shi$t +e$t

– shr $or a +ogi'a+ shi$t right

– Examp+es9

» R8 ← shr R8

» R= ← shl R=

@

@




CIRC(LAR SHIFT

• In a 'ir'%+ar shi$t the seria+ inp%t is the *it that is shi$ted o%t o$the other end o$ the register-

• A right 'ir'%+ar shi$t operation9

• A +e$t 'ir'%+ar shi$t operation9

• In a RTL3 the $o++o.ing notation is %sed – cil $or a 'ir'%+ar shi$t +e$t

– cir $or a 'ir'%+ar shi$t right

– Examp+es9

» R8 ← cir R8

» R= ← cil R=



Logical versus Arithmetic Shift

• A logical shift fills the newly created bit position withzero:

• An arithmetic shift fills the newly created bit position with a copy of the number’s sign bit:




ARITHETIC SHIFT

• An +e$t arithmeti' shi$t operation m%st *e 'he'ed $or theo0er$+o.

@

;Before the shift! if the leftmost two"its differ! the shift will result in anoverflow

• In a RTL3 the $o++o.ing notation is %sed – ashl $or an arithmeti' shi$t +e$t

– ashr $or an arithmeti' shi$t right

– Examp+es9» R8 ← ashr R8

» R= ← ashl R=

sign*it




HARD4ARE I"LEENTATI!N !F SHIFT ICR!!"ERATI!NS

S

@1

H@(J

S

@1

H1(J

S

@1

H8(J

S

@1

H=(J

Se+e't@ $or shi$t right 5do.n61 $or shi$t +e$t 5%p6Seria+

inp%t 5IR6

A@

A1

A8

A=

Seria+inp%t 5IL6




ARITHETIC L!GIC SHIFT (NIT

S= S8 S1 S@ Cin !peration F%n'tion@ @ @ @ @ F A Trans$er A@ @ @ @ 1 F A 1 In'rement A@ @ @ 1 @ F A & Addition@ @ @ 1 1 F A & 1 Add .ith 'arry

@ @ 1 @ @ F A &< S%*tra't .ith *orro.@ @ 1 @ 1 F A &< 1 S%*tra'tion@ @ 1 1 @ F A / 1 De'rement A@ @ 1 1 1 F A Trans$erA@ 1 @ @ J F A∧ & AND@ 1 @ 1 J F A ∨ & !R@ 1 1 @ J F A⊕ & J!R@ 1 1 1 J F A< Comp+ement A1 @ J J J F shr A Shi$t right A into F1 1 J J J F sh+ A Shi$t +e$t A into F

Arithmeti'Cir'%it

Logi'

Cir'%it

C

C B x 1(J

Se+e't

@18=

F

S=S8S1S@

&

A

i

A

D

A

E

shr sh+

i1 i

ii

i1i/1

i

i

H4 7



H4 7

1- (se D/type $+ip $+ops and gates to design a 'o%nter.ith the $o++o.ing repeated *inary se,%en'e9 @3 13 =383 B3 -

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CO-II B.tech (IT)-Notes-register Transfer Lang. & Microoperation-PDF (1)