CN310 Microprocessor Systems Design · A device incorporates most or all of the functions of a central processing unit (CPU) on a single integrated circuit. CN310 Microprocessor Systems

CN310 Microprocessor Systems DesignMicroprocessor Architecture

Nawin Somyat

Department of Electrical and Computer EngineeringThammasat University

Outline

Course Contents1 Introduction2 Simple Computer3 Microprocessor Architecture4 Memory5 Peripherals6 Applications

Outline1 Diagram2 Architecture

Processor CoreMemoryBuses

3 Instruction SetBasicsData AccessControl Flow

CN310 Microprocessor Systems Design 2 / 60

Block Diagram

A graphical representation of principal structure and itsinterconnections, used for a higher level, less detailed description ofthe overall concepts.

Blocks: parts / components / functionsLines: connections / relationshipsThick lines: grouped connectionsArrows: direction of energy / current / signal / data


Block Diagram


Block Diagram


Schematic

A graphical representation of the elements of a system usingabstract, graphic symbols rather than realistic pictures.


Timing Diagram

A graphical representation of the time variation of signals, as wellas the timed relationship between the signals.


What is Microprocessor

A device incorporates most or all of the functions of a centralprocessing unit (CPU) on a single integrated circuit.


What is Microprocessor

An electronic component:Need fixed supply DC voltage (Vcc) and ground (GND).Operations rely on voltage signal.Internal operations are based on transistors.

A digital IC:Operate with respect to clock signal.Interpret voltage level as logic.

A device with constrained electrical properties:Can supply only limited current (sink > source)When interfacing with analog signal, input voltage must notexceed supply voltage.

A device with processing capability: compared with similarprocessor core

More frequency (MHz) means faster computation.Larger data width (8bit < 16bit < 32bit < 64bit) means moredata processing and transfer capability.


Cautions

Microprocessor is built using CMOS technologyLower supply voltage (3.3V,2.5V,1.8V) uses less power, butwill be damaged from 5V circuit.Power loss is proportional to switching frequency.Vulnerable to electrostatic discharge (ESD).

Microprocessor executes code within memory.Memory address must be aligned with instruction/data width.

Microprocessor selection may need to concern regulations.Thermal properties: operating temperature, heat dissipation.Electromagnetic properties: EMC.Production requirements: lead-free, RoHS.


Processor Core

A microprocessor is a programmable chip that is used for executinginstructions to process data or control other devices.


Processor Core

Control Unit: manage sequence of processing, e.g.Fetch and execute instructions.Move data among memory locations.Branch to separate instruction based on decisions.

Arithematic and Logic Unit: perform mathematical andlogical operations, e.g.

Addition, subtraction, multiplication, and divisionAND, OR, XOR, and shift operations.

Registers and Flags:Instruction register/decoder:Program counter (PC): memory address of next instruction

Memory bus: path to access memory


Processor Core: Example


Processor Core: Example ARM


Processor Core: Example AVR


Processor Core: Example Core 2


Concepts

Instruction = what to do!Register = temporary memoryData = intermediate (constant) or reference(register/memory)Memory = place of code (ROM) or data (RAM)Address = location in memory of code/data


Architecture

Fundamental operational structure of processor core fromprogramming viewpoint

Instruction setRegistersData typesAddressing modesMemory architectureInterrupt and exception handlingExternal I/O


Instruction Set

An instruction set is a list of all the opcodes (machine language)that a processor can execute.

instruction = opcode + operands


Instruction Set

Registers for arithmetic, addressing, or control functionsMemory locations or offsetsOperands referred by addressing modes

Arithmetic instructions, e.g. add, subtractLogic instructions, e.g. and, or, notData instructions, e.g. move, input, output, load, storeControl flow instructions, e.g. goto, if-goto, call, returnSpecial instructions, e.g. test-and-set, vector/floating-point


Instruction set

Other than their functions, instructions may be grouped based onthe number of operands.

0-operand (stack machines): arithmetic operations use datafrom stack.push a; push b; add; pop c;

1-operand (accumulator machines): specify an operand(register, mem location, constant) with implicit accumulatorload a; add b; store c;

2-operand:load a,reg1; load b,reg2; add reg1,reg2;

3-operand: complex operations or addressing modesCISC = move a,reg1; add reg1,b,c;RISC = load a,reg1; add reg1,reg2,reg3;(add reg1+reg2 -> reg3)

more operands:


Registers and Flags

Registers are limited internal storage within microprocessor, fastestto access from MPU side.

Used as temporary storage for execution input and outputIndicate the execution capability of instruction/data, e.g. 8bit,16bit, 32bit, 64bitReflect the size of word, group of bits that processor canhandle in one operation

Flags refer to one or more bits within a register, that store a binaryvalue representing a specific meaning


Registers and Flags

Instruction registers stores the instruction currently beingexecuted or decodedGeneral purpose registers hold data/address values

Data registers hold numeric valuesAddress registers hold index values for memory addressing

Control and status registers include program counter, stackpointer, and status registerConditional registers hold enable/disable conditions forspecific instructionsSpecial purpose registers store program stateHardware registers contain bits of hardware state.Some architectures include additional registers, e.g. floatingpoint registers, vector registers


AVR Registers

AVR architecture uses fast-accessregister file containing 32 x 8-bitregisters.

Single clock cycle access timeSixteen 16-bit addressable units


AVR Status Register

Status Register (SREG) is updated after all arithmetic and logicalinstructions, containing a set of status flags:

I: Global Interrupt EnableH: Half Carry FlagV: Twos Complement Overflow FlagZ: Zero Flag

T: Bit Copy StorageS: Sign BitN: Negative FlagC: Carry Flag


Memory Models

Memory model is the way that processor can reference to an entityin memory.

Flat memory model: single space up to 2n

Simple, efficient for single task.Not appropriate for multitasking OS (required MMU)

Paged memory model: multiple pages, each page up to 2n

Suitable for multitasking environmentHarder for low-level management

Segmented memory model: combined segment:offsetMore efficient due to variable page boundariesMore difficult for compilers


Memory Map

A memory map is a representation of memory layout for storingcode and data.

Program codeInternal or external flash memory

Read/write memory

Internal or external RAMHardware registers mapping


Harvard Architecture

Harvard → code and data use separate memory space.


von Neumann Architecture

von Neumann → code and data use shared memory space.


Cache Memory

CPU cache is a smaller, faster memory used by CPU to reduce theaverage time to access system memory.

Cache stores copies of frequently usedcode/data in main memoryModern processors integrate threetypes of cache

Instruction cache to speed upexecutable instruction fetch.Data cache to speed up data fetchand store.Translation lookaside buffer to speedup virtual-to-physical addresstranslation

Efficiency depends on hit/miss ratio


Architecture Classification

Instruction Set:Complex Instuction Set Computer (CISC): limitedaccumulators, complex instruction set, various addressingmodes.

Aim for 1 processing/1 instruction = small code size

Reduced Instruction Set Computer (RISC): general-purposeregisters, simple instruction set, limited addressing modes,load-store execution

Aim for 1 clock/1 instruction = better MIPSOthers: DSP, VLIW, . . .

Word size: 8 / 16 / 32 / 64 bitMemory space: program and data.

von Neumann architecture: share address space.Harvard architecture: separate address space.


Questions

What architecture typesof AVR coreHow many registers inAVR coreWhat is word length ofAVR coreHow large memory can beaddressedHow many addressingmodes AVR core support


Processor Bus

Processor bus is a subsystem that transfers data betweencomponents inside a microprocessor.

Data bus: transport data to/from memoryAddress bus: provide address of memory locationsControl bus: control devices on bus

There are different type of processor buses

System bus or memory bus:CPU ↔main memoryPeripheral bus or I/O bus:bridge ↔ peripheral devices


Bus Addressing & Timing

Processor core accesses to code and data in memory using asequence of signals from address/data/control buses.

Generate and hold address valueon address bus

Some address bits may beused for memory chipselection

Assert Read/Write signal fromcontrol busAccess data via data bus


System and Peripheral Clocks

Microprocessor components are digital logics which operate w.r.t.clock signals.

Clock source may be external or internal oscillatorPLL (phase-locked-loop) multiplies clock frequency

Use low-frequency oscillatorPrescalar divides clock frequency

Peripheral devicesLower-speed devices


System and Peripheral Clocks: Example AVR


System and Peripheral Clocks

Clock source can be selected via I/O register

Changing clock source requires time to stabilize frequencyAdjusting clock frequency makes trade-off between processingpower and power consumption


Computer Buses

Computer buses cover data pathway among CPU, mainboardchipset, and external devices.

Northbridge or memory controller hub: front-side busMemory (RAM)Highspeed graphics subsystem

Southbridge or I/O controller hub:PCI bus = standardized bus for expansion cardsSATA and IDE = hard disk driveSPI bus = flash BIOS, SMBus = batteryUSB bus


Computer Buses: Example


Instruction Set

An instruction set is a list of all the opcodes (machine language)that a processor can execute.

Arithmetic instructions, e.g. add, subtractLogic instructions, e.g. and, or, notData instructions, e.g. move, input, output, load, storeControl flow instructions, e.g. goto, if-goto, call, returnSpecial instructions, e.g. test-and-set, vector/floating-point

Programming env. at level of machine instructions includes

Data typesAddressing mode

Execution statusInstruction timing


Instruction Cycle

Fetch-and-Execute cycle is a sequence where instructions arefetched from memory, then executed.

1 Fetch the instruction at PC into instruction register:IR ← [PC]

2 Decode the instruction and increment PC:PC ← PC + n

3 Fetch operands from memory (instruction with indirectaddress)

4 Execute the instruction by control unit or ALU5 Store result to memory


Execution Timing

The Parallel Instruction Fetches and Instruction Executions

Single Cycle ALU Operation


Accumulator Architecture

CISC processors have limited accumulators, complex instructions,orthogonal addressing modes.

Load data into accumulator.Execute instructions with additional data from memory.Store results into memory.


RISC Architecture

RISC processors have many working registers, simple addressingmodes, memory access via load/store instructions.

Load data from memory into registersExecute instructions using registersStore results into memory


ALU-Related Instructions

Basic arithematic and logic instructions that almost ALUs canperform:

Integer arithmetic operations: addition, subtraction,multiplication, divisionBitwise logic operations: AND, NOT, OR, XORBit-shifting operations: to the left or right, with or withoutsign extension

Shifts can be interpreted as multiplications by 2 and divisions by 2.Additional complex ALU operations are optional for the design ofinstruction set architecture.

Floating-point calculation is handled by FPU, not ALU.


Binary Representation

Two’s complement of a binary number is the value obtained bysubtracting the number from 2n.

−1 = 28(100000000)− 1(00000001) = 11111111

Encode negative numbers into ordinary binary without specialcircuit to handle signed computationRepresent number in the range −2n−1 to +2n−1 − 1

binary base-10 binary base-100111 1111 127 1111 1111 -10111 1110 126 1111 1110 -20000 0001 1 1000 0001 -1270000 0000 0 1000 0000 -128


Machine Data Size

Processor core view machine data types according to therelationship between instructions and registers/flags.

Bit: 0 or 1Each flag in conditional registers can be accessed via specificinstructionsA few processor cores can access general purpose registers atbit level

Byte: an octet (8-bit)Similar to word for 8-bit processorsNeed downsizing for 16-/32-/64-bit processors

Word: word length equals the size of registersSome processors support instructions that handle operandswith 2 words or more


Machine Data Types

Programming data types are translated at compiler level intomachine data types

Boolean, char, integer types are treated as word-length dataFloating-point value is handled by software or co-processor

Integer processing is the fastest since it is word-alignedFloating-point processing is the slowest if no co-processorArithematic operations based on native instructions, e.g. add,shift, are faster

In C language, integer promotion rules are applied for thecomputation of char/integer/long data


Status Register

Status register refers to a group of registers containing flags (bits)showing the status of microprocessor and execution result. Typicalstatuses include:

Carry Flag = result has carry from arithemetic operationZero Flag = result is zeroNegative Flag = result is negativeOverflow Flag = result is overflowParity Flag = result is odd or even’Interrupt Enable Flag = flag to enable/disable interruptTrap Flag = trap condition occurs w.r.t. execution result

Some instructions can manipulate these flags directly, orexecute according to their value.


Data Instructions

The movement of data between processor and external devices ishandled via the control unit through processor bus.

Set register to a constant value.Move data among registers and memory locations: copy,move, load, store.Read and write data with hardware devices: in, out.

Flexibility of referencing memory locations allow processor tohandle data transfer easier → addressing mode.


Addressing Modes

Addressing mode specifies how to calculate the effective memoryaddress of an operand by using information held in registers and/orconstants.

Register: operand is in the registerImmediate: operand is in the instruction itselfDirect: address of operand is in the instructionRegister Direct: address of operand is in the given registerBase Displacement: address is the sum of register content anda constantIndirect: instruction have address, the contents at the addressis the address of the operandRegister Indirect: register contains address, the contents atthe address is the address of the operand


Addressing Modes

Addressing modes for codeDirect: jump addrRegister Direct: jump regBase Displacement: jump offset

Addressing modes for dataDirect: load reg,addrBase Displacement: load reg,base,offset


Addressing Modes: Examples

Direct Data Addressing


Addressing Modes: Examples

Indirect Data Addressing with Displacement


Control Flow Instructions

Jumping (unconditional) or Branching (conditional) is the abilityto load the PC register with a new address that is not the nextsequential address.⇒ executing these instructions alters the flow of software.

Jump instructions:Absolute: local or longRelative

Branch instructions:Status register’s flagsComparison result

Subroutine instructions:Call and returnSoftware traps


Control Flow Instructions: Branch Instructions


Subroutine Call

A subroutine is a group of instructions that will be used repeatedlyin different locations of the program.⇒ basis of function call in high-level language.

CALL instruction: redirect the execution to the subroutineRET insutruction: return the execution to the calling routine

To return after subroutine ends, how processor can rememberits code address and execution state.


Stack

Processor stack is a memory portion used as temporary storageduring execution.

Stack operation is based onlast-in, first-out mechanism

Push register into stackPop top stack to register

Stack is always used for savingstatus and passing argumentsPC, status registers, workingregisters

PC, calling argumentsReturn value


Stack: Frame

Stack pointer (SP) is thememory address of stack lastdata

Kept by stack pointer registerEither increase or decrease,depend on processor

Stack overflow is the problem ofpushing too much data intostack


Stack: Subroutine

Hardware level: PC and SREG are saved by default.Software level: required registers by PUSH instruction.High-level language: all registers before each function call.


Documents

CN310 Microprocessor Systems Design · A device incorporates most or all of the functions of a central processing unit (CPU) on a single integrated circuit. CN310 Microprocessor Systems