CMSC 313 Preview Slideschang/cs313.f12/topics/Preview26.pdf · CMSC 313 Preview Slides These are draft slides. The actual slides presented in lecture may be different due to last

CMSC 313 Preview Slides

These are draft slides.

The actual slides presented in lecture may be different

due to last minute changes, schedule slippage, ...

UMBC, CMSC313, Richard Chang <[email protected]>

CMSC 313 Lecture 20

• Introduction to Circuit Simplification

• Karnaugh Map examples• Quine-McCluskey (Tabular Reduction)


Appendix B: Reduction of Digital LogicB-3

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring

Reduction (Simplification) of BooleanExpressions

• It is usually possible to simplify the canonical SOP (or POS)forms.

• A smaller Boolean equation generally translates to a lower gatecount in the target circuit.

• We cover three methods: algebraic reduction, Karnaugh map re-duction, and tabular (Quine-McCluskey) reduction.



Karnaugh Maps: Venn Diagram Rep-resentation of Majority Function

• Each distinct region in the “Universe” represents a minterm.• This diagram can be transformed into a Karnaugh Map.

ABC

ABC’ AB’CAB’C’

A’BC

A’BC’ A’B’C

A’B’C’B

A

C



K-Map for Majority Function• Place a “1” in each cell that corresponds to that minterm.• Cells on the outer edge of the map “wrap around”

A B C FMintermIndex

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

01234567

1

0

0-side 1-side

0

A balance tips to the left or right depending on whether

there are more 0’s or 1’s.

00 01 11 10

0

1

ABC

1

11 1



Adjacency Groupings for MajorityFunction

• F = BC + AC + AB

00 01 11 10

0

1

ABC

1

11 1



Minimized AND-OR Majority Circuit

• F = BC + AC + AB• The K-map approach yields the same minimal two-level form as

the algebraic approach.

F

A B C



K-Map Groupings• Minimal grouping is on the left, non-minimal (but logically equiva-

lent) grouping is on the right.• To obtain minimal grouping, create smallest groups first.

00 01 11

1

01

11

11

10AB

1

CD

10

00

01 11

01

11

10CD

10

00

00AB

1

1

1

1

1

2

3

4

1

11

1

1

1

1

1

2

4

51

F = A B C + A C D + A B C + A C D

F = B D + A B C + A C D + A B C + A C D

3

Richard Chang

Example Requiring More Rules

0000

1100

01

00

10

11

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10




K-Map Corners are Logically Adjacent

00 01 11

1

1

1

01

11

1

1

1

1

1

10AB

1

CD

00

10

F = B C D + B D + A B



K-Maps and Don’t Cares• There can be more than one minimal grouping, as a result of

don’t cares.

00 01 11

1

01

11

11

10AB

1

CD

10 d

00 d

F = B C D + B D

01 11

1

01

11

11

10

1

CD

10 d

00 d

00AB

F = A B D + B D

1 1

Gray Code

• Two bits: 00, 01, 11, 10

• Three bits: 000, 001, 011, 010, 110, 111, 101, 100• Successive bit patterns only differ at 1 position

• For Karnaugh maps, adjacent 1’s represent minterms that can be simplified using the rule: ABC’ + A’BC’ = (A + A’)BC’ = 1 BC’ = BC’

00 01 11 10

0

1

ABC 11

A

B

1 1


Karnaugh Maps

Implicant: rectangle with 1, 2, 4, 8, 16 ... 1’s

Prime Implicant: an implicant that cannot be extended into a larger implicant

Essential Prime Implicant: the only prime implicant that covers some 1

K-map Algorithm (not from M&H):

1. Find ALL the prime implicants. Be sure to check every 1 and to use don’t cares.

2. Include all essential prime implicants.

3. Try all possibilities to find the minimum cover for the remaining 1’s.


K-map Example

1010

0dd0

11

10

10

1d

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C

1010

0dd0

11

10

10

1d

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

A’B + AC’D + AB’D’


Notes on K-maps

• Also works for POS

• Takes 2n time for formulas with n variables

• Only optimizes two-level logicReduces number of terms, then number of literals in each term

• Assumes inverters are free

• Does not consider minimizations across functions• Circuit minimization is generally a hard problem

• Quine-McCluskey can be used with more variables

• CAD tools are available if you are serious


Karnaugh Maps

Implicant: rectangle with 1, 2, 4, 8, 16 ... 1’s

Prime Implicant: an implicant that cannot be extended into a larger implicant

Essential Prime Implicant: the only prime implicant that covers some 1

K-map Algorithm (not from M&H):

1. Find ALL the prime implicants. Be sure to check every 1 and to use don’t cares.

2. Include all essential prime implicants.

3. Try all possibilities to find the minimum cover for the remaining 1’s.


Notes on K-maps

• Also works for POS

• Takes 2n time for formulas with n variables

• Only optimizes two-level logicReduces number of terms, then number of literals in each term

• Assumes inverters are free

• Does not consider minimizations across functions• Circuit minimization is generally a hard problem

• Quine-McCluskey can be used with more variables

• CAD tools are available if you are serious


Circuit Minimization is Hard

• Unix systems store passwords in encrypted form.User types in x, system computes f(x) and looks for f(x) in a file.

• Suppose we us 64-bit passwords and I want to find the password x, such that f(x) = y. Let gi(x) = 0 if f(x) = y and the ith bit of x is 0 1 otherwise.

• If the ith bit of x is 1, then gi(x) outputs 1 for every x and has a very, very simple circuit.

• If you can simplify every circuit quickly, then you can crack passwords quickly.




3-Level Majority Circuit• K-Map Reduction results in a reduced two-level circuit (that is,

AND followed by OR. Inverters are not included in the two-levelcount). Algebraic reduction can result in multi-level circuits witheven fewer logic gates and fewer inputs to the logic gates.

M

A B C

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C



Five-Variable K-Map• Visualize two 4-variable K-maps stacked one on top of the other;

groupings are made in three dimensional cubes.

01 11

001

011

10CDE

010

000

00AB

01 11

101

111

10CDE

110

100

00AB

1 1

1 1

1 11 1

1 1

11

F = A C D E + A B D E + B E



Six-Variable K-Map• Visualize four 4-variable K-maps stacked one on top of the other;

groupings are made in three dimensional cubes.

001 011

001

011

010DEF

010

000

000ABC

001 011

101

111

010DEF

110

100

000ABC

101 111

001

011

110DEF

010

000

100ABC

101 111

101

111

110DEF

110

100

100ABC

1

11

1

1

1 1

1

G = B C E F + A B D E



Truth Table with Don’t Cares• A truth table repre-

sentation of a singlefunction with don’tcares.

0011001100110011

0101010101010101

C D

0000111100001111

B

d1010111001d010d

F

0000000011111111

A



Tabular (Quine-McCluskey) Reduction• Tabular reduction be-

gins by groupingminterms for which Fis nonzero accordingto the number of 1’s ineach minterm. Don’tcares are consideredto be nonzero.

• The next step forms aconsensus (the logicalform of a cross prod-uct) between each pairof adjacent groups forall terms that differ inonly one variable.

0010111101

0111001111

C D

0001101011

B

0000010111

A

√ √ √ √ √ √ √ √ √ √

0_011_01111_

_111111__111

C D

00__011101_1

B

0000_0_01_11

A

*√ √ √ √ √ √ **√ √ √

_1_

111

C D

__1

B

0__

A

***

Initial setup After firstreduction

After secondreduction

(a)

(b)

(c)



Table of Choice• The prime implicants form a set that completely covers the func-

tion, although not necessarily minimally.• A table of choice is used to obtain a minimal cover set.

0

0

1

0

_

_

0

1

0

_

_

1

0

1

1

_

1

_

_

_

_

1

1

1

0001 0011 0101 0110 0111 1010 1101

MintermsPrimeImplicants

√

√

√

√

√ √ √ √

√ √

√ √ √

*

*

*



Reduced Table of Choice• In a reduced table of choice, the essential prime implicants and

the minterms they cover are removed, producing the eligible set.• F = ABC + ABC + BD + AD

0

0

_

0

_

_

0

_

1

_

1

1

0001 0011

MintermsEligibleSet

√

√

Set 10 0 0 __ _ 1 1

Set 20 _ _ 1

X

Y

Z √

√



Multiple Output Truth Table• The power of tabular reduction comes into play for multiple func-

tions, in which minterms can be shared among the functions.

00110011

01010101

B C

00001111

A

10010001

F0

01011011

F1

00110011

F2

m0m1m2m3m4m5m6m7

Minterm



Multiple Output Table of ChoiceF0(A,B,C) = ABC + BCF1(A,B,C) = AC + AC + BCF2(A,B,C) = B

0

0

1

_

1

_

0

_

_

1

1

1

0

1

0

_

_

1

PrimeImplicants

√

m0 m3 m7 m1 m3 m4 m6 m7 m2 m3 m6 m7

F0(A,B,C) F1(A,B,C) F2(A,B,C)Min-terms

F0

F1

F1

F2

F1,2

F0,1,2

√ √

√ √

√ √ √ √

√ √

√ √ √ √ √ √

*

*

*

*

*

√ √

Simplifying Finite State Machines

• State Reduction: equivalent FSM with fewer states

• State Assignment: choose an assignment of bit patterns to states (e.g., B is 010) that results in a smaller circuit

• Choice of flip-flops: use D flip-flops, J-K flip-flops or a T flip-flops? a good choice could lead to simpler circuits.




The State Assignment Problem• Two state assignments for machine M2.

P.S.

Input X0 1

A B/1 A/1B C/0 D/1C C/0 D/0D B/1 A/0

Machine M2

Input X0 1

A: 00 01/1 00/1B: 01 10/0 11/1C: 10 10/0 11/0D: 11 01/1 00/0

State assignment SA0

S0S1

Input X0 1

A: 00 01/1 00/1B: 01 11/0 10/1C: 11 11/0 10/0D: 10 01/1 00/0

State assignment SA1

S0S1



State Assignment SA0• Boolean equations for machine M2 using state assignment SA0.

01

11

1

10

X0

00S0S1

1 1

11

01

11

1

10

000 1

1

1

1

XS0S1

01

11

1

10

000 1 1

1

1

XS0S1

S0 = S0S1 + S0S1 Z = S0S1 + S0X+ S0S1X

S1 = S0S1X + S0S1X+ S0S1X + S0S1X



State Assignment SA1• Boolean equations for machine M2 using state assignment SA1.

01

11

1

10

X0

00S0S1

1 1

11

01

11

1

10

000 1

1

1

1

XS0S1

01

11

1

10

00

X

1 1

1

1

S0S10

S1 = XS0 = S1 Z = S1X + S0X

State Assignment Heuristics

• No known efficient alg. for best state assignment

• Some heuristics (rules of thumb):The initial state should be simple to reset — all zeroes or all ones.

Minimize the number of state variables that change on each transition.

Maximize the number of state variables that don't change on each transition.

Exploit symmetries in the state diagram.

If there are unused states (when the number of states s is not a power of 2), choose the unused state variable combinations carefully. (Don't just use the first s combination of state variables.)

Decompose the set of state variables into bits or fields that have well-defined meaning with respect to the input or output behavior.

Consider using more than the minimum number of states to achieve the objectives above.




Sequence Detector State TransitionDiagram

A

B0/0

1/0C

D

E

F

G

0/0

1/0

0/0

1/0

0/0

1/0

1/0

1/1

0/01/1

0/0

0/1

Input: 0 1 1 0 1 1 1 0 0Output: 0 0 1 1 1 1 0 1 0Time: 0 1 2 3 4 5 6 7 8



Sequence Detector State Table

X0 1

A B/0 C/0

Present state

Input

BCDE

D/0 E/0F/0 G/0D/0 E/0F/0 G/1

F D/0 E/1G F/1 G/0

Sequence Detector State Reduction Table

x

xx

xx

xxx

xx

xxx

F

E

FE

x

x

xx

xxx

G

D

C

B

A

GDCBA




Sequence Detector Reduced StateTable

X0 1

B'/0 C'/0

Present state

Input

B'/0 D'/0E'/0 F'/0E'/0 F'/1B'/0 D'/1E'/1 F'/0

A: A'BD: B'

C: C'E: D'F: E'G: F'

UMBC, CMSC 313, Richard Chang <[email protected]>

A

B/D

C

E

F

G

0/10/0

0/00/0

0/0

0/0

1/0

1/0

1/0

1/1

1/1

6-State Sequence Detector



Sequence Detector State Assignment

X0 1

A': 000 001/0 010/0

Present state

Input

B': 001C': 010D': 011E': 100

001/0 011/0100/0 101/0100/0 101/1001/0 011/1

F': 101 100/1 101/0

S2S1S0 S2S1S0Z S2S1S0Z



Sequence Detector K-Maps

• K-map re-duction ofnext stateand outputfunctions forsequencedetector.

01

11

10

00S0X

1

1

1

1

01 11 10

d

d

d

d

1

1

1

1

00S2S1

01

11

10

00S0X

1

1

01 11 10

d

d

d

d

1

00S2S1

01

11

10

00S0X

1

1 1

10

d

d

d

d

00S2S1

01

11

10

00S0X

1

01 11 10

d

d

d

d

1

1

00S2S1

01 11

S0 = S2S1X + S0X+ S2S0 + S1X

S1 = S2S1X + S2S0X

Z = S2S0X + S1S0X + S2S0X

11

1

S2 = S2S0 + S1

Improved Sequence Detector?

• Formulas from the 7-state FSM: __ s2’= (s0 + x)(s2 + s1 + s0) __ _s1’= s0 x + s0 x = s0 xor x _ s0’= x __ _ z = s2 s1 x + s2 s1 x

• Formulas from the 6-state FSM: s2’= s2 s0 + s1 __ __ __ s1’= s2 s1 x + s2 s0 x __ __ _ __s0’= s2 s1 x + s0 x + s2 s0 + s1 x __ _ z = s2 s0 x + s1 s0 x + s2 s0 x


Sequence Detector State Assignment7-state new 6-state

s2 s1 s0 x s2' s1' s0' z0 0 0 0 0 0 0 1 01 0 0 0 1 0 1 0 02 0 0 1 0 0 1 1 03 0 0 1 1 1 0 0 04 0 1 0 0 1 0 1 05 0 1 0 1 1 1 0 06 0 1 1 0 0 1 1 07 0 1 1 1 1 0 0 08 1 0 0 0 1 0 1 09 1 0 0 1 1 1 0 1

10 1 0 1 0 0 1 1 011 1 0 1 1 1 0 0 112 1 1 0 0 1 0 1 113 1 1 0 1 1 1 0 014 1 1 1 0 d d d d15 1 1 1 1 d d d d

s2 s1 s0 x s2' s1' s0' z0 0 0 0 0 0 0 1 01 0 0 0 1 0 1 0 02 0 0 1 0 0 0 1 03 0 0 1 1 1 0 0 04 0 1 0 0 1 0 1 05 0 1 0 1 1 1 0 06 0 1 1 0 d d d d7 0 1 1 1 d d d d8 1 0 0 0 1 0 1 09 1 0 0 1 1 1 0 1

10 1 0 1 0 0 0 1 011 1 0 1 1 1 0 0 112 1 1 0 0 1 0 1 113 1 1 0 1 1 1 0 014 1 1 1 0 d d d d15 1 1 1 1 d d d d

A = 000 E = 100 B = 001 F = 101 C = 010 G = 110 D = 011

A = 000 E = 100B/D = 001 F = 101 C = 010 G = 110 D = 011


6-State Sequence Detector7-state new 6-state

0d00

1d11

11

11

10

10

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

0dd0

1dd1

11

11

10

10

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

__ __s2’= (s0 + x)(s2 + s1 + s0) s2’= (s0 + x)(s2 + s1 + s0)



1

d

d11

1111

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

d

0

d

dd0

1111

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

__ _ __s1’= s0 x + s0 x s1’= s0 x



1111

1

d

d11

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

d

1111

1

d

dd1

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

_ _s0’ = x s0’ = x



1

1

1

d

d

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

d

d 1

1

1

d

d

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

__ _ __ _z = s2 s1 x + s2 s1 x z = s2 s1 x + s2 s1 x


Improved Sequence Detector

• Textbook formulas for the 6-state FSM: s2’= s2 s0 + s1 __ __ __ s1’= s2 s1 x + s2 s0 x __ __ _ __s0’= s2 s1 x + s0 x + s2 s0 + s1 x __ _ z = s2 s0 x + s1 s0 x + s2 s0 x

• New formulas for the 6-state FSM: __ s2’= (s0 + x)(s2 + s1 + s0) __s1’= s0 x _ s0’= x __ _ z = s2 s1 x + s2 s1 x




Excitation Tables• Each table

shows the set-tings that mustbe applied at theinputs at time tin order tochange the out-puts at time t+1.

0011

0101

Qt Qt+1 S

0100

R

0010

S-Rflip-flop

0011

0101

Qt Qt+1 D

0101

Dflip-flop

0011

0101

Qt Qt+1 J

01dd

K

dd10

J-Kflip-flop

0011

0101

Qt Qt+1 T

0110

Tflip-flop



Serial Adder

SerialAdder

0 1 1 0 00 1 1 1 0

1 1 0 1 0XY

Z

Cin Cout

4 3 2 1 04 3 2 1 0 Time (t)Time (t)

A B00/0

01/1

10/1

11/0

00/1

10/0

01/0

11/1

No carrystate

Carry state

xi yi

zi

Presentstate (St)

Input XY00 01 10 11

A:0 0/0 0/1 0/1 1/0B:1 0/1 1/0 1/0 1/1

Present state

Input XY00 01 10 11

A A/0 A/1 A/1 B/0B A/1 B/0 B/0 B/1

Next state Output

• State transi-tion diagram,state table,and state as-signment fora serial adder.



Serial Adder Next-State Functions• Truth table showing next-state functions for a serial adder for D,

S-R, T, and J-K flip-flops. Shaded functions are used in the ex-ample.

00110011

01010101

Y St

00001111

X

00010111

D

00000010

S

01000000

R

0d0d0d1d

J

d1d0d0d0

K

01000010

T

01101001

Z

Present State (Set) (Reset)



J-K Flip-Flop Serial Adder Circuit

CLKQJ

X

Y

Q

XY

Y

X

Z

SKX

Y



D Flip-Flop Serial Adder Circuit

CLK

QD

X

Y

Q

XY

Y

X

Z

SX

Y



Sequence Detector State TransitionDiagram

A

B0/0

1/0C

D

E

F

G

0/0

1/0

0/0

1/0

0/0

1/0

1/0

1/1

0/01/1

0/0

0/1

Input: 0 1 1 0 1 1 1 0 0Output: 0 0 1 1 1 1 0 1 0Time: 0 1 2 3 4 5 6 7 8

UMBC, CMSC 313, Richard Chang <[email protected]>

A

B/D

C

E

F

G

0/10/0

0/00/0

0/0

0/0

1/0

1/0

1/0

1/1

1/1


Improved Sequence Detector?

• Formulas from the 7-state FSM: __ s2’= (s0 + x)(s2 + s1 + s0) __ _s1’= s0 x + s0 x = s0 xor x _ s0’= x __ _ z = s2 s1 x + s2 s1 x

• Formulas from the 6-state FSM: s2’= s2 s0 + s1 __ __ __ s1’= s2 s1 x + s2 s0 x __ __ _ __s0’= s2 s1 x + s0 x + s2 s0 + s1 x __ _ z = s2 s0 x + s1 s0 x + s2 s0 x


Sequence Detector State Assignment7-state new 6-state

s2 s1 s0 x s2' s1' s0' z0 0 0 0 0 0 0 1 01 0 0 0 1 0 1 0 02 0 0 1 0 0 1 1 03 0 0 1 1 1 0 0 04 0 1 0 0 1 0 1 05 0 1 0 1 1 1 0 06 0 1 1 0 0 1 1 07 0 1 1 1 1 0 0 08 1 0 0 0 1 0 1 09 1 0 0 1 1 1 0 1

10 1 0 1 0 0 1 1 011 1 0 1 1 1 0 0 112 1 1 0 0 1 0 1 113 1 1 0 1 1 1 0 014 1 1 1 0 d d d d15 1 1 1 1 d d d d

s2 s1 s0 x s2' s1' s0' z0 0 0 0 0 0 0 1 01 0 0 0 1 0 1 0 02 0 0 1 0 0 0 1 03 0 0 1 1 1 0 0 04 0 1 0 0 1 0 1 05 0 1 0 1 1 1 0 06 0 1 1 0 d d d d7 0 1 1 1 d d d d8 1 0 0 0 1 0 1 09 1 0 0 1 1 1 0 1

10 1 0 1 0 0 0 1 011 1 0 1 1 1 0 0 112 1 1 0 0 1 0 1 113 1 1 0 1 1 1 0 014 1 1 1 0 d d d d15 1 1 1 1 d d d d

A = 000 E = 100 B = 001 F = 101 C = 010 G = 110 D = 011

A = 000 E = 100B/D = 001 F = 101 C = 010 G = 110 D = 011



• Textbook formulas for the 6-state FSM: s2’= s2 s0 + s1 __ __ __ s1’= s2 s1 x + s2 s0 x __ __ _ __s0’= s2 s1 x + s0 x + s2 s0 + s1 x __ _ z = s2 s0 x + s1 s0 x + s2 s0 x

• New formulas for the 6-state FSM: __ s2’= (s0 + x)(s2 + s1 + s0) __s1’= s0 x _ s0’= x __ _ z = s2 s1 x + s2 s1 x



Q Q' J K

0 0 0 d

0 1 1 d

1 0 d 1

1 1 d 0

s2 s1 s0 x s2' s1' s0' z j2 k2 j1 k1 j0 k0

0 0 0 0 0 0 0 1 0 0 d 0 d 1 d

1 0 0 0 1 0 1 0 0 0 d 1 d 0 d

2 0 0 1 0 0 0 1 0 0 d 0 d d 0

3 0 0 1 1 1 0 0 0 1 d 0 d d 1

4 0 1 0 0 1 0 1 0 1 d d 1 1 d

5 0 1 0 1 1 1 0 0 1 d d 0 0 d

6 0 1 1 0 d d d d d d d d d d

7 0 1 1 1 d d d d d d d d d d

8 1 0 0 0 1 0 1 0 d 0 0 d 1 d

9 1 0 0 1 1 1 0 1 d 0 1 d 0 d

10 1 0 1 0 0 0 1 0 d 1 0 d d 0

11 1 0 1 1 1 0 0 1 d 0 0 d d 1

12 1 1 0 0 1 0 1 1 d 0 d 1 1 d

13 1 1 0 1 1 1 0 0 d 0 d 0 0 d

14 1 1 1 0 d d d d d d d d d d

15 1 1 1 1 d d d d d d d d d d


6-State Sequence DetectorJ2 K2

ddd0

ddd1

dd

dd

10

10

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

1ddd

0ddd

00

00

dd

dd

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

_J2 = s1 + s0 x K2 = s0 x



0dd0

0dd0

1d

0d

d1

d0

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

dddd

dddd

d0

d1

0d

1d

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

__ _J1 = s0 x K1 = x



dddd

dddd

00

11

00

11

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

0dd0

1dd1

dd

dd

dd

dd

00 01 11 10

00

01

11

10

s2 s111

s2

s1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

s0 x

s0

x

_J0 = x K0 = x



• Formulas for the 6-state FSM with D Flip-flops: __ s2’= (s0 + x)(s2 + s1 + s0) __s1’= s0 x _ s0’= x

• Formulas for the 6-state FSM with J-K Flip-flops: _J2 = s1 + s0 x K2 = s0 x __ _J1 = s0 x K1 = x _J0 = x K0 = x


CMSC 313 Computer Organization & Assembly Language Programming Section 0101Fall 2004 Homework 5

Due: Tuesday, December 7, 2003

1. (10 points) Question A.13, page 494, Murdocca & Heuring

2. (10 points) Question A.29, page 497, Murdocca & Heuring

3. (10 points) Question B.10, page 542, Murdocca & Heuring

4. (10 points) Question B.11, page 542, Murdocca & Heuring

5. (60 points) This problem asks you to take the steps involved in the design process of afinite state machine. You will design a finite state machine that has a one bit input x

and a one bit output z. The machine must output 1 for every input sequence endingin the string 0010 or 100. The output should be 0 in all other cases.

[Adapted from Contemporary Logic Design, Randy H. Katz, Benjamin/CummingsPublishing, 1994.]

(a) (10 points) In the space provided on the next page, draw the minimum state-transition diagram for the finite state machine described above. You must usethe state-minimization algorithm described in class to show that the finite statemachine has the minimum number of states. (Hint: You should have fewer than8 states in your machine.)

(b) (5 points) Use the state assignment heuristics described in class and pick two

di!erent state assignments for your finite state machine. Note: the bit patternfor the initial state must be 000.

(c) (40 points) For each of the two state assignments:

i. Fill in the truth tables with values for D flip-flops, for the output bit andfor J-K flip-flops.

ii. Use the Karnaugh maps provided to minimize the formulas for each columnof the truth table.

iii. Count the number of gates needed for each implementation.

(d) (5 points) Should you use your first or second state assignment? D flip-flops orJ-K flip-flops?

Note: Keep a copy of your work for the last question. You will need it for DigSimAssignment 3.

CMSC 313 Homework 5 Name: _________________________________

Minimized State Transition Diagram (show work)

State Assignment:

Assignment#2Assignment #1

000000

F

E

D

C

B

unused

unused

A

ASSIGNMENT #1

Excitation Table for J-K Flip-Flops

Q Q' J K

0 0 0 d

0 1 1 d

1 0 d 1

1 1 d 0

Truth Table:

s2 s1 s0 x s2' s1' s0' z j2 k2 j1 k1 j0 k0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

s2’ = s1’ =

s0’ = z =

Assignment #1: Karnaugh Maps for D Flip-Flops and the output

# of gates = # of gates =

# of gates =# of gates =

Total # of gates for D flip-flops (don’t count z) =

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

j2 = k2 =

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

j1 = k1 =

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

j0 = k0 =

Assignment #1: Karnaugh Maps for J-K Flip-Flops




Total # of gates for J-K flip-flops (don’t count z) =

ASSIGNMENT #2

Excitation Table for J-K Flip-Flops

Q Q' J K

0 0 0 d

0 1 1 d

1 0 d 1

1 1 d 0

Truth Table:

s2 s1 s0 x s2' s1' s0' z j2 k2 j1 k1 j0 k0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

s2’ = s1’ =

s0’ = z =

Assignment #2: Karnaugh Maps for D Flip-Flops and the output


# of gates =# of gates =

Total # of gates for D flip-flops (don’t count z) =

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

j2 = k2 =

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

j1 = k1 =

10

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s010

11

9

14

15

13

6

7

5

2

3

1

81240

00 01 11 10

00

01

11

10

s2 s1

s0 x 11

s2

s1

x

s0

j0 = k0 =

Assignment #2: Karnaugh Maps for J-K Flip-Flops




Total # of gates for J-K flip-flops (don’t count z) =

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