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CMS Tracker FED CMS Tracker System Meeting Test Rob Halsall et al 30 July 2001 CERN. CMS Tracker FED Test 96 ADC Module. analogue. digital. FLASH. 3V. 3V. 3V. 2.5V. 1.8V. 1. 1. Opto Rx. 1. 1. Dual ADC. I2C. FPGA config. Synch & Processing. VME. VME Interface. SBC. FE 1. - PowerPoint PPT Presentation
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Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
CMS Tracker FED
CMS Tracker System Meeting
Test
Rob Halsall et al
30 July 2001
CERN
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
3V
CMS Tracker FED Test96 ADC Module
TTC
FPGA
Opto RxP
D A
rra
y
ProgDelay
1
Synch &Processing
TTCrx
FE 1
9
SBC
DAQ
QDR SSRAM1
SLINK
VME
BSCAN
FPGA
3V 2.5V 1.8V
DualADC
3V
DualADC
1
6
3V
FPGA
Opto Rx
PD
Arr
ay
8
Synch &ProcessingFE 8
8
3V2.5V 1.8V
DualADC
3V
DualADC
43
48
12 way FR
Readout &Synch Control
ASIC
ASIC
ASIC
3
ProgDelay
3
FPGA
FPGA
12
12
FPGA
FLASH
VMEInterface
I2C
12 way FR
BScan
FPGA config
12
1
85
96
clk40
I2C
1
I2CTempSense
TempSense
analogue digital
Clock inj
TTS
3V
3V
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
CMS Tracker FED System OverviewBoard Layout Reference
adc
TTCrx
FE 1
DAQ
TTC
FE 2
FE 3
FE 4
FE 5
FE 6
FE 7
FE 8
360 MByte/s
150 MByte/s/%
100 KHz
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
360 MByte/s
96 ADC Channels
VMEFPGA
SLINK PMC
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
VME
Boundary Scan
TTS
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
Test board
CMS Tracker FED TestPost Assembly 1
adc
TTCrx
96 ADC Channels
VMEFPGA
Test board
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
PSU
BSCAN CARD
Loop back
• Analogue Scan I/O via Test Modules• ‘Bed of Nails’ ATE test for Analogue?• ‘Fying Probe’ test for Analogue?
• Analogue Scan I/O via Test Modules• ‘Bed of Nails’ ATE test for Analogue?• ‘Fying Probe’ test for Analogue?
• Boundary Scan Test digital devices
• Bounday Scan Test Modules for I/O
• Boundary Scan Test digital devices
• Bounday Scan Test Modules for I/O
Opto Rxposition
Loop back
Loo
p ba
ck
Sysclock
BSCAN Module
Loop backTest board
AFGor
DACBSCAN
x12
x96
Assembly Company
Simple Passive Loop backVersion
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
FPGA
Test Module
CMS Tracker FED TestPost Assembly 1+
adc
TTCrx
96 ADC Channels
VMEFPGA
Test CMC
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
FPGA
PSU
BSCAN CARDor CHIPSCOPESysclock
• Bounday Scan Test Modules for connectors with digital signals
• CHIPSCOPE JTAG Readout…
• Bounday Scan Test Modules for connectors with digital signals
• CHIPSCOPE JTAG Readout…
• Boundary Scan digital devices• ‘Bed of Nails’ ATE test for Analogue• ‘Flying Probe’ ATE test for Analogue
• Boundary Scan digital devices• ‘Bed of Nails’ ATE test for Analogue• ‘Flying Probe’ ATE test for Analogue
Test board
Analogue signal Injection
DAC/AFG
Opto Rxposition
Assembly Company
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
Test board
CMS Tracker FED TestChipscope
adc
TTCrx
96 ADC Channels
VMEFPGA
Test board
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
PSU
Loop back
• Little design effort required• Early readout of ADC data• No VME Interface required
• Little design effort required• Early readout of ADC data• No VME Interface required
• ChipscopeLogic Analyser per ADC embedded in FPGA
Efffectively ‘Scope Mode’ with JTAG Readout
• ChipscopeLogic Analyser per ADC embedded in FPGA
Efffectively ‘Scope Mode’ with JTAG Readout
Opto Rxposition
Loop back
Loo
p ba
ck
Loop backTest board
AFGor
DACBSCAN
x12
x96
Assembly Company
Simple Passive Loop backVersion
Chipscope
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
FPGA
Test Module PSU
BSCAN CARDSysclock
CMS Tracker FED TestPost Assembly 2
adc
TTCrx
96 ADC Channels
VMEFPGA
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
TTC
• Single DAC Opto Tx fanned out 96 wayBoundary Scan controlled...
• Single DAC Opto Tx fanned out 96 wayBoundary Scan controlled...
• Simple DC scan test of ADC bitsToo complicated?
• Simple DC scan test of ADC bitsToo complicated?
BSCAN Controlled DAC& Opto Tx
Assembly Companyor RAL
Test CMC
FPGA
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
CMS Tracker FED TestInternal tests via VME
adc
TTCrx
96 ADC Channels
VMEFPGA
SLINK CMC
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
VMEVME SBC
RAL
EXT Clock
Boundary Scan
TTS
CHIPSCOPE
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
CMS Tracker FED TestPerformance/Soak
adc
TTCrx
96 ADC Channels
VMEFPGA
SLINK CMC
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
VME
BSCAN
AFG & Opto Tx
TTC System
DAQ System
VME SBC
TTS
• Level of Analogue testing?crosstalk, performance...
• Level of Analogue testing?crosstalk, performance...
• CHIPSCOPEFPGA Embedded Logic Analysers readout via Boundary Scan
• CHIPSCOPEFPGA Embedded Logic Analysers readout via Boundary Scan
CHIPSCOPE
RAL
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
CMS Tracker FED TestIn System
adc
TTCrx
96 ADC Channels
VMEFPGA
SLINK PMC
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
ROFPGA
SSRAMs
Top viewdigitalanalogue
VME
Boundary Scan
Detector
TTC System
DAQ System
VME SBC
TTS
• Detector ModuleGenerate input test signals
• Detector ModuleGenerate input test signals
• CHIPSCOPEFPGA Embedded Logic Analysers readout via Boundary Scan for commissioning
• CHIPSCOPEFPGA Embedded Logic Analysers readout via Boundary Scan for commissioning
CHIPSCOPE
Detector
Detector
Detector
Detector
Detector
Detector
Detector
RAL/CERN
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
CMS Tracker FED TestIn System - other aspects
adc
TTCrx
96 ADC Channels
VMEFPGA
SLINK PMC
FEFPGA
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
adc
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
FEFPGA
BEFPGA
SSRAMs
Top viewdigitalanalogue
VME
Front End
TTC System
DAQ System
VME SBC
• BE FPGA -> DAQ & TTSGenerate input test signals to DAQ &TTS
Fixed Pattern & Random Data Generation
• BE FPGA -> DAQ & TTSGenerate input test signals to DAQ &TTS
Fixed Pattern & Random Data Generation
• FED ‘SCOPE’ MODE + async TriggerSetup timing & calibration
APV diagnostics
• FED ‘SCOPE’ MODE + async TriggerSetup timing & calibration
APV diagnostics
Front End
Front End
Front End
Front End
Front End
Front End
Front End
CERN
Boundary Scan
TTS
CHIPSCOPE
Electronic System Design GroupInstrumentation Department Rob Halsall et al.Rutherford Appleton Laboratory 30 July 2001
CMS Tracker FED TestEquipment List
• JTAGLaptop & JTAG Software, USB-JTAG box, JTAG-I/O box, Cables & Connectors
VME I/O Module, Analogue I/O Module, SLINK I/O Module
• Analogue Performance TestsArbitrary Function Generator
Analogue I/O Module
Chipscope Kit
• Optical Test+Electrical-Optical Converter & Fanout
• Other ItemsTTC System, Clock Generator
VME SBC, VME-PC Interface
SLINK Modules
Labview, VxWorks….
9U VIPA Crate
Cooled Rack, Cooler
• JTAGLaptop & JTAG Software, USB-JTAG box, JTAG-I/O box, Cables & Connectors
VME I/O Module, Analogue I/O Module, SLINK I/O Module
• Analogue Performance TestsArbitrary Function Generator
Analogue I/O Module
Chipscope Kit
• Optical Test+Electrical-Optical Converter & Fanout
• Other ItemsTTC System, Clock Generator
VME SBC, VME-PC Interface
SLINK Modules
Labview, VxWorks….
9U VIPA Crate
Cooled Rack, Cooler