Cmpt Lect 02

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Brno University of Technology

Programming of Microcontrollers in Assembly Language

Microprocessor Techniques and Embedded SystemsLecture 2

Dr. Tomas Fryza
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Contents

Basic Architectures in Microprocessor TechniquesVon Neumann, Harvard, CISC, RISC

Development of Microcontrollers Applications

Assembler Directives

Programming Model

Types of InstructionsAVR Source Code Example
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Contents




Programming Model

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Princeton versus Harvard

In 1970s U.S. government asked Princeton and Harvard universities to come upwith a computer architecture (used in computing tables of Naval Artillery shelldistances for varying elevations and environmental conditions).Two basic conceptions:

Von Neumann (chief scientists name in Princeton univ.),Harvard.

Von Neumann architecture:computer with common memory for storing the control program as well as variables andother data structures,three fundamental parts of every computers: CPU, memory, I/O,internal structure is independent to the computer task (i.e. computer is controlled bysoftware),program is executed in sequential way (current instruction is dened by Program

Counter),memory is divided to constant blocks; indexes of these blocks are used as addresses.

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Harvard Architecture

Harvard conception used separate memory banks for program storage, theprocessor stack, and variable RAM.The Harvard architecture was largely ignored until the late 1970s.The Harvard architecture executes instructions in fewer instruction cycles thanthe Von Neumann architecture, because of a much greater amount of instructionparallelism is possible in Harvard architecture.Instruction fetches can take place during previous instruction execution and notwait for either a nish of instruction execution or have to stop the processorsoperation while the next instruction is being fetched.I.e. the current instruction was fetched during the previous instructionsexecution. This allows the instruction to execute in only one instruction cycle.
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Separate Memory Conception of Harvard Architecture (ATmega16)

Figure: Memory space for 8-bit MCU ATmega16.

Program memory is Flash type.Data memory is SRAM (StaticRandom Access Memory):32 general purpose registers,64 I/O registers, internal/externalmemory RAM.Date memory is also EEPROMtype (Electrically ErasableProgrammable Read-OnlyMemory).
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CISC versus RISC

There are two basic types of processor designed philosophies:CISC (Complex Instruction Set Computer),RISC (Reduced Instruction Set Computer).

In the 1970s and early 1980s, processors predominantly followed the CISCdesigned. The current trend is to use the RISC philosophy.

One factor of the popularity of CISC in the 1970s was the high price (mid-1970s:16KB 500) and small capacity of memory. So there was a need to minimize theamount of memory required to store a program.CISC systems use complex instructions (e.g. instruction that copies an elementfrom one array to another and automatically updates both array subscripts).RISC systems use only simple instructions (e.g. adding of two integers). Required

operands are in the processors internal registers, not in the main memory.
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CISC Processors

Table: Percent occurrence of operation types in common source codes.

Operation Percent occurrenceMemory loading 27.3 %

Conditional jump 13.7 %Memory storing 9.8 % P 50.8 %Values comparison 6.2 %Address loading 6.1 %Subtraction 4.5 %Character insert 4.1 %Addition 3.7 % P 75.4 %
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CISC/RISC Comparison

Table: Comparison of test applications for Intel 8085 (CISC) a ATmega16 (RISC).

Routine/application Intel 8085 ATmega16

Delay routine size 6 B 8 BDelay routine velocity* 10.5ms 2msStopwatch size 60 B 92 B (assembly)

3.5 kB (C code)

* Number of routine repetitions: 1,000 , f CPU =2MHz.

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Intel 8085 Instruction Set

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RISC Processor Instruction Set

Op code (instruction structure) of instruction ADD Rd, Rr (Rd=Rd+Rr):0000 11rd dddd rrrrd {0;31} 1st operand, resultr {0;31} 2nd operand

Op code of instruction INC Rd (Rd=Rd+1):1001 010d dddd 0011d {0;31} 1st operand, result
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Contents




Programming Model

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There are three basic methods how to program the target applications for

a MCU:First approach is to write an entire code in C language. The using of high-levellanguage brings to user the fast development possibilities and high code portability.With taking advantage of effective optimizing tools of development environment, thecompiled application could be optimized by speed and/or size criteria.The opposite approach uses the programming in low-level assembly language byparticular MCU instructions. By assembly programming approach, the absolute controlof program ow and the functional units loading is guaranteed.

Combination of both assembly and C code approaches.The microprocessor is controlled by program, i.e. by succession of instructionsstored in binary form.Instructions are stored in program memory (Flash type in AVRs); allinstructions are read and executed in sequential (successive) order.In microprocessor technique, instructions contains double information:

(1) What kind of operation should be executed (op code),(2) Operands address.

Each type of microcontrollers use different instruction set, i.e. there is no singleinstruction set for all manufactured microcontrollers.
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Source Code Translation

Figure: Process of source codetranslation.

Control unit of microcontroller works withinstructions in binary form machine language(16-bit words for AVRs).Compose applications in machine code isextremely ineffective, complicated, illegible the assembly code is used.Process of translation into machine language issupported by assembler replace eachinstruction with binary succession accordingthe dened rules.
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Source Code Example Registers

1 . include < m16def_mod.inc > ; i n c l u d e m o d i fi e d d e s c r i p t i o n f i l e f o r ATmega1623 l d i r1 6 , 0x0 a ; r1 6 = 0 a ( h ex )4 l d i r1 7 , 12 ; r 17 = 12 ( d ec )5

6 mov r1 8 , r16 ; r18 < r167 ad d r1 8 , r17 ; r 18 = r 18 + r 178 sub r1 6 , r17 ; r 16 = r 16 r179

10 loop : ; f o r ev e r l oo p11 r jmp loop ; jump t o l oo p l a b e l
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Programming in Assembly Language

Program stored in program memory is commonly displayed in hexadecimal system.Source code could contains 4 types of entry:(1) [label:] .directive [operands] [; comments](2) [label:] instruction [operands] [; comments](3) ; comments(4) empty line

Notation [ ] represents optional entry.Label is a symbolic identication of memory position ends by colon.

C

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Contents




Programming Model


A bl Di i (f AVR )

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Assembler Directives (for AVRs)(1) [label:] .directive [operands] [; comments]

Assembler-Directives control the assembler process and do not create any owncode.The leading dot must be in column 1 of the line.Most frequent using of directives:

Specifying memory type for code storing ( .cseg , .dseg , . . .),Macro denition ( .macro , .endmacro ),Variable denition ( .def , .equ , .set ),Files including ( .include ),. . .

Directive Description--------------------------------------------------------------------------.byte Byte allocation in data segment (SRAM memory).cseg Assemble to the program segment (Flash memory).db Inserts one or more constant bytes in the code segment.def Register definition.device Defines the type of the target processor.dseg Assemble to the data segment (SRAM).dw Insert a binary word in the code segment.endmacro End of the macro.equ Defines a symbol and sets its value.eseg Assemble to the EEPROM-segment.exit End of the assembler-source code (stops the assembling process).include Inserts the content of another source code file.list Switches the listing to the .LST-file on.listmac Macros will be listed in the .LST-file.macro Beginning of the macro.nolist Switches the output to the .LST-file off.org Defines the address, where the assembler assembles to.set Fixes the value of a symbol

P t f D iti Fil 16d f d i

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Part of Denition File m16def mod.inc

1 ; S p e c i f y D ev ic e2 . device ATmega1634 ; I /O R e g i s te r D e f i n i t i o n s5 .equ SREG = 3f6 .equ SPH = 3e7 .equ SPL = 3d8 .equ OCR0 = 3c9 .equ GICR = 3b ; New name f or GIMSK

10 .. .1112 ; PORTB 13 ; PORTB P or t B Data R e g i s t e r14 .equ PORTB0 = 0 ; Por t B Data R e g is t e r b i t 015 .equ PB0 = 0 ; For c o m p a t i b i l i t y16 .equ PORTB1 = 1 ; Por t B Data R e g is t e r b i t 117 .equ PB1 = 1 ; For c o m p a t i b i l i t y18 .. .1920 .equ RAMEND = 45F21 .. .2223 ; INTERRUPT VECTORS 24 .equ INT0addr = 0 x0002 ; E x t er n al I n t e r r u p t Re qu est 025 .equ INT1addr = 0 x0004 ; E x t er n al I n t e r r u p t Re qu est 126 .equ OC2addr = 0 x0006 ; Timer / Counter2 Compare Match27 .. .

Using of Macro Directives
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Macros could be used for repetitious parts of source code.

While the macro name is used inside the source code, it is replaced byinstructions succession dened between directives .macro and .endmacro .Macro can use up to 10 parameters (operands), titled @0 @9.

1 ; a p p l i c a t i o n i n i t i a l i z a t i o n , i n c l u d i n g new m acr o d e f i n i t i o n2 . include < m16def_mod.inc > ; i n c l u d e m o d i fi e d d e s c . f i l e f o r ATmega163 .macro ADD16 ; b eg in ni ng od new macro t i t l e d ADD164 add @0 , @2 ; add two l ow e r b y te s5 adc @1 , @3 ; add two h i g he r b y te s ( w it h c a r r y )6 .endmacro ; e nd o f new m ac ro78 .. .9 ; u s i n g t h e new macro i n c od e

10 ADD16 r16 , r1 7 , r18 , r19 ; a dd t wo 16 b i t v a lu e s

Example of macro usage: ADD16 r16,r17,r18,r19@0: r16 , @1: r17 , @2: r18 , @3: r19

1 ad d R1 6 , R182 adc R1 7 , R19

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1 ; a p p l i c a t i o n i n i t i a l i z a t i o n , i n c l u d i n g new ma cr o d e f i n i t i o n2 . include < m16def_mod.inc > ; i n c l u d e m o d if i e d d e s c . f i l e f o r ATmega163 .macro SETPORTB ; be gi nn in g of new macro t i t l e d SETPORTB4 l d i r1 6 , @0 ; l o a d f i r s t m ac ro p a r a m e te r5 out DDRB , r1 6 ; s et d i r e c t i o n o f p o rt B6 l d i r1 6 , @1 ; l o a d s e co n d m ac ro p a r am e t er7 out PORTB , r1 6 ; s et da ta o f p or t B8 .endmacro ; e nd o f new ma cr o9

10 . ..11 ; u s i n g t h e new macro i n c od e12 SETPORTB 0xf f , 0x11110000 ; s e t p or t B

Example of macro usage:SETPORTB 0xff, 0b10101010

This macro contains two input parameters: 0xff (assembler works with in via symbol@0) and 0b10101010 (@1).In process of preprocessing, the new dened macro SETPORTB will be replaced byfollowing code:

1 l d i r1 6 , 0xf f2 out DDRB , r1 63 l d i r1 6 , 0b101010104 out PORTB , r1 6

Contents
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Contents




Programming Model


Programming Model
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Programming Model

Denition (Programming model)Programming model of microcontroller is description of memory space, availableregisters, addresses and functions the programmer could used.

Memory space (AVRs)Separated memory space for program and data (Harvard architecture),Internal and external address space,ATmega16: Flash (8k 16), SRAM (1k 8), EEPROM (512 8).

SRAM: 32 general purpose registers ( R0R31), 64 I/O registers for controllinginternal peripherals, and data memory.EEPROM: longer access time than SRAM, stored data rest in memory after thesupply voltage disconnection, (constant storage, conversion table, settings, etc.).

I/O (Control) Registers of AVR
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I/O (Control) Registers of AVR

I/O registers are used for internal peripheries and MCU core control. Mostimportant registers for programmers.For ATmega16 the I/O registers are mapped from 0x20 to 0x5F addresses.Access to I/O registers are possible via IN and OUT instructions.

Table: Selected I/O AVR Registers

Address Name Description

. . .0x39 PINA Port A Input Pins Address0x3A DDRA Port A Data Direction Register0x3B PORTA Port A Data Register. . .

0x52 TCNT0 Timer/Counter 0 (8 Bits). . .

0x5B GICR General Interrupt Control Register0x5C OCR0 Timer/Counter 0 Output Compare Reg.0x5D SPL Stack Pointer (low byte)0x5E SPH Stack Pointer (high byte)0x5F SREG Status Register

Contents

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Contents




Programming Model


Types of Instructions
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Types of Instructions

(2) [label:] instruction [operands] [; comments]Instructions could be divided into:

Arithmetical operations (addition, subtraction, incrementation, . . .),Logical operations (AND, XOR, . . .),Jump operations (unconditional/conditional branching, subroutines calling, . . .),Data movement operations (between registers, read/write from/to memory, . . .),Binary operations (set/clear individual bits, swap nibbles, . . .),Control instructions (nop, sleep, watchdog reset, . . .).

For AVR (ATmega16) there are 131 instructions. Detailed information could befound in AVR instruction set manual.

Arithmetical/logical Operations (AVRs)
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Arithmetical/logical Operations (AVRs)

Instr. Operands Description Operation Flag Cycles----------------------------------------------------------------------------

ADD Rd, Rr Add two Registers Rd=Rd+Rr Z,C,N,V,H 1ADC Rd, Rr Add with Carry two Registers Rd=Rd+Rr+C Z,C,N,V,H 1SUB Rd, Rr Subtract two Registers Rd=Rd-Rr Z,C,N,V,H 1AND Rd, Rr Logical AND Registers Rd=Rd^Rr Z,N,V 1OR Rd, Rr Logical OR Registers Rd=RdvRr Z,N,V 1EOR Rd, Rr Exclusive OR Registers Rd=RdxorRr Z,N,V 1COM Rd Ones Complement Rd=$FF-Rd Z,C,N,V 1

NEG Rd Twos Complement Rd=$00-Rd Z,C,N,V,H 1SBR Rd,K Set Bit(s) in Register Rd=RdvK Z,N,V 1CBR Rd,K Clear Bit(s) in Register Rd=Rd^($FF-K) Z,N,V 1INC Rd Increment Rd=Rd+1 Z,N,V 1DEC Rd Decrement Rd=Rd-1 Z,N,V 1TST Rd Test for Zero or Minus Rd=Rd^Rd Z,N,V 1CLR Rd Clear Register Rd=RdxorRd Z,N,V 1SER Rd Set Register Rd=$FF None 1MUL Rd, Rr Multiply Unsigned R1:R0=RdxRr Z,C 2MULS Rd, Rr Multiply Signed R1:R0=RdxRr Z,C 2... ...

Jump Operations (AVRs)
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p p ( )

Instr. Operands Description Operation Flag Cycles----------------------------------------------------------------------------RJMP k Relative Jump PC=PC+k+1 None 2IJMP Indirect Jump to (Z) PC=Z None 2JMP k Direct Jump PC=k None 3RCALL k Relative Subroutine Call PC=PC+k+1 None 3ICALL Indirect Call to (Z) PC=Z None 3CALL k Direct Subroutine Call PC=k None 4RET Subroutine Return PC=STACK None 4RETI Interrupt Return PC=STACK I 4CPSE Rd, Rr Compare, Skip if Equal None 1/2/3CP Rd, Rr Compare Rd-Rr Z,N,V,C,H 1CPC Rd, Rr Compare with Carry Rd-Rr-C Z,N,V,C,H 1CPI Rd, K Compare Register with Immediate Z,N,V,C,H 1SBRC Rr, b Skip if Bit in Register Cleared None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set None 1/2/3SBIC P, b Skip if Bit in I/O Register Cleared None 1/2/3SBIS P, b Skip if Bit in I/O Register is Set None 1/2/3... ...

Data Movement Operations (AVRs)
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p ( )

Instr. Operands Description Operation Flag Cycles----------------------------------------------------------------------------

MOV Rd, Rr Move Between Registers Rd=Rr None 1MOVW Rd, Rr Copy Register Word Rd+1:Rd=Rr+1:Rr 1LDI Rd, K Load Immediate Rd=K None 1LD Rd, X Load Indirect Rd=(X) None 2LD Rd, X+ Load Indirect and Post-Inc. Rd=(X), X=X+1 2LDD Rd, Z+q Load Indirect with Displacement Rd=(Z+q) None 2LDS Rd, k Load Direct from SRAM Rd=(k) None 2

ST X, Rr Store Indirect (X)=Rr None 2ST X+, Rr Store Indirect and Post-Inc. (X)=Rr, X=X+1 2STS k, Rr Store Direct to SRAM (k)=Rr None 2LPM Load Program Memory R0=(Z) None 3LPM Rd, Z Load Program Memory Rd=(Z) None 3LPM Rd, Z+ Load Program Memory and Post-Inc Rd=(Z), Z=Z+1 3SPM Store Program Memory (Z)=R1:R0 None -IN Rd, P In Port Rd=P None 1OUT P, Rr Out Port P=Rr None 1PUSH Rr Push Register on Stack STACK=Rr None 2POP Rd Pop Register from Stack Rd=STACK None 2... ...

Binary Operations (AVRs)
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y p ( )

Instr. Operands Description Operation Flag Cycles----------------------------------------------------------------------------SBI P,b Set Bit in I/O Register I/O(P,b)=1 None 2

CBI P,b Clear Bit in I/O Register I/O(P,b)=0 None 2LSL Rd Logical Shift Left Z,C,N,V 1LSR Rd Logical Shift Right Z,C,N,V 1ROL Rd Rotate Left Through Carry Z,C,N,V 1ROR Rd Rotate Right Through Carry Z,C,N,V 1ASR Rd Arithmetic Shift Right Z,C,N,V 1SWAP Rd Swap Nibbles None 1BSET s Flag Set SREG(s)=1 SREG(s) 1BCLR s Flag Clear SREG(s)=0 SREG(s) 1BST Rr, b Bit Store from Register to T T=Rr(b) T 1BLD Rd, b Bit load from T to Register Rd(b)=T None 1SEC Set Carry C=1 C 1CLC Clear Carry C=0 C 1SEN Set Negative Flag N=1 N 1CLN Clear Negative Flag N=0 N 1SEZ Set Zero Flag Z=1 Z 1CLZ Clear Zero Flag Z=0 Z 1SEI Global Interrupt Enable I=1 I 1CLI Global Interrupt Disable I=0 I 1... ...

Control Operations (AVRs)
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Instr. Operands Description Operation Flag Cycles----------------------------------------------------------------------------NOP No Operation None 1

SLEEP Sleep None 1WDR Watchdog Reset None 1BREAK Break For On-Chip Debug Only None N/A... ...
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Source Code Example Arithmetical Operations

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1 . include < m16def . inc > ; desc rip t ion f i le fo r ATmega162 . de f t emp = R16 ; s y m bo l ic n am e f or r e gi s te r R 163 . d ef a = R1 7 ; s y m bo l ic n am e f or r e gi s te r R 174 . d ef b = R1 8 ; s y m bo l ic n am e f or r e gi s te r R 185

6 L DI a , 0x05 ; a = 57 L DI b , 6 ; b = 689 M UL a , a ; R1 : R0 = a x a

10 MOV temp , R0 ; temp < R011 M UL a , b ; R1 : R0 = a x b12 L SL R 0 ; R0 = 2 x R013 ADD temp , R0 ; temp = temp + R014 M UL b , b ; R1 : R0 = b x b

15 ADD temp , R0 ; temp = temp + R01617 loop : ; fo rever loop18 RJMP loop ; j u mp t o l oo p

Machine language of source code example:Address Mach.lang. Instruction-----------------------------------------

+00000000: E015 LDI R17,0x05+00000001: E026 LDI R18,0x06+00000002: 9F11 MUL R17,R17+00000003: 2D00 MOV R16,R0+00000004: 9F12 MUL R17,R18+00000005: 0C00 LSL R0+00000006: 0D00 ADD R16,R0+00000007: 9F22 MUL R18,R18+00000008: 0D00 ADD R16,R0@00000009: loop+0000000A: CFFF RJMP PC-0x0000
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