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TV OF HAWAII UBI'.ARY UNIVERSI
CMOS IC IMPLEMENTATION OF HEART RATE DETECTION HARDWARE
A THESIS SUBMITTED TO THE GRADUATE DIVISION OF
THE UNIVERSITY OF HAWAI'I IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING
DECEMBER 2006
By
Xiaoyue Wang
Thesis Committee:
Olga Boric-Lubecke, Chairperson Victor M. Lubecke Luca Macchiarulo
We certify that we have read this thesis and that, in our opinion, it is satisfactory in scope and quality as a thesis for the degree of Master of Science in Electrical Engineering.
THESIS COMMITIEE
Zr: g~ - :;{£eJe I Chairperson
tfod~ ~ v
Abstract
Heart rate variability (HRV) studies have shown that beat-to-beat interval variability
is a strong indicator of a number of medical conditions, including heart failure, diabetes,
and hypertension. Instantaneous heart rate interval is required for HRV evaluation. The
focus of this thesis is hardware design and integrated circuit implementation for heart rate
interval extraction in Doppler radar and BCG systems. The hardware includes an RF
mixer for frequency translation in a Doppler radar receiver, a pre-amplifier for
physiological base-band signal conditioning prior to analog-to-digital conversion, as well
as digital ASIC for storing long-term heart rate intervals. The 0.25 J.Illl CMOS resistive
ring mixer operates in the near-threshold region, achieving conversion loss of 7 dB at 3.6
GHz, with low RF insertion loss in the frequency range of 2-8 GHz. By applying a small
gate bias, the conversion loss under very low LO conditions is improved tremendously.
The conversion loss degrades by 14 dB only for LO power in the range of 10 dBm to
-IOdBm, as compared to over 85 dB degradation for the same LO power range but
without gate bias. A pre-amplifier with the tunable bandwidth of 0.1-50Hz and tunable
gain of 500-1 0,000 was implemented on a proto-board as well as PCB. The amplifier was
tested using BCc; finger pressure pulse, and Doppler radar signals, and it was
demonstrated that it has a lower noise floor than a commercial instrumentation amplifier.
This amplifier can be integrated on a single chip with the exception of two capacitors.
Finally, a digital ASIC design with an efficient memory that can store up to 24 hours of
continuous heart rate interval data by recording the difference between every two
adjacent intervals in a single-port synchronous, high-performance SRAM, with a fixed
resolution of 1 ms, is discussed. The system has been laid out in a commercial 0.18 J.Illl
2
CMOS process in a 2.5 mm x 2.5 mm hardware core, and power consumption was
estimated to be I 551lW. The hardware described in this thesis may enable future
miniaturization ofHRV monitoring devices.
3
Table of Contents
Abstract ...•...•.••...•.•...•............•.••..............•.•...•.•....•..•.••..•..........................•..••..•..••...••.••.................... 2 List of Figures .................................................................................................................................. 6 List of Tables .................................................................................................................................. 11 Chapter 1 .... .•.. .•. .•.. .•.... ....... ...... ...... .•... .••.•. ............ ..•.. .•.... ... ... ...... ............... ........ .••.••.. .•••••. .•••••.••.•. 12 1. Introduction ............................................................................................................................ 12 Chapter 2 ........................................................................................................................................ IS 2. 0.25 IIlII CMOS Resistive Ring Near-threshold Mixer Design .............................................. IS
2.1. Introduction ................................................................................................................. 15 2.2. Mixer theory ................................................................................................................ 16
2.2.1. Mixer Introduction ........................................................................................... 16 2.2.2. Devices for Mixers .......................................................................................... 17 2.2.3. Mixer Classifications ....................................................................................... 20
2.3. Theoretical Analysis of Mixer Design ........................................................................ 26 2.3.1 Selection of Device Size .................................................................................. 26 2.3.2 The Theoretical Verification of the Improvements of Conversion Loss Applied by A SmaIl DC Gate Biased Voltage ................................................ , ............................. 27
2.4. 2.4 GHz Resistive Ring Mixer Design ........................................................................ 33 2.4.1. Schematic of the mixer .................................................................................... 33 2.4.2. The relationship between Conversion Loss and DC Gate Biased Voltage •.•... 35 2.4.3. Mixer Perfonnance .......................................................................................... 36 2.4.4. Mixer Layout ....................................................................................................... 42
2.5. Chip Measurements .................................................................................................... 44 2.6. Conclusions ................................................................................................................. 52
Chapter 3 ........................................................................................................................................ 53 3. Analog Signal Processing ...................................................................................................... 53
3.1. Review of Previous Preamplifier ................................................................................ 53 3.2. Improvements and Modifications ............................................................................... 56 3.3. BreadOOatd Test .......................................................................................................... 58
3.3.1. Test with Real-time Figure Pu\se Signals and BCG Signala ........................... 58 3.3.2. Test the Pre-amplifiers with Coaxia1-component Doppler Radar System. .••.•• 59 3.3.3. Test the Pre-amplifiers with Shuhei's Boards .••..........................................•...• 61
3.4. PCB Implementation ................................................................................................... 62 3.4.1. PCB Layout of the Preamplifier ...................................................................... 62 3.4.2. PCB Assemble of the Preamplifier .................................................................. 65
3.5. Test of Preamplifier PCB ..........................•.....•..•...•...............................•...•..•..••..•..•... 67 3.6. Conclusion .................................................................................................................. 70
Chapter 4 ........................................................................................................................................ 72 4. Digital HRV Monitoring System on Chip .............................................................................. 72
4.1. Pre-existing HRV Monitoring System ........................................................................ 73 4.2. Improved Design of System on Chip .......................................................................... 74
4.2.1. Introduction ..................................................................................................... 74 4.2.2. Efficient Algorithm .......................................................................................... 76 4.2.3. SOC Design ...................................................................................................... 80 4.2.4. Verification and Layout of the SoC ................................................................. 85
4.3. Conclusions ................................................................................................................. 87 Chapter 5 ........................................................................................................................................ 89 5. Conclusions ............................................................................................................................ 89
4
Acknowledgements ........................................................................................................................ 91 References ...................................................................................................................................... 92 Appendix ........................................................................................................................................ 97
L VHDL Code of Efficient SRAM ................................................................................. 97
s
List of Figures
Fig. 1.1 Block diagram ofECG (a) and microwave Doppler radar (b) heart rate extraction
systems ............................................................................................................................... 13
Fig. 2.1 (a) Schematic representation of a generic mixer. (b) Mixing products when RF
frequency, IV, is mixed with local oscillator frequency, IVp ................................ 17
Fig. 2.2 Single-ended diode mixer ............................................................... 19
Fig. 2.3 A single-device FET mixer ................................................................................... 21
Fig. 2.4 (a) RealiUltion of single balanced diode mixer using the transformer. (b) A
double balanced diode mixer using the transformer hybrid .............................................. 22
Fig. 2.5 Circuit schematic of a Gilbert Cell mixer ......................................................... ..
23
Fig. 2.6 Schematic of a double-balanced passive FET mixer ............................................ 2S
Fig. 2.7 The ring configuration for selecting device size .................................................. 26
Fig. 2.8 Conversion loss as a function of device size ........................................................ 27
Fig. 2.9 Schematic of the passive mixer without any gate biased voltage ................... 28
Fig. 2.10 The return loss at LO and RF port, respectively ................................................. 29
Fig. 2.11 Conversion loss (dB) as a function ofRF frequency (GHz) without bias .......... 29
Fig. 2.12 Conversion Loss as a function ofLO power without bias ................................. 30
Fig. 2.13 S-paramter simulation at LO and RF ports of the ring structure without
bias ..................................................................................................................................... 30
Fig. 2.14 S-paramter simulation at LO and RF ports of the ring structure with a small gate
6
bias of 0.4S V at gates ........................................................................................................ 31
Fig. 2.1S Return Loss at LO (left) and RF (right) ports with a small gate biased voltage of
0.4SY. ................................................................................................................................. 32
Fig. 2.16 Conversion loss as a function ofRF frequency with a small gate biased voltage
of O.4SV .............................................................................................................................. 32
Fig. 2.17 Conversion loss as a function ofLO power with a small gate biased voltage of
O.4SY. ................................................................................................................................. 33
Fig. 2.18 Schematic of mixer ............................................................................................. 34
Fig. 2.19 Conversion loss as a function of DC gate biased voltage for LO power of 10
dBm ...................................................................•..•..............•............ . 3S
Fig. 2.20 Conversion loss as a function ofLO power with (solid line) and without (circles)
gate bias voltage ...............................................................................................................•. 3S
Fig. 2.21 Return loss at (a) LO port and (b) RF port as a function of frequency (c)
S-parameter in LO and RF port, respectively ..............•.•.•.••............................. 37
Fig. 2.22 The conversion loss as a function ofRF frequency for LO power of 1000m
(circles). OdBm (crosses). -10dBm (squares) .................................................................... 38
Fig. 2.23 PldB for LO power of 1000m with a small gate biased voltage ofO.4SV ........ 39
Fig. 2.24 PldB for LO power of 10dBm without gate biased voltage .............................. 39
Fig. 2.2S IIP2 and IIP3 of the double balanced ring mixer with a small DC gate biased
voltage of O.4SV ................................................................................................................ 40
Fig. 2.26 IIP2 and IIP3 of the double balanced ring mixer without DC gate biased
volta.ge .............................................................................................................................. 41
Fig. 2.27 lIfnoise of passive mixer with a small DC gate biased voltage of
O.4SV ................................................................................................................................ 42
7
Fig. 2.28 lIf noise of passive mixer without DC gate bias .................••••..•••.•................. .42
Fig. 2.29 Layout of the mixer. Chip size is 1.2mm x 0.8 mm .•....................................... 43
Fig. 2.30 The photograph of the passive mixer on chip .................................................. 45
Fig. 2.31 The return loss at each port of mixer ..............................•.•..•.•..•.•.•.••............... .47
Fig. 2.32 Conversion loss measurement setup for test of chip •............................. 47
Fig. 2.33 The power level at different stage of measurements setup .........................•..•. .48
Fig. 2.34 The measurement results of conversion loss as a function of Gate Biased
voltage .............................................................................................................................. 49
Fig. 2.35 The measurement results of conversion loss as a function of LO Power .•...... 49
Fig. 2.36 Measurement results of conversion loss as a function ofRF frequency ........ 50
Fig. 2.37 PldB ..................................................................................... 51
Fig. 2.38 The third-order intercept power ...................................................... 51
Fig. 3.1 The schematic of the previous preamplifier ...................................•....•. 55
Fig. 3.2 Frequency response in PSpice vs. breadboard implementation [29] ............. 55
Fig. 3.3 . Block diagram of the new preamplifier ..................................••....................... 56
Fig. 3.4 Comparison between the output of the preamplifiers (blue) and SRS (Model
No.: SR560) (green) using real-time ECG signals ..............................•.............. 59
Fig. 3.5 The block diagram of coaxial-component Doppler radar system ................ 59
Fig. 3.6 Test result when connecting the coaxial-component Doppler radar with SRS
(Model No.: SR560) ............................................................................. 60
Fig. 3.7 Test results connecting the coaxial-component Doppler radar with
8
preamplifier .................................................................................................................... 60
Fig.3.8 Comparison between the heart rate as a function of time determined from the
reference signal (yellow) and the output of the preamplifier (red) using
Labview ..................................................................................................... 61
Fig. 3.9 Comparison between the heart rate as a function of time determined from the
reference signal (yellow) and the output ofSRS (Model No.: SRS60) (red) using
I.,abview ... ............ ......................................................................................................... 61
Fig.3.10 Comparison between the heart rate as a function of time determined from the
reference signal (yellow) and the output of the preamplifier (red) using Labview ........... 62
Fig. 3.11 The layout of the preamplifier (5 inches x 3.1 inches) .............................. 62
Fig. 3.12 The picture of the preamplifier on PCB before assembling ............................. 65
Fig. 3.13 The picture of preamplifier on PCB after assembling .............................. 66
Fig. 3.14 Measurement Setup I for PCB Preamplifier .................................................. 67
Fig. 3.15 Measurement results from Setup 1. .................................................. 68
Fig. 3.16 The comparison between Stanford Research System and PCB Preamplifer .... 68
Fig. 3.17 Measurement setup n for PCB preamplifier test .................................... 69
Fig. 3.18 The comparison between two PCB preamplifers ............................................... 70
Fig. 4.1 HRV monitoring system block diagram ............................................................... 72
Fig. 4.2 Previous SoC block diagram ............................................................. 73
Fig. 4.3 Pre-recoded ECG trace from Physionet database (top), corresponding R-R
intervals (middle) and difference ofR-R intervals (bottom) ............................................. 75
Fig.4.4 The lllustration of the Efficient RAM Algoritbm. ...................................... 78
9
Fig. 4.5 SoC Block Diagram ............................................................................................ 81
Fig. 4.6. Finite state machine of peak detector[29] ........................................................... 82
Fig. 4.7 Finite state machine of RAM (a) writing (b) reading protocol ............................ 85
Fig. 4.8 VHDL Post-synthesis Simulation ...................................................... 86
Fig. 4.9 Layout of the Chip ........................................................................ 88
10
List of Tables
Table 2.1 Power level at different positions ...................................................................... 48
Table 2.2 The measurements results on 11P2 and 11P3 .... '" .................................. 51
Table 3.1 Gerber File Representation. ............................................................................... 63
Table 3.2 The General Fabrication Infonnation for PCB ofPreamplifier .................... 64
Table 3.3 Corresponding cut off frequency ofHPF by channel selection ................•.. 66
11
Chapter 1
1. Introduction
Heart rate variability (HRV) studies have shown that beat-to-beat interval variability
is a strong indicator of a number of medical conditions, including heart failure [1],
diabetes [2-3], and hypertension [4]. Instantaneous heart rate interval is required for HRV
evaluation. Heart rate is usually obtained using at least three ECG electrodes attached to
the patient. Microwave Doppler radar offers a non-contact alternative for heart rate
extraction and monitoring [5-12]. The focus of this thesis is hardware design and
integrated circuit implementation for heart rate interval extraction in Doppler radar and
ECG systems.
Fig. 1.1. illustrates the block diagram of typical ECG (a) and Doppler radar (b) heart
rate extraction systems. Both types of signals require a pre-amplifier to adjust the signal
level for optimum quantization and provide anti-aliasing filtering prior to
ana1og-to-digital conversion. Once the signals are digitized, heart rate extraction is
usually performed off-line using a PC. Radio part of Doppler radar hardware includes a
signal source which provides both the transmit signal and local oscillator required for
frequency translation, and a frequency down-converter (mixer) that down-converts
reflected signal to baseband. The signal that is reflected from the subject is "mixed" with
the portion of the signal source to produce a baseband output proportional to the chest
displacement [8-10]. Three hardware blocks highlighted in Fig.l.l will be discussed in
this thesis.
12
ADe H ::~J (a)
Antenna
ADC
(b)
Fig. 1.1 Block diagram ofECG (a) and microwave Doppler radar (b) heart rate extraction systems.
Chapter 2 presents a mixer design suitable for a Doppler radar system. A 2.4 GHz
(ISM band) double-balanced resistive ring mixer design and IC implementation are
discussed. A novel implementation with a small gate bias vo ltage just below the threshold
voltage is proposed, to enable very low LO power operation. This mixer has been
designed and fabricated in 0.25 !!m CMOS TSMC process. The lowest conversion loss of
7 dB was achieved at 3.6 GHz, with LO power of 10 dBm, and with low RF insertion loss
in the frequency range of 2-8 GHz. If the LO power is reduced to -IOdBm, this mixer
conversion loss is increased by 14dB. For comparison, if the mixer is not biased,
conversion loss would increase by over 85 dB for the change in LO power from 10 dBm
to-IOdBm.
Chapter 3 presents the preamplifier with the tunable gain of 500-10,000 and the
tunable bandwidth of 0.1, 0.33, 0.5, I and 3.3Hz-50Hz, which was implemented on a
13
proto-board as well as PCB. It can be connected to IF port of mixer discussed in Chapter
2 to amplify and filter the signals and remove the DC as required. The preamplifier was
tested using BCG, finger pressure pulse, and Doppler radar signals, and it was
demonstrated that it has a lower noise floor than a commercial instrumentation low-noise
preamplifier. This preamplifier can be integrated on a single chip with the exception of
two large capacitors.
Chapter 4 discusses a digital ASIC design with an efficient memory that can store up
to 24 hours of continuous heart rate interval data by recording the difference between
every two adjacent intervals in a single-port synchronous, high-performance SRAM, with
a fixed resolution of Ims. The system has been laid out in a commercial 0.18 jUl1 CMOS
process in a 2.Smm x 2.Smm hardware core with a low power consumption of less than 155
jLW. This system includes peak detector, R-R interval counter, and a SRAM with a very
efficient writing and reading algorithm.
Chapter 5 drsws thesis conclusions and includes suggestions for future work. The
hardware described in this thesis may enable future miniaturization of HRY monitoring
devices.
14
Chapter 2
2. 0.25 JIm CMOS Resistive Ring Near-threshold Mixer
Design
2.1. Introduction
High-performance mixers capable of downconverting small RF signals without
distortion are required for wireless communication radios [13-25]. As compared to
Gilbert cell active mixers, passive CMOS mixers exhibit high linearity, low lIf noise and
shot noise, with no DC power consumption. While conversion loss of passive mixers is
moderate and comparable to diode mixers [17], a relatively high level of LO power is
required to achieve such performance. This chapter will present the design of a 2.4-GHz
double-balanced resistive ring mixer with a gate bias voltage below the threshold voltage.
This low gate bid improves conversion loss under low LO conditions tremendously,
while the DC power dissipation is negligible.
This chapter is organized as follows. In Section 2.2, the mixer theory is introduced.
The theoretical verification of the improvements of conversion loss by applying a small
gate bias voltage, is explored in detail in Section 2.3, followed by mixer with gate bias
design, simulation, and layout in Section 2.4. Measurement results are presented in
Section 2.5, followed by conclusions in Section 2.6.
15
2.2. Mixer theory
2.2.1. Mixer Introduction
Mixer is fundamentally a frequency translating device or a multiplier. If two
sinusoid waves are applied to an ideal analog multiplier, the signal applied to the RF port
has a carrier frequency c.>. and a modulation waveform A(t); and the LO signal is a pure,
unmodulated sinusoid at frequency COp, the signal at the IF port will carry same
modulation properties of the RF signal, at the sum and difference of the two input
frequencies. Fig. 2.1 (a) illustrates the results after RF and LO signals are mixed. If the
mixing device is non-linear, the harmonics associated with fundamental frequencies will
be generated after mixing, indicated in Fig. 2.1 (b)
RF: A(t)cos(w,t)
LO:cos(wi)
IF: A(t) cos(w,t) cos(wi) = A~) [cos[(w, -wp)t]+cos[(w, +wp)t]]
RF
(a)
16
rop
(b)
Fig. 2.1 (a) Schematic representation of a generic mixer. (b) Mixing products when RF frequency, IV, is mixed with local oscillator frequency, IVp
The output consists of the harmonics of the tones, both the sum and difference
frequencies. Fig. 2.1 (b) shows all the intennodulation products at the IF ports after RF and LO
signals are mixed.
Frequency multiplication can be realized using a non-linear element (such as
Schottky-barrier diode), a time-varying resistsnce (such as FET channel resistsnce where
an AC signal is applied to the gate) or a variable gain amplifier where the gain is a
function of the control signal.
2.2.2. Devices for Mixers
Devices that exhibit nonlinear or rectifying characteristics are good candidates for
designing mixers. Schottky barrier diode is widely used for its nonlinear characteristic, a
diode consisting of a rectifying meta1-to-semiconductor junction, can be fabricated with
low junction capacitance and low series resistance [22]. Such mixers have broad
bandwidth and are low cost. In addition, diodes do not need dc bias to operate and have
17
fast switching capability. The nonlinearity of the diode is given by the following
expression mathematically: The current is approximately expressed by
I(V) = I.., [exp(q V /7JKT)-I] '" A. +~V +~V2 +A,V' +...... (Eq.2-1)
where q is the electron charge; K is Boltzmann's constant, 1.37 x 10-23
JIK; and T is
absolute temperature, and 7J is a constant greater than 1.0 and normally smaller than 1.20,
dependant on imperfections in the junction. And 11111 is called the reverse-saturation
current because 1(V) equals I"" as voltage is approaching infinite.
Th A.~A,A, d 'edbth sh' en , , , ... are constants etermin y ose parameters own m
I(V) =lw[exp(qV /7JKT)-I] '" A. + ~V + A,V2 + A,V' +... ... (Eq.2-1.
Then V. which includes two-tone excitation, is given in the following expression:
v. = ~ cos(w,t) + V2 cos(w2t) ................................................... (Eq. 2-2)
Substituting V. = ~ cos(w,t) + 11; COS(W2t) ................................................... (Eq.
2-21(V) = I.., [exp(q V /7JKT)-I]", A. +~V +A,V2 +A,V' +...... (Eq. 2-1, we have
I(V) '" A. + ~[~ cos(w,t) + 11; COS(W2t)] + ~[~ cos(wrt) + V2 COS(102t)]2 + ...
= A. + ~[~ cos(~t) + 11; cos(lOzI)]
+A,[~2 cos2(lO,t) + 2~V2 cos(~t)COS(102t) + 11;2 cos2 (102t )] + ...
= A. + ~[~ cos(~t) + V2 COS(102t)]
+ A, {~2 + V22 + ~2 cos(2w,t)+ 11;2 COS(2lO2t)+2~V2[COS«lO, + lO2)/)+COS«lO, -(2)t)]}
2
The output current consists of a remarkable number of new frequency components,
including the products of two frequencies, for example, cos(~t)COs(102t), which
indicated the mixing action since the products contains both the sum and difference of the
frequencies.
18
Both the RF and LO signals are applied into one terminal of the diode through
appropriated filters. The IF signal is coming out from the other terminal through the IF
filter, which is illustrated in Fig. 2.2. This type of mixer is fundamentally a switch that
turns on and off at the local oscillator frequency [23]. The diode moves from a
low-resistance state (when it is forward biased) to a high-resistance state (when it is
reverse biased) during the voltage swing of the LO. The RF signal delivered to the IF
load is interrupted as the diode are switched on and off. When this type of modulation
occurs the signal at the IF port contains the sum and difference frequencies as well as
many other products of the RF and LO.
RF IF Filler Filler
Fig. 2.2 Single-ended diode mixer
Besides Schottke-barrier diodes. field-effect transistors (FETs) and bipolar junction
transistors (BIT), have also been used in mixer design. While diode mixers have been
traditionally used in microwave and millimeter-wave applications, the transistor mixers
are more common for lower frequency applications. With the advances in integrated
circuit technology, transistor mixer are becoming more prevalent since diodes are not as
amenable to circuit integration.
FETs mixers can be either active or passive. In the active FETs mixer, their
time-varying transconductance results in frequency conversion when the LO power is
applied at the gates of the devices. While in the passive FETs mixer, normally called FET
resistive mixer, the contributor to the frequency conversion is due to the time-varying
19
channel resistance.
In the active FET mixers, the LO and RF signals are combined to apply to the gate
of the transistor, the transconductance and the RF signal contributes to the mixing, which
is indicated by the following expression:
id(t) = g .. (t)V u(t) ............................................................... (Eq. 2-3)
lIB for passive FET mixers, the FET operates in the linear region, without any de
bias applied to the channel. FET resistive mixer has many advantages, for example, very
low levels of intennodulation distortion, very good linearity and the conversion loss are
comparable to diode mixers.
Bipolar-junction transistors (BITs) are employed in Gilbert-cell multiplier circuit,
which is an extensively used doubly balanced mixer .. It is fundamentally a variable gain
amplifier.
2.2.3. Mixer Classifications
Mixers can be divided into several classes: single ended, single balanced, and double
balanced mixers. Depending on the circuit specifications, we can choose the
configuration which may be more suitable than the others.
2.2.3.1. Single-Ended Mixers
A schematic of a single-ended diode mixer is shown in, Fig. 2.3 which illustrated a
single-device. Despite several serious limitations, they are widely used in many systems
(especially in microwave and millimeter-wave frequency range) because of their
20
simplicity of design and adequate perfonnance [22]. Since RF and LO are injected into
the same port, it is difficult to isolate RF, LO, and IF signals, which is the main
disadvantage of singie-end mixers.
D
RF LOIRF DipIexer o. IF Filler
S
-to -
Fig. 2.3 A singie-device FET mixer.
2.2.3.2. Balanced Mixers
(a)
21
D4
1
4
Filter
IF
IF 1-
2
D2
(b)
Fig. 2.4 (a) Realization of single balanced diode mixer using the transformer. (b) A
double balanced diode mixer using the transformer hybrid.
Balanced mixers overcome the problems of single-ended mixer and offer some
additional advantages. They exhibit better power handling capability, and also increased
suppression of LO noise and spurious signals [28], increase the inherent RF-to-JF
isolation of the polarity-switch mixer. Second, the RF and LO are inherently isolated. A
balanced mixer also rejects the AM noise from the LO source, and rejects certain spurious
responses.
The two basic balanced mixer design topologies, shown in Fig. 2.4, consist of singly
balanced and doubly balanced configurations. Because the input power is divided
between multiple devices, the power handling capability of a balanced mixer is invariably
better than that of a single-device mixer. Unfortunately, the LO power is divided between
the diodes as well, so the LO power requirements are commensurately greater. An
important advantage of double-balanced configuration is inherently low even-order
intermodulation.
:U.3.3. Gilbert CeU Mixers
The mixer shown in Fig. 2.5 is essentially an active double balanced mixer
employing bipolar or MOSFET transistors. This circuit has several attractive features
such as conversion gain, low LO power. monolithic integration capability and good
isolation.
22
La
RF
RF
IF IF
'-DC SRC1 1dc=1 rnA.
ap pn_2N1711_19930601 Q2
Fig. 2.5 Circuit schematic of a Gilbert Cell mixer.
The Gilbert Cell mixer operates as follows. In the absence of any RF signal there is
no voltage difference between the bases of Q I and Q2 and the collector currents of these
two devices are equal. Thus a voltage applied at the LO inputs result in no change in the
output current. When an RF signal is applied to the bases of Q I and Q2, and there is no
voltage difference at the LO port, the output likewise will be balanced and no IF output
will be present. If there is any small offset voltage present at the RF port when the LO is
present it would only result in small feed through of the LO signal to the IF output, which
will be rejected by the IF filters. Similarly, if there is any small offset voltage present at
the LO port when RF signal is present, it would only result in small feedthrough of the
RF signal to the IF output, which will be rejected by the IF filters. It is only when a signal
is applied to both the RF and LO ports that a signal appears at the output. Since both LO
and RF powrts are differential , the Gilbert cell mixer is a double balanced mixer.
23
2.2.3.4. FET Resistive Mixers
FET passive resistive mixer is using a linear time-vary channel resistance for
frequency conversion as a mixing element. Most commonly it is implemented as a
double-balances resistive ring. It is the best topology for low distortion performance, and
requires moderate LO power [20]. The LO is applied to the gate and no de bias is applied
to the channel, and the LO voltage modulates the depth of the depletion region, which
varies the channel resistance so that the FET serves as a gate-voltage-controlled resistor
[20]. When the RF signal is used to apply the drain-source current, the drain-source
voltage is the RF current multiplied by the channel resistance. Since the channel
resistance is very close to linearly proportional to the gate voltage at small signal voltages,
this produces a very linear mixer, with the output voltage proportional to the
multiplication of the LO and RF signals. FET resistive mixers have much lower levels of
intermodulation than diode or active FET mixers [20]. The conversion loss and required
LO power of resistive FET mixers can be comparable to that of diode mixers [17].
We witt examine the MOSFET passive mixer in detai1. The channel resistance of a
MOSFET, will vary with the LO signals applied to the gate of the devices. Because LO
voltage modulates the channel resistance by changing the depth of depletion region under
the gate resulting in the change of channel resistance, which can be indicated by the
approximation when vtb is very small:
id = P.C .. W [(v8J -vth)vtb -.!.Vtb2] L 2
.................................•........ (Eq.2-4)
Without any biased voltage at gate, the channel resistance is ideally infinite; when
24
the gate biased voltage is increased, below threshold voltage, the device is operating in
near-threshold region. In this case the channel resistance is decreased, which enables the
mixer achieve better conversion loss at very low LO power. The channel resistance is
dependant both on the gate bias and the LO power.
In order to separate the RF from the IF and to prevent LO leakage from activating
the drain conductance, the appropriate filtering is required. The matching circuits at RF
and IF ports should prevent significant LO voltage from being coupled to the drain, and
the gate should be short-circuited at the RF frequency to prevent the RF voltage from
introducing nonlinearity by varying the channel conductance.
if "
n RF
Fig. 2.6 Schematic of a double-balanced passive FET mixer.
Fig. 2.6 illustrates the basic configuration for a double-balanced FET mixer. The LO
is applied to the gates through a transformer, and the RF is applied to drains in phase. All
25
four comers of the ring are virtual grounds for the LO; the IF and RF connection points
are virtual ground for the each other, and the gates are virtual grounds for both RF and IF
which implies that RF, LO and IF are well isolated.
2.3. Theoretical Analysis of Mixer Design
Due to the low distortion, low l l f noise, and relatively low conversion loss, we
choose the topology of a double-balanced resistive ring to design the mixer in the system
of heart rate extraction using Doppler radar. The mixer performance was simulated using
Agilent ADS software with BSIM3v3 transistor models.
2.3.1 Selection of Device Size
... ...
~ jFT .f r-""', --, ... - .... -"'""' .............. "" . ........... -tP.IIf. ,. ....... ,.- ' .... ot.I'If'GHo
~J I ..,."-,, .rs M II
~ ' I- • • -'1' -, _., ~ Fi~'os .,.,,' -- "'OIIffl
...".,.~~, .lO. _lOJ ~_lOGHI
,~ .t-II
-I. ~ ' I-]. ~ ..... ,~ , -- __ rv_~ ~M_ ""~ ... " ............. 1000(I' _LO __ ~"OI
~LOO'"
[ ]~~ [ f ,--~ ,.M_ ~M_
- -
,-
-- " ,
Fig. 2.7 The ring configuration for selecting device size.
26
Conversion Loss Vs. Device Size 30 I I
co ~ 25
'" '" 0
rri1 - irldep(qn 1 )=180.000
plot vs(Conversion Loss, W)=13.,616 -J C 20 0 'Vi ~
C1> > 15 c 0 U
-
1 -~-- m1 I y t
I 10
I I I 30 60 90 120 150 180 210 240 270
Device size (urn)
Fig. 2.8 Conversion loss as a function of device size.
For the first step of mixer design, the device size is selected to yield the lowest
conversion loss. Without the matching the network at LO, RF and IF ports, the LO and
RF signals have been directly applied to the MOSFET double balanced resistive ring
structure. Fig. 2.7 shows the ring configuration to select device size. The conversion loss
as a function of device size is shown in Fig. 2.8, which indicates that when the width of
the device is 180 ~m, the conversion loss reaches the minimum value. After the device
size has been determined, the matching networks have been designed in the next step.
2.3.2 The Theoretical Verification of the Improvements of
Conversion Loss Applied by A Small DC Gate Biased
Voltage
In order to examine the relationship between conversion loss and the small gate bias
voltage, a design of passive mixer without any biased voltage applied at gates was
demonstrated here. After the optimum conversion loss has been achieved, a small gate
biased voltage has been applied to the gate to see if the conversion loss can be improved
27
at very low LO power.
Fig. 2.9 Schematic of the passive mixer without any gate biased voltage
The matching networks have been designed across 2.20Hz to 2.6 OHz. Fig. 2.9
shows the schematic of the passive mixer design, with a NMOS size of 180flm. The
resistors at LO and RF ports are used to obtain the good matching at each ports. The
return loss at LO and RF ports, is shown in Fig. 2.10. Both good RF and LO matches are
obtained, the return loss are higher than 10 dB within the frequency range.
Fig. 2.11 and Fig. 2.12 illustrate the conversion loss as a function of RF frequency,
and LO power, respectively. The conversion loss is 6.776 dB at a LO power of 10 dBm,
and within the frequency range of 2.20Hz to 2.60Hz, the conversion loss varied 3dB. At
very low LO power, the conversion loss increased tremendously under the condition
without any gate bias voltage, dropped to 10.9 dB and 72 dB at a LO power of OdBm and
28
-10 dBm.
iO ~
'" '" o -' c: o I!! Q) > c: o ()
iir f-----'~--
.... .,:===:::::::::::::::::'.--, .• ~ . ;15
iir f ·» .• INq, GHr
\f f----+----I
.• i = .•
Fig. 2. 10 The return loss at LO and RF port, respectively.
Conversion Loss Vs. RF Frequency 10-,------------------------------,
9
8
7 m1 ~
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60
RF Frequency (dBm)
m1 f RF=2 .400 ConvLoss=6.766
Fig. 2.1 1 Conversion loss (dB) as a function ofRF frequency (GHz) without bias.
29
Conversion Loss Vs. LO Power 140
~
120 -----CD "0 ~
<II 100 ~ m3 --' 80
m3 P LO dbm=-10.000 ConvLoss=72.850
m2 c 0 60 'iii ~
P LO dbm=O.OOO ConvLoss= 1 0.971
Ql 40 > c
m2 0 m1 0 20 T -~ 0
m1 P LO dbm=10.000 ConvLoss=6.766
-40 -30 -20 -10 0 10 20
LO Power (dBm)
Fig. 2.12 Conversion Loss as a function ofLO power without bias.
Based on the passive mixer without any bias discussed above, a very small gate
voltage of 0.45V (below threshold voltage which is 0.48V for the model) has been
applied to the gate. Without any matching network, the S-parameter simulation results of
the ring transistors only without and with gate biased voltage have been shown in Fig.
2.13 and Fig. 2. 14, respectively. After the comparison, we can tell that it doesn't change
much at LO port, but status changed a lot at RF port since the channel transistances
changed because channel has been conducted.
m' freq- 2.400GHZ. S{1, 1)-0. 960 1-44.477 impedance :0= ZO • (0.069 - j2.444)
<> M f---------I ... Mf--------
tlq (221X1GHz ~2SXIGHz)
Fig. 2.13 S-paramter simulation at LO and RF ports of the ring structure without bias.
30
m1 freq=2.400GHz 5(1.1}=O.971 1 -51 .051 Impedance· ZO' (0.079 - .12,092)
~ 1-----------1 :l l----------'"
1I'eq (2 200GHz tl2.l5OOGHz)
m2 T
tCICI (2200GHr: kl2l!OOGHz)
m2 req=2,400GHz Si:.~J:". 657 I "~ .• ~3 imptNi:.nce • ZO " \ 1.001 - jl .744)
Fig. 2.14 S-paramter simulation at LO and RF ports of the ring structure with a small gate bias of 0.45 V at gates.
After new matching networks were obtained at RF and LO ports with a small gate
biased voltage of 0.45V, the return loss is indicated by Fig. 2.15. The figure shows very
good matching across 2.2 OHz to 2.60Hz at both LO and RF ports, much better than the
results without any biased voltage at the gate.
The conversion loss was examined as a function of RF frequency and LO power,
respectively, illustrated by Fig. 2.16 and Fig. 2.17. We can tell that after a small gate
biased voltage of 0.45 V was applied, the conversion loss has been improved
tremendously at very low LO power. The conversion loss is 6.29 dB at a LO power of
10dBm, 6.76 dB at a LO power of 0 dBm, 8.69 dB at a LO power of -10 dBm. Compared
with the results without any biased voltage at gate, the conversion loss increased a lot less
in this case. And within the frequency range from 220Hz to 2.60Hz, the conversion loss
varies smaller than IdB.
J I
m1 i f----4 ---
• f-------'1!'-------5i
freqoo2.~ 5(1,1 )-0.027/159.-493
T~~~~·~·~ro~· (~O.,~~~.p~.O~'''L-, ." .• ·N
'''' "" Fig. 2. 15 Return Loss at LO (left) and RF (right) ports with a small gate biased voltage of 0.45Y.
10 ~ -co
9 '0 -~
<f) -<f) 0 8 ....J -c 0 <f) 7 -~
<l> > c 6 0 0 -
5 •
2.2
Conversion Loss Vs . RF Frequency
r --
~~ r
I t
• I • • I I I I ( I ( ( I I
2.3 2.4
RF frequency (GHz)
m6 indep(m6)=2.400
2.5
plot vs(ConvLoss , f RF)=6.296
2.6
Fig. 2.16 Conversion loss as a function of RF frequency with a small gate biased voltage of0.45Y.
32
Conversion Loss Vs. LO Power 35
m5 iD 30
~ P LO dbm=-10.000 ~ ConvLoss=8.946 III 25 '-, .§
~'" m4
.§ 20 P LO dbm=O.OOO ConvLoss=6.758
~ 15 m5 m3 0 10 () P LO dbm=10.000
5 ConvLoss=6.296 -40 -30 -20 -10 0 10 20
LO Power (dBm)
Fig. 2.17 Conversion loss as a function of LO power with a small gate biased voltage of 0.45V.
2.4. 2.4 GHz Resistive Ring Mixer Design
2.4.1. Schematic of the mixer
Mixer was designed for RF center frequency of2.4 GHz, assuming low IF frequency.
Fig. 2.18 shows the circuit schematic topology used for the 2.4 GHz mixer. The NMOS
device size was selected to yield lowest conversion loss, resulting in device size of 180
1l1ll. The LC networks at RF and LO ports were designed to provide 50-a wideband
matching ranging from 2 to 3 GHz, dc blocking and isolation improvement. All parasitics
were taken into account during simulation, including the substrate series resistance. The
inductor model included quality factor Q, which is set to 7.
The parameters of transistor have been given by the following equations,
Ad = E·(W /2).10-12 ......•.••....••.•. (Eq. 2-5)
A, =E·(W / k)-(k/2+1).10-12 .............. (Eq. 2-6)
33
~ =k·(Wlk+E).10-6
P, =k·(W I k+E).10-6
Nrd=(k·E)IW
Nrs=(k·E)IW
..•.•.......... (Eq.2-7)
........••.... (Eq.2-8)
..•.....•..... (Eq.2-9)
.........••... (Eq.2-10)
where A.J is drain area, As is source area, P d is drain perimeter, P 8 is source perimeter, Nrd
is drain squares and Nrs is source squares. Here E and k are constants, which are equal to
0.6 and 12, respectively. Using the equations from 2-1 to 2-6, the physical characteristics
of transistors have been determined.
IF+
~ C7 f-j\JoO
0 Bias ~
~ Yo
~o
C1 C2 L4
LO+>>--l 1---« RF+
~~1d L3 C5
C3 C4 L2
"" L5 C6 0' Bias
1---« RF-C8 f-j\J4J L6
liI ""0
IF-
Fig. 2.18 Schematic of mixer.
34
2.4.2. The relationship between Conversion Loss and DC Gate
Biased Voltage
12-.------------------,
4"or~Tr~Tn~nn"nn"nn"rrrl 0..0. 0.1 Q.2 0.3 0..4 0.5 0..6 0..7
DC gate bias voltage (V)
Fig. 2.19 Conversion loss as a function of DC gate biased voltage for LO power of 10
dBm
16,~-----r----,_----,_--_,----,
-40 -30 -20 -10 o 10
LO Power (dBm)
Fig. 2.20 Conversion loss as a function ofLO power with (solid line) and without (circles) gate bias voltage.
Fig. 2.19 illustrates conversion loss as a function of gate-bias voltage below the
threshold voltage when LO power is fixed at 10 dBm. The conversion loss reaches its
minimum value of close to 5.8 dBm when the gate is biased at 0.45 V. Fig. 2.20 shows
3S
the relationship between the conversion loss and LO power with (solid line) and without
(circles) gate bias voltage when RF power is set to -40 dBm.
Comparing these two curves, there is a dramatic improvement in conversion loss
when a small gate bias is applied for LO power below 6dBm. For example, for LO power
of 0dBm, conversion loss decreases from over 50 dB to below 10dB due to the gate
biased voltage. For LO power below -20 dBm, conversion loss improvement is as high as
90 dB. Therefore, by applying a small gate biased voltage, a significant improvement in
conversion loss can be achieved for low LO power levels. When the gate is biased at a
voltage around 0.4V (slightly lower than 0.48 V that causes channel conduction), the
trsnsistors are operating in the sub-threshold region, which enables the passive mixer to
achieve good conversion performance. Additionally, since the bias voltage is applied to
the gate rather than the drain or source, there is no power consumption resulting from the
gate bias voltage.
2.4.3. Mixer Performance
2.4.3.1. Return Loss
Fig. 2.21 illustrstes LO (a) and RF (b) return loss, associated with (c) S-parameter
simulation for frequency range of 2-3 GHz. The LO return loss is lower than -10dB in the
frequency range of 2.3 to 2.5 GHz. The RF return loss is lower than -10dB for a
frequency range of 2-3 GHz. We can tell the mixer I designed has very good wide band
matching characteristics at RF port. This broad-band RF and LO performance makes the
mixer suitable for a wide range of applications.
36
LOPort
.. 2.0 2.2 2.4 2.0 2.8 3.0
Fmquenqr(GHz)
(a)
RF Port
·1
2.0 2.2 2.4 2.8 2.8 3.0
Frequency (OHz)
(b)
~I-----f-------'
I~ ~ I-------=~-----I
LOPort RFPort (e)
Fig. 2.21 Return loss at (a) LO port and (b) RF port as a function of frequency (c) S-parameter in LO and RF port, respectively
37
2.4.3.2. Conversion Loss
18
m 16 :&
~ 14
...J 12 c
-,-- -
.Q 10
~ 8
<3 6
4
2.0 2.2 2.4 2.6 2.8 3.0
RF Frequency (GHz)
Fig. 2.22 The conversion loss as a function of RF frequency for LO power of 1000m (circles), OdBm (crosses), -IOdBm (squares).
Fig. 2.22 shows the mixer conversion loss as a function of RF frequency from 2
GHz to 3 GHz for IF frequency of I kHz. Conversion loss is shown for LO power of
10dBm (circles), 0 dBm (crosses), and -10 dBm (squares). As indicates, this mixer has a
very slight change of conversion loss at a LO power of 10 dBm in a wide band. The
conversion loss reaches the minimum value of 5.8 dBm at 2.4 GHz, and increases by less
than I dBm from 2 to 3 GHz. The conversion loss at LO power of 0 dBm slightly
increased to 6.3 dBm, and it reached 8.8 dBm at LO power of -I 0 dBm at 2.4 GHz.
2.4.3.3. Input P1dB , llP2 and IIP3
The mixer not only performs well at a wide bandwidth from 2 to 3 GHz, with a
relatively small variation of conversion loss, but also shows good linearity.
The IdB compression point is the point where the gain of the circuit has dropped I
dB from it small signal asymptotic value. At the I dB compression point, the output
38
power of the fundamental crosses the line that represents the output power extrapolated
from small-signal conditions minus I dB.
The input PI dB of 10 dBm, shown in Fig. 2.23 is obtained at 2.4 GHz with a LO power of
10 dBm. Fig. 2.24 illustrates the situation of input P I dB at a LO power of IOdB without
any gate biased voltage. At this time PldB is close to 9 dBm, which has a minor
difference with the case applied by a small gate voltage of O.4Sy. After the comparison,
the linearity characteristic changes very slightly with and without biased voltage at the
gate.
P1 dB (LO Power=1 0 dBm) 30
;[ 20
~ 10
$ 0 ~ ~ ·10
·20
-- ~.~ .....
-7~ ,.....,...
~ - L -,.....,...r I , I I I 'I '
·20 ·15 ·10 ·5 0 5 10 15 20
RF Power (dBm)
Fig. 2.23 PldB for LO power of IOdBm with a small gate biased voltage of O.4Sy.
m6 r-m~5--------------------------'
P _ RF _dbm - 9 .0 0 0 Indep(m5 )-g .OOO Mn •• r: 9 .39 8 10 v'(de m He 1 He .V I 1 ), HB 1.HB .P RF dbm - 8 .2 78
P1 dB
2 • .-------------------~~~~
E • i • ! ·2. ~
~
., . . ,. ·3. ·2. .,. • ,. 2.
RF Powe r (dB m)
eo mer.ulon 1 122 I
Fig. 2.24 PldB for LO power of 1 OdBm without gate biased voltage.
IlP2 (Input second-order intercept power) is the input power in dBm where the
39
fundamental output power and the second-order intermodulation output power are the
same. 1lP3 (Input third-order intercept power) is the input power in dBm where the
fundamental output power and the third-order intermodulation output power are the same.
In narrowband circuits distortion is commonly measured by applying two pure sinusoids
with frequencies well within the bandwidth of the circuit. Call these frequencies n and 12.
The harmonics of these two frequencies would be outside the bandwidth of the circuit,
however there are distortion products that fall at the frequencies 2n - 12, 212 - n, 3n -
212,312 - 2n , etc. These frequencies should be within the bandwidth of the circuit and so
can be used to measure the intermodulation distortion, or IMD, produced by the circuit.
Once an appropriate Pin is applied, the output intercept point is computed with
IPn=P+ P/(n-l) .... . . . ... . ... .. (Eq.2-11)
where IPn is the nth-order intercept point (dBm), P is the power in the fundamental in
dBm, and t. P is the difference between the desired output signal and the undesired
nthorder output product in dB. P is the input power Pin if iIPn is desired.
Spectrum NoIr" F Frequency
D,----m-,~--------------, ~-------.
·50
~ · ' 00- a ~ · ' 50-
· 200
. ,. 0.6 1.1
fIr rn ., . 1.6 ' .1 ' .6
freq. KHl
IP2& F3
0"
59.4261
m3
TI 3.1 3.6 4.0
0'3
23.6761
Fig. 2.25 lIP2 and lIP3 of the double balanced ring mixer with a small DC gate biased voltage of 0.45Y.
40
Speclrun Near F Frequency o
m1 1 1, II-
~ I -
m3 freq=3. 150kHz dBrr(Vif)=-154.759
m2 freq=2QO.0 Hz dBrr(Vif)=-128.702
·50
~ ·100
E ·150 In
" -
• I
m1 freq=95O.0 Hz dBrr(Vif)=-46.897
·200
·250 0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.0
freq . KHz
11P2 &.,3
11P2
47.814 1
11P3
19.9391
Fig. 2.26 I1P2 and lIP3 of the double balanced nng mixer without DC gate biased voltage.
From Fig. 2.25, the input IP2 and input IP3 are of23.6dBm and 59.4 dBm obtained
by simulation, respectively, under the condition that a small gate biased voltage of 0.45 V
has been applied. Fig. 2.26 shows that the IIP2 and IIP3 without any DC gate biased
voltage are 19.9 dBm and 47.8 dBm respectively, at a LO power of 10dBm.
2.4.3.4. lff noise
Flicker noise in the mixer of a low-intermediate frequency (IF) wireless receiver can
compromise overall receiver sensitivity. Passive mixers could exhibit internal 11f noise,
even when used in AC coupled configuration. Fig. 2.27 and Fig. 2.28 illustrate the 11f
noise simulation results with and without gate biased voltage, whi le RF ports of mixers
have been tenninated to 50 Ohms load and LO ports have been applied by a LO power of
10 dBm. From the comparison, the IIf noise dropped slightly when the small DC gate
biased voltage is removed. When the small DC bias is applied to the gates, although the
RF drain current is very small, I/fnoise is increased as comprade to the case without bias.
If the LO drive is very large in order to achieve high linearity, the overlap capacitances
41
can couple significant currents into the drain circuit resulting in higher I l f noise.[22]
5E-8
4E-8-
-Ql
3E-8-<Jl '0 c -
....: 2E-8 -:> 1E-8-
-0
0 I
100
I
, I ' , I 200 300 400 500
noisefreq, KHz
Fig. 2.27 IIf noise of passive mixer with a small DC gate biased voltage of 0.45Y.
1.0E-8
8.0E-9 -
t - -
Ql 6.0E-9 <Jl '0 C ~ 4.0E-9 >
- -
j .-
- .- c- --
2.0E-9 - t '-0.0 , , , I ' , , I
o 100 200 300 400 500
noisefreq. KHz
Fig. 2.28 I l f noise of passive mixer without DC gate bias.
2.4.4. Mixer Layout
All the components in Fig. 2.18 are integrated on chip. Fig. 2.29 shows the chip
layout of the 2.4 GHz resistive ring mixer. The size of the chip is 1.24 mm x 0.8 mm, and
the chip was submitted for fabrication in 0.25-~m CMOS TSMC process. Considering
42
that the high sheet resistance of the poly-silicon layer can significantly affect the
conversion loss, the layout was carried out to minimize the parasitic series resistance
within the device. The total device gate width of 180 11m is arranged to minimize the
parasitic resistances by separating into 15 instances that each one has a size of 12 11m ..
Also, terminal to terminal and substrate to temlinal parasitic capacitance have to be taken
into account.
Bias
LO IF
GND RF
Fig. 2.29 Layout of the mixer. Chip size is 1.2rnm x 0.8 rnm.
The passive integrated components required for RF designs are typically
compromised by parasitic capacitances, inductances and resistances that are significant at
RF, and they often take up a large percentage of the area on RF die. Inductors are
necessary in RF designs, while they are not needed in most analog or digital integrated
circuits. Even with an optimized design, the parasitics have a great effect on these
43
inductors, limiting the achievable quality factor Q to between 5 and 10. The quality factor,
Q, is defined as the angular frequency multiplied by the ratio of the energy stored to the
average power dissipated. A second type of passive component, the on-chip parallel plate
capacitor, cannot avoid the substrate acting as an extra plate and therefore adding
unwanted parasitic capacitance. Additionally, because the distance between metal layers
does not change as technology scales, capacitor size does not scale with transistor size
and the capacitors take up a greater proportion of the die area [22).
Parasitic capacitances have to be taken into account. Since low parasitic capacitance
within the device is important to minimize LO signal leakage pumping the drain
conductance of the device [20), great care bas to be taken to minimize the parasitic
capacitance within the NMOS device.
General parasitic circuit resistance is minimized by using thick inductor metal for
inductors. I also made smaller value capacitors array to minimize the series resistance of
the DC blocking capacitors on LO and RF ports.
2.5. Chip Measurements
The chip was fabricated in 0.25-J.Un CMOS TSMC process. Return loss bas been
tested by measuring one port while terminating the other five ports by 50 Ohms load. The
frequency range is from 0 to 100Hz. Fig. 2.30 shows the snapshot of the passive mixer
on chip, and each ports have been labeled.
Fig. 2.31 shows the return loss at each port of the mixer on chip. The return loss at
RF ports of the mixer shows very good broadband matching characteristics, which is
44
consistent with the simulation results. Within a wide band frequency from 20Hz to 80Hz,
the scattering parameter is lower than -10 dB. The return loss reaches maximum at a
frequency of2.58 OHz instead of2.4 OHz, showing a frequency shift due to the parasitic
capacitances or inductances of the layout.
Bias Bias
Fig. 2.30 The photograph of the passive mixer on chip. Chip size is 1.2mm x 0.8 tum.
At LO ports, the value of S-parameter keeps going down at a frequency range of
0-70Hz, exhibiting an obvious center frequency shift. The reason why the center
frequency shifts a lot is because there are four large inductors at LO ports. On the layout,
the spiral topology of the inductor I drew has relatively small center hole, resulting in less
inductance than predicted.
45
IF
IF
At IF ports, the return loss is very similar with that of simulation results. Since the
IF outputs will be connected to the high input impedance preamplifier described In
Chapter 3, the good performance is not required here.
The mixer I designed is supposed to be connected with external baluns while testing
the chip. Thus we use two baluns with a frequency range of2GHz to 8GHz at RF and LO
ports. One IF port is connected to the spectrum analyzer, and the other is terminated with
50 Ohms. Fig.2.32 shows the measurement setup. Before mixer was tested, the loss due
to the cable and balun at different frequency were measured first, and was compensated
into LO and RF power in order to calculate conversion loss conveniently.
After sweeping IF frequency from I KHz to 500Mz, the IF frequency is fixed at 100
KHz" and LO and RF frequencies are adjusted accordingly. Thus, the center frequency of
RF, LO and IF ports are 2399.9 MHz, 2.4GHz, and 100KHz. The IF frequency shifts
resulting from the center frequency shift at LO ports. The input power level at RF and LO
ports are set to -40dBm and 10dBm, respectively, after compensating the loss at different
stages.
Return Loss at RF port (Vg=0.45V)
5
CD 0
~
'" -5 '" 0
...J c -10 :; -Q)
0:: -15
-20
0 2 4 6 8 10
F reque ncy (GHz)
46
Return Loss at LO port (Vg=O.45V) 5
t 0 + iil ~ -5 <IJ <IJ 0 -10 -' E :::l -15 -Q)
a: -20
-25
0 2 4 6 8 10
Frequency (GHz)
Return Loss at IF Port (Vg=O.4S) -1 .5
iil -2.0 "0 ~
<IJ
t
<IJ 0 -2.5 -' c ~
:::l -Q) -3.0 a::
-3.5
0 2 4 6 8 10
Frequency (GHz)
Fig. 2.3 1 The return loss at each port of mjxer.
Balun Balun 2GHz-8GHz 2GHz-8GH z
RF LO Signal In
1 1 In Generator 2 2
RF LO ~ ~
V> .-0 ~.g' 80 E!.R "-9" ~ ~
Fig. 2.32 conversion loss measurement setup for test of chip.
47
Conversion 1oss= PRF- PIF
RF Port R" ...... ~.s.p;;;~;~ ... ""'.s ..... ~£ IF Port
6 10SS
LOPort
Fig. 2.33 The power level at different stage of measurements setup.
Fig. 2.33 demonstrates the power level we should measure in the whole system in
order to calculate conversion loss since the loss from devices, cables are required to be
considered. Table 2.1 lists the power level we measured at different positions at 2.4 GHz,
under a gate biased voltage of O.4SV, which is illustrated by Fig. 2.33
Table 2.1 Power level at different positions.
Position Power (dBm)
PIN
POUT
PRF
PIF
PLO
-37.64
-52.48
-40
-52.445
12.36
Thus, conversion loss of the mixer can be given by
ConversionLoss = P RF - PlF = -40 - (-52.445) + 3 = 9.445dB
where Pw = 12.36dBm'PRF =-40dBm.
(Eq.2-12)
Compared to the simulation results, the conversion loss is 5.8dBm at a LO power of
10dBm and RF power of -40 dBm, with a DC bias ofO.4V at gates. The conversion loss
measurement is 4dB higher in the measurements than the simulation results.
48
Conver sion Loss vs. Ga te Bias
"" 35 3 30
"-Vl 25 Vl '\. 0 ~ 20 ""'- --Conversion Loss <= 15 ./ Gate Bias 0
""""'- ~ vs.
''';
Vl 10 h ..... Q)
> 5 <= 0
0 ,
u
0 O. 2 0. 4 0.6
Ga te Biased Voltage (V)
Fig. 2.34 The measurement results of conversion loss as a function of Gate Biased voltage.
Fig. 2.34 shows the measurement results of conversion loss as a function of gate
biased voltage from 0 to 0.7 V. The threshold voltage of the transistor is O.48V, and the
conversion loss is minimum at a small DC gate biased voltage of 0.45V, which has a
conversion loss of9.445dB. Without bias, the conversion loss will increase to 30 dB.
Convers i on Loss Vs. LO Power
~ 35 c::> '-"0 30 ~
Vl 25 '" Vl
"'-0 ~ 20 -- Vg=0. 45V <= 15 '- ...... 0 ......... • --- Vg=O . ..; Vl 10 h Q) > 5 <= 0
0 u
- 30 - 20 - 10 0 10 20
LO Power (dBm)
Fig. 2.35 The measurement results of conversion loss as a function of LO Power
Fig. 2.35 illustrates the relationship between conversion loss and LO power, with
49
and without biased gate voltage in measurements. The conversion loss drop to ISdB and
23dB at LO power of OdBm and - IOdBm, much higher difference with the simulation
results, which is around 3dB. Under the condition without gate biased voltage, the
conversion loss is much larger, and IF signals only can be detected at higher LO power.
Convers ion Loss Vs. RF Frequency
@ 30 -0 ~ 25
Vl Vl 20 - -- LO Power : IOdBm 0 --' -c 15 -- LO Power :OdBm 0
""" -.... 10 I· LO Power :- IOdBm Vl .... "'"
'" 5 > c 0
0 u
2 2.5 3 3. 5 4
RF Frequency (GHz)
Fig. 2.36 Measurement results of conversion loss as a function ofRF frequency
The measurement results of conversion loss as a function of RF frequency has been
shown in Fig. 2.36. The conversion loss doesn't change much across the very wide band
from 2GHz to 4GHz, at LO power of IOdBm, OdBm and -IOdBm. Moreover, the trend of
conversion loss keeps dropping till 3.6GHz, which obtains the minimum value of7.3 dB.
The measurement results demonstrate that the conversion loss varies gradually with a
small DC gate biased voltage, much less than the case without any bias at gate.
P IdB, IIP2 and TIP3 were measured to examine the linearity of the mixer. Fig. 2.37
shows the PI dB measurement results. The conversion loss suppressed I dB at around
4dBm,which means IdB compression point is 4dBm which is obtained at a LO power of
IOdBm and a gate biased voltage ofO.4SY..
50
~5 -35
2f1-f2 fI
Pin
-25 -15 -5 5 15
AdBm-
K •
Input Power [dBm]
Fig. 2.37 PldB
f2 2f2-f1
Fig. 2.38 The third-order intercept power
o Iii' ;E.
-5 :a .3
-1 0 I: o 'jij
-15 ~ I:
<'3 -20
The third-order intercept power is achieved by applying two RF excitations by use
of a 0- degree power splitter, with 2KHz difference between the fundamental
frequencies,99 KHz and 10 I KHz. The second-order hamlonics occurs at a frequency of
fRF-0.5flF, which is 202.95 KHz with a power of -71.83dBm.The third-order hamlonics
at 2f1 -f2 and 2f2-f1 are obtained at 98.22 KHz and 104.7 KHz, respectively, with a power
of -81.99dBm and -81.18dBm. The measurement results on linearity are listed in Table
2.2, which demonstrates that IIP2 and IIP3 are 33.936dBm and 7.674dBm. Comparing
with simulation results, the linearity is not what it has been expected.
Table 2.2 The measurements results on TIP2 and TIP3
IMeasurements:
51
IF sIde: 1kHZ IdBm 1 100.~ -31.31 2f1-f2 98Z -81.9S 2f2-f1 104. -81.1S r.z 102.m -31.4li I2RF-2LO 202.9f -71.~
[RF-IFI2 239989861 -40.4~
lSummary of Results for IIn~ 1P2 33.93.ti [dBm IPS 7.673 [dBm P1dB ~ [dBm
2.6. Conclusions
This chapter proposes the design of a resistive ring mixer, which was fabricated in a
0.25 II m CMOS TSMC process, operating in the near-threshold region. Both simulation
and measurement results have demonstrated that the conversion loss at very low LO
power levels could be improved tremendously by applying a small gate bias voltage.
The mixer achieves a conversion loss of 7 dB at 3.6 GHz, with low RF insertion
loss in the frequency range of 2-8 GHz. The conversion loss degrades by 14 dB for ill
power in the range of 10 dBm to -lOdBm which shows the conversion loss under very
low LO conditions are improved by over 85 dB by applying a small gate bias. The
linearity of the mixer represented by PldB.DP2 and IIP3 are 4dBm, 34 dBm and 7.7 dBm
from the measurements.
The output of the mixer will be connected to the preamplifier, which will be discussed in
Chapter 3.
52
Chapter 3
3. Analog Signal Processing
A typical BCG signal ranges from O.S mV to S mY, combined with a high dc offset
[29], and the average signal level of Doppler mixer output is also of the same order [30].
Thus, the pre-amplifier must be able to provide enough gain, remove dc offset, and reject
out-of-band noise. The requirements of the preamplifier are: gain = Soo - 10000,
bandwidth = 0.1 - SO Hz, high input impedance, and low output impedance to drive latter
stages. In this Chapter, pre-amplifier design and proto-board and PCB implementation
will be discussed.
3.1. Review of Previous Preamplifier
The preamplifier designed by Mingqi Chen consists of four stages, high pass filter,
instrumentation amplifier, differential-mode low pass filter and amplifier with
T-embedding network, which is indicated in Fig. 3.1.
The high pass filter (HPF) blocks DC and the first order HPF is enough. The cut-off
frequency is 0.1 Hz.
The previous design employs the differential input single-ended output
instrumentation amplifier, which is widely used for precision amplification of differential
signals while rejecting large values of any common mode signals.
A low pass filter (LPF) has been combined into a common instrumentation amplifier
53
in order to save components and area. Since the instrumentation amplifier is of
differential-mode configuration, the 2-order LPF also needs to be differential-mode, with
a 3-dB frequency of approximately 50 Hz and the mid-band gain of250.
I a----
& ~dI ~
----------ot
I jtlll8,--~ !§ ~ ..fi...'<1 "NY
o 1- 'VI/v-
,
~,
... CD' G
&l~~~1iI
___ ----<I ~ L- ~ i~ ~ I I~o 5 j
Fig. 3.1 The schematic of the previous preamplifier
An inverting amplifier with T-embedding network is used to achieve high gain using
relatively small resistor, while maintaining relatively high input impedance and obtain a
high tuning range, while keeping the same resistance to ground seen by non-inverting and
inverting terminals of the op amp. The range of tunable gain is from 2 to 51. Therefore,
the overall mid-band gain is from 500 to 12750 (52dB - 83dB).
Fig. 3.2 shows the frequency response of PSpice simulation and experimental results.
The blue dashed line with triangulars is simulation result in PSpice and the green solid
line is experimental result of breadboard implementation [29].
EXpelin19ntal 118. Sirn.llation
1400r-----~~~----~::=*======~::~----~_r~~~~~1l I - ... ~ ~- Expelimental - SimJlation
1200
1000
800
600
400
200
~O~'~~~~~10~'--~~~~I~if~~~~~10~'--~~~-Ul0~2~~~~-I+~
Frequency (Hz)
Fig. 3.2 Frequency response in PSpice vs. breadboard implementation [29]
55
3.2. Improvements and Modifications
• • • •
• L-______________ ~ ~AA_~,
I I
i !
~ •• !
I •• _
.- §
I ~
'CJ:r
• • • • Fig. 3.3 . Block diagram of the new preamplifier
I made several modifications based on Mingqi's design and improved the
performance of the preamplifier.
The ultimate goal to design is preamplifier is to replace the Stanford Research
System (Model: SR560 Low-noise Preamplifier) with it, which has multiple options of
bandwidth and gain.
At the previous stage of the preamplifer, the preamplifier can be connected with the
RF circuits designed by my colleague, Shuhei Yamada [9] and the mixer [31] I designed
which was described in Chapter 2. The reactive part of the output impedance of the
circuits will change the frequency response of the HPF stage of preamplifier. Thus, one
voltage follower needs to be introduced at the front end, before the HPF, in order to
isolate the preamplifiers from Shuhei's circuit. After the modification, the DC voltage
level is much more stable than before.
Second, I added a DIP-6 switch to adjust the cut off frequency of the high pass filter.
The cut off high pass frequency can be O.IHz, 0.33Hz, 0.5Hz, 1Hz, 3.3Hz. Thus, the
pre-amplifiers not only have tunable gain but also have tunable cut off frequency.
Since the whole heart rate sensing system requires that the DC voltage level is under
control, I added one stage as DC shifter which enables the circuits to remove all the DC
level or to some extent.
Fig. 3.3 illustrates the new schematic of preamplifier after I made above
modifications. In sum, the preamplifier after improvements can meet all the requirements
of the experiments.
S7
3.3. Breadboard Test
3.3.1. Test with Real-time Figure Pulse Signals and ECG Signals.
First, the pre-amplifiers have been tested using real-time finger pulse signals and
EeG signals. The gain of the preamplifier was set to S2 dB (SOO VN) for the finger pulse
measurements and 77 dB (SOOOVN) for EeG signals test, respectively. And the
bandwidth of the preamplifier was set from 0.1 to SOHz.
Fig. 3.4 illustrates the comparisons between the outputs from our pre-amp Ii fiers and
Stanford Research Systems (SRS, Model No.: SRS60). The signal in green is the output
from the SR6S0 Stanford Research System, low-noise preamplifier, while the signal in
blue is the output from the preamplifier. This graph indicates that the pre-amplifiers can
get the similar signals using real-time finger pulse and EeG signals under the condition
of O'\ - SOHz bandwidth and S2- 83dB gain. Moreover, from Fig. 3.4, the signals from
preamplifier indicated in blue has lower noise floor.
:;: ,
J
., .}-----;;~---!----;';:---+-----;~---!----;';:----:! T .... (II
58
Fig. 3.4 Comparison between the output of the preamplifiers (blue) and SRS (Model No.: SRS60) (green) using real-time ECG signals.
3.3.2. Test the Pre-amplifiers with Coaxial-component Doppler Radar
System.
Preamp q
Signal Generator d[m]
2Way 0 degree
/ Power Splitter 1 ,--,r-, RFout_
LO
LO -l\1iJ~.r
lWay 90 degree II _rSpllller t=::
LO
Qout
RFin
-RFin
Ampllfiaotlon, -1 f-I DC block and Digitimtio AntI aliasing IDters. _ .
RFin
2Way 0 degree Power Splitter
Signal Processing
Fig. 3.5 The block diagram of coaxial-component Doppler radar system
Fig. 3.5 shows the block diagram of coaxial component Doppler radar system which
is used for testing preamplifier I made. Fig. 3.6 and Fig. 3.7 respectively show the outputs
of the preamplifiers and SRS (Model No.: SRS60) when connecting with the
coaxial-component Doppler radar system which includes O-degree power splitters,
59
circulator and mixers. The blue is the finger pulse signal as a reference and the green is
the output. The difference of the amplitude of the output waveforms is due to the
difference of the gain. Fig. 3.8 shows the comparison between the heart rate as a function
of time determined from the reference signal (yellow) and the output of the preamplifier
(red) using Labview.
1 -I --- IRS
~ , L
Fig. 3.6 Test result when connecting the coaxial-component Doppler radar with SRS (Model No.: SR560)
, - :; .... 1
• • • , 2
I \.\ Itl A ~ --. ...-, 'V I
2 \... ..... ~ ~ \I" ....-J " " " " "
Fig. 3.7 Test results connecting the coaxial-component Doppler radar with preamplifier
60
Fig.3 .8 Comparison between the heart rate as a function of time determined from the reference signal (yellow) and the output of the preamplifier (red) using Labview.
3.3.3. Test the Pre-amplifiers with Shuhei's Boards.
Fig. 3.9 Comparison between the heart rate as a function of time determined from the reference signal (yellow) and the output of SRS (Model No.: SR560) (red) using Labview.
Fig. 3.9 and Fig. 3.10 respectively show comparisons between the heart rate as a
function of time determined from the reference signal (yellow) and the outputs of SRS
(Model No.: SR560) and the preamplifier (red) using Labview. We can conclude that the
heart signals are consistent with the reference after FFT analysis in Labview.
61
Fig.3.10 Comparison between the heart rate as a function of time determined from the reference signal (yellow) and the output of the preamplifier (red) using Labview.
From the measurement results shown in this section, we can draw a conclusion that the
pre-amplifiers work very well with coaxial-component Dopplar Radar and Shuhei's board. Thus
we can replace the Stanford Research System with the preamplifiers in order that the whole
system is more portable and efficient.
3.4. PCB Implementation
The preamplifier implemented on breadboard has been tested and exhibits good
performance. However, all kinds of interferes and noise in the surroundings might affect
the performance of the preamplifier, therefore, I need to implement the preamplifier on
printed circuit board (PCB) to eliminate interferes and reach higher accuracy.
3.4_1. PCB Layout of the Preamplifier.
Fig. 3.11 The layout of the preamplifier (5 inches x 3. I inches)
62
The two- layer layout is done in ProteI 99 SE, with a size of 5 inches long and 3.1
inches wide, which is indicated in Fig. 3.11. The width ofwires I used for routing is 20
mils. On both top and bottom layer, I put ground layers with a track width of 10 mils, grid
size of20 mils, using 4S-degree hatching style and arcs surrounded pads.
After generating the Gerber file, a series of design files were export to a Wmdow
directory. Top layer gerber file notes that this file should have the comers marked with
crop marks. Bottom layer gerber file is represented by .gbl; drill report can be found
in .drr, and etc. The detail of gerber file has been shown in Table 3.1
Table 3.1 Gerber File Representation
.gbl bottom lsyer
.gbs bottom solder mask
.gbo bottom overlay (silk screen)
.gbp bottom paste
.gIro keep out
.gml mechanical 1 (board outline)
.gm2 mechanical 2
.gpl inner plane 1.
. gp2 inner plane 2 .
.gpb bottom pad master
63
.gpt top pad master
.gtp top paste
.gtl top layer
.gts top solder mask
.gto top overlay (silk screen)
The general information of printed circuit board, is shown in Table 3.2, the material
type we chose is FR4, the selected layers are 2; the finish plating plan we chose is leaded
free solder. Also, the copper weight of prototype is 1 oz, solder mask is needed for both
top and bottom layers in green. and the color of silkscreen is white, and the material
thickness is 0.03 1m.
Table 3.2 The General Fabrication Information for PCB of Preamplifier
MateriallyPe FR4
Layers Both top and bottom layers
Finish Plating Leaded Free Solder
Copper Weight (outer, finished) 10z
Solder Mask Sides Both sides
Solder Mask Color green
Silkscreen Sides Both sides
64
Silkscreen Color white
Material Thickness 0.031"
3.4.2. PCB Assemble of the Preamplifier.
The pictures of PCB of preamplifier before and after assembling are shown inFig.
3.12 and Fig. 3.13, respectively. The power supply is ± ISY. There are several options to
adjust the cut off frequency of high pass filter by selecting the one or two channels on
Dip-6 switch.
Table 3.3 lists the single channel and the combinations of any two channels which are
corresponding to different cut off frequency of the high pass filter.
But Table 3.3 only shows two combinations of the channels, since the capacitance
corresponding to channel 2 is huge. while channel S is very small compared to other
channel capacitance.
Fig. 3.12 The picture of the preamplifier on PCB before assembling.
65
Fig. 3.13 The picture of preamplifier on PCB after assembling.
Table 3.3 Corresponding cut off frequency ofHPF by channel selection
Channel Selection Capacitance (IlF) Cut off frequency (Hz)
Channel I I I
Channel 2 10 O. I
Channel 3.3 0.33
Channel 4 I I
Channel 5 0.33 3.3
Channel 6 Short Short HPF
Channel I and Channel 4 2 0.5
Channe l I and Channel 3 1.33 0.75
66
3.5. Test of Preamplltier PCB
The first measurement setup is shown in
Fig. 3.14. The hardware implementation is direct conversion Doppler Radar system
for heart rate extraction. The bandwidth of PCB preamplifier is from 0.1 to 50Hz. The
signal has been split into two ways to compare the performance of PCB Preamplifier with
that of Stanford Research System.
11m!
1 -_ ...... _lID
I"'''''''''''' ::. 1---I-oI-I-----C)c~}_----l
1-
Fig. 3.14 Measurement Setup I for PCB Preamplifier
The measurement results in time domain have been indicated in Fig. 3.15. The
original outputs from Stanford Research System and PCB preamplifier have passed
through the same band pass filter, and results shown in Fig. 3.16 demonstrate that the
67
PCB preamplifier can achieve similar signals wi th Stanford Research System.
Stanford Original AfterBPF
0.015 0.'"
0.01 0003 0.005 o,on
0
~.005 0.001
.Q.01 0
-0.01 5 -0.001
~.02
-0.025 ~.002
~.03 ..0.003
Original Preamp AfterBPF
0.'" . ."
0.002
.0" 0
.(l,001
~.002
~ . ." ~.'"
Fig. 3.15 Measurement results from Setup 1.
1- Stanford - PCB I 1.2
1
~ 0.8 ~ /"< f\ .!!; -JV ~ - ""'--J c;; 0.6 i!: ~ 0.4
0.2
0 1 4 7101316 19 22 25 28 31 34 37 40 43 46 49
Tlme[secl
Fig. 3.1 6 The comparison between Stanfo rd Research System and PCB Preamplifer.
Fig. 3.16 illustrates the comparison of outputs between Stanford Research System
and the PCB preamplifier, which exhibits a very good consistency between these two
68
series of R-R intervals in time domain, and demonstrates that PCB preamplifier can be
used to replace the SRS (Model No.: SRS60) for convenient and portable devices.
Fig. 3.17 shows the measurement setup n for ail the PCB preamplifiers I assembled. The
hardware system is quadratlD'e direct conversion Doppler Radar system with YQ outputs with 90
degree phase difference. Two PCB preamplifiers have been connected with IF port of mixer. Fig.
3.18 also indicates two PCB preamplifiers are consistent with each other, which can be used for
multi~hannel filtering, amplification and to remove DC.
Sigoa. Geaerator
Phase Shifter
2W ay 0 degree Power Splitter
11m I
RFoDt J
M or 2W., 90 de.n, I L~><J--::;==-_.J Power SpUtter L.::; , ~
LO RFID
Fig. 3.17 Measurement setup n for PCB preamplifier test
69
lW8,. 0 dea". Pow.rSpWter
1--Reference --Amp1 Amp2 1
2
- -
" \.----~ .... _) ~-_____ .--.-.l.-~ ... ---' .~
r,C __ . ---- .1., "
1.6 0' CII
.!E. 1.2
"' ~ 0.8 -c: 0.4
o ,
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58
Time[sec]
Fig. 3.18 The comparison between two PCB preamplifers.
The preamplifer can be integrated on a single chip, for example, using a CMOS
0.51!m process, except for the large capacitors. There are two large capacitors in high pass
filter, 3.3 pf and 10 pf, respectively, which are used to adjust high pass cut off frequency.
This will be a subject of further research.
3.6. Conclusion
This chapter presents a preamplifier with the tunable gain of 500-10,000 and the
tunable bandwidth of 0.1 , 0.33, 0.5, I and 3.3Hz-50Hz, which was implemented on a
proto-board as well as PCB. It can be connected to IF port of mixer discussed in Chapter
2 to amplif'y and filter the signals and remove the DC as required.
The preamplifier was tested using ECG, finger pressure pulse, and Doppler radar
signals, and it was demonstrated that it has a lower noise floor than a commercial
instrumentation low-noise preamplifier. This preamplifier can be integrated on a single
70
chip with the exception of two large capacitors.
71
Chapter 4
4. Digital DRV Monitoring System on Chip
Heart rate variability is a strong indicator of a number of medical conditions.
Current HRV systems typically determine R-R intervals from pre-recorded ECG signals,
which include a large amount of redundant data. A digital ASIC design for HRV
monitoring was introduced in [32]. The overall HRV system block diagram is illustrated
in Previous SoC block diagram. This HRV chip receives the digitized input ECG signal
through an ADC, processes and stores the RR interval data which can be transferred to
portable devices, such as Holter monitor via an off-the-shelf microcontroller. For test
purposes. or for further data processing off-line, the same interface can be used to transfer
data to a PC. This transfer protocol will enable communication between the chip and any
equipment (e.g., computers) with RS232 peripherals. A microcontroller and an ADC
could also be implemented on-chip to further reduce size and power dissipation.
Fig. 4.1 HRV monitoring system block diagram
In this chapter a more efficient HRV monitoring and assessm'IDt system on chip is
described. By applying digital techniques to store the difference between every two
72
adjacent R-R intervals in a single-port synchronous, high-performance SRAM, up to 24
hours of continuous ECG data can be stored on chip with a fixed resolution of I ms. The
system has been tested for functionality, synthesized and laid out in a commercial O.IS
11m CMOS process in a 2.5x2.5 mm2 hardware core with less than 155 11 W power
consumption. Such a system can enable HRV monitoring with home based healthcare.
4.1. Pre-existing HRV Monitoring System
Fig. 4.2 Previous SoC block diagram
Previous HRV Soc was developed in AMIS 0.51lm CMOS process [32]. The area of
the chip is about 3x3 mm2 with a power consumption of 1.5 11 W. Fig. 4.2 shows the
previous SoC block diagram. The system performs the four following functions: I) the
peak detector receives digitized ECG input and produces an output pulse one clock cycle
long each time it identifies a peak of a heart signal and such pulse is used to reset the
counter to start a new RR interval computation, 2) the RR interval counter writes the
previous content into the 12SxS register file (RF) tachogram memory, 3) the HRV
classifier categorizes the RR interval signals and increases the contents in the 16xS RF
histogranl memory, and 4) the control unit checks whether the tachogram memory is full
and then initiates a transfer to a serial port via a microcontroller. The system was
73
designed to receive 16-bit digitized ECG data sampled at 1 kHz, which is also the
frequency of the system clock. The tachogram and histogram both store 8 bits of
information per datum. Assuming that input ECG signal is sampled with a frequency of 1
kHz, the system provides ± 7 ms ofRR interval accuracy, which can be easily increased
to the maximum precision of 1 ms by employing a larger word width [32].
However, this SoC design has some limitations due to area constraints for the
memories, larger data widths were not feasible. Also, the accuracy of the data that is
being stored is highly reduced by the limited size of the memory. That is the reason
why we come up a new idea of designing a more efficient algorithm for SRAM to
overcome those problems and store long-term ECG signals with a fixed and high
resolution and accuracy.
4.2. Improved Design of System on Chip
4.2.1. Introduction
The significance of using heart rate variability (HRV) measures as important
quantitative indices of cardiovascular control became apparent when they were confirmed
as effective diagnostic tools and strong independent predictors of mortality for diseases
related to cardiovascular function and regulation in the late 80's [33]-[39]. Measurement
of HRV provides a noninvasive method to obtain reliable information on autonomic
modulation ofhesrt rate. A compact, low-power, real-time HRV assesament system could
provide a valuable feature for portable cardiac monitoring and intervention devices. A
microprocessor HRV monitoring system based on QRS detector for ambulatory
74
monitoring was described in [40], and a system on a chip (SoC) for HRV monitoring and
assessment has been described in [32]. The SoC approach applies digital techniques to
measure RR intervals from ECG signals, and stores HRV measures in an internal 16x8
register file histogram memory [32].
10' ECG Trace 2x~------'-------.--------r-------.--------r-------'
.20~------'1t,-0 ----,J20t,--------,J30t,-------.J40:--------,JSO:------''---:'60·
R-R interval vs. Time ~ 1,----,----,---,----,----,----, .!!. !! !!
~ 08 ~
E 06 II: a: 04
···· ·· ····i···········"?7J$S- ··············j··············.) ................... + ............... . ····················i········· ···· 535~; ······ ········ · ·· · i··· · ········· · ····· ·· ; ·= · I·~~ .. ....... . .. . ....... ~ ... .................. ~ .... ................. ! ........... ......... . ! ........ _ . .Y __ ____ . _ ! _____ __ ............ . · . . · . . · . i ;
020~------,1t,-0 ----,J20t,--------,J30t,-------.J40:--------,JSOt,--------,J60·
Difference of R·R interval V5. Time 04.-------,-------,--------.-------.--------.-------.
I ! ! .... "iii' 0::: 02 ~ II CJ ~
. . --_. __ .. _--_._----_ .•................... ! ..................... !-_ .. _----_ .. _-----_ .. ! ..................................... . · . . · . . · . . · . C ~ 0
; .E 'IV \ V ~! V If: cr ·O 2 .. ..... ......... .......................... ~ ..................... ; ............... ...... ; .......... . -_ ... _-- ; ... __ . __ ........... . oct: : : : :
; ; . i .0 40L-------1~0------~20:------~3~0-------4~0------~SOL-----~60
Time (5)
Fig. 4.3 Pre-recoded ECG trace from Physionet database (top), corresponding R-R intervals (middle) and difference ofR-R intervals (bottom).
The HRV SoC design described in [32] has a modest memory capability due to the
limitations of 0.5 ~m CMOS process that was used for the design, and thus does not
allow storage of long-term ECG signals. In addition, even though most R-R intervals
exhibit low variations, such redundancy is not exploited to compress the information.
75
Also, the resolution of the 128x8 register file is dependent on the R-R interval lengths,
due to truncation of the binary representation. These issues are resolved in a new 0.18 jUIl
SoC design described in my design.
To illustrate the typical redundancy of HRV data, Fig. 4.3 shows a I-minute
pre-recorded BCG trace (the top graph) obtained from PTB Diagnostic BCG Database
[41], the corresponding R-R intervals (the middle graph) and the difference between
every two adjacent R-R intervals (the bottom graph). The bottom graph shows that abrupt
variations (called abnormal heart beats in the following) account for lesa than 10% of the
complete dataset, indicating a high degree of redundancy if full R-R intervals are
recorded. In this chapter, we present an efficient HRV SoC, which stores the difference of
every two adjacent intervals instead of full R-R intervals. This difference information is
stored in a high-density/high-speed single-ported SRAM of 8196 words x 64 bits, which
is designed to take full advantage of an advanced commercial CMOS procesa and its
design libraries. As a result, a much longer, and more clinically relevant, set of intervals
can be recorded without increasing the chip size.
The following sections descn'be the previous work done by my colleagues and the
improvements I made, including the algorithm of the efficient RAM, the SoC design, the
chip implementation in a commercial 0.18 I'm CMOS technology, the verification of the
hardware core functionality using pre-recorded BCG signals shown in Fig. 4.3 from the
PTB Diagnostic BCG Database [41] and its physical synthesis.
4.2.2. Efficient Algorithm
Since typical human heart rate ranges from 30 to 150 beats per minute, the beat to
76
beat intervals range from 0.4 s to 2 s. In [32], the R-R intervals are stored in a 128 x 8
register file using a straightforward storing algorithm. thus stored intervals vary from 1.6
ms to 8 ms. Therefore, assuming the worst case of 2 s beat to beat interval, 11 bits are
needed when a Ims resolution is required. In the 128x8 register file described in [32], the
last three digits of the intervals are ignored, which greatly reduces the system accuracy.
1st interval Ixll RF
.. I I I I I I I I I I I 2nd interval
~f'\.
kth-(k-
''/ , 8196x64 SRAM x x x x x x x x ... x x x x x x
x x x x x x x x ... 1 1 1 1 1 Y
x x x x x x x X ... Y Y Y Y Y Y
x x x x x x x x ... Il!!! intel:vjl x x x x x x x x ...
x x x x x x x x ... kO interval
x x x x x x x x ... 1 1 1 1 1 ~ Y Y ... Y Y Y Y Y Y , Y ... . . . . "'- . ..
"" if ldifference!> 120 IDS
Fig. 4.4 The illustration of the efficient SRAM algorithm.
x
Y
Y
x
Y
Y
After taking into account that the differences between every two adjacent R-R •
intervals rarely exceed :1:100 ms as shown in Fig. 4.3, we can increase the resolution to 1
ms by writing only the differences of the· R-R intervals. We separate the R-R intervals
into two categories, normal and abnormal ones (as explained above). The differences are
written one by one, occupying 8 or 16 digits according to the category of the intervals.
77
For a resolution of 1 InS, we use an II-bit binary to represent the heart rate of 30
beats per minute. For the differences of R-R intervals within ±100 InS, we can use an
8-bit binary to store the data. We employ a register to store the first II-bit interval and a
8196 words x 64 bits single-ported synchronous SRAM to store the differences of every
two adjacent R-R intervals.
The algorithm flow is described in the following steps:
1) The first interval is stored by a separate 11- bit register.
2) An 8196x64 SRAM is separated into eight sections. Each section includes 8196
words x 8 bits. The RAM has a write mask capability that allows us to write the
data at the selection of 8 bits. Hence we set the write mask word to select one
section which is used to store the differences of every two adjacent R-R intervals
vertically.
3) If the absolute value of the difference between the current interval and the
previous interval is smaller than 120 InS (1111000 in binary), the 8-bit value
representing the difference in sign and magnitude is written into the selected
section of the current cell of the RAM.
4) If the absolute value of the difference between the current and the previous
interval is larger than or equal to 120 ms, the first five digits of the current cell
are set to 1 as a flag. Then the three most significant digits of the current interval
are written into the last three digits of the current cell and the remaining eight
digits of the current interval are written into the next cell without subtraction.
78
Hence we use two cells to store a value ofan abnormal R-R interval.
5) When it comes to the end of the last address of the SRAM, the following section,
if one is still available, of the SRAM will be selected by the write enable mask to
store the data. At last, when the RAM is full, a corresponding flag is generated.
Fig. 4.4 illustrates the algorithm flow: SRAM bits indicated with 'x' represent normal
intervals, while the two cases with 'y' are examples of abnormal intervals. The distinction
between the two types of interval is guaranteed by the fact that no normal interval will
ever have its five most significant bits set to 1.
Based on the previous observation, a read unit can follow the following procedure to
retrieve the R-R intervals:
1) Read the first interval from the appropriate register.
2) According to the address in sequence, starting from the first cell of the selected
section of the 8196 x 64 SRAM, if the left five digits of the first cell of this
8196x8 section are not all ones, take the sum of the first interval and the first cell
as the second interval. If the 5-digit flag are all 1, indicating an abnormal interval,
the last 3-digit in the current cell and the 8-digit in next cell are combined to
generate the next datum.
3) Repeat step 2 until the end of the memory address space.
4) If the section read is not the last one, address the next 8-bit section of the memory
and reset the address to 0, going to step 2.
79
5) Otherwise, issue an end read flag. This algorithm ensures that the accuracy of
stored data is at least I IDS, even if most data are stored using the same amount
of memory employed in [32].
Assuming that around 99% of the R-R intervals are regular intervals, while the other
I % are the abnonnal ones (for example as indicated in Fig. 4.3), we can estimate the
upper bound on the memory savings. With 99% of intervals represented with 8 bits and
1 % of intervals represented with 16 bits, the occupied memory space equals
99% x 81ll + 1% x 161ll =73.46%.
We estimate 26.54% memory space reduction as compared to writing all intervals
with 11 bits.
4.2.3. SoC Design
ECG Beat RRinterval RR_in~aI 8196 x 64 effICient ~ Peak detector counter SRAM
Fig. 4.5 SoC block diagram.
The SoC block diagram is shown in Fig. 4.5. It consists of the peak detector, R-R
interval counter, and the efficient 8196 words x 64 bits SRAM. The peak detector
converts the digitized ECG input signals into narrow pulses which identify the R-peaks of
the input heart signals. Then the R-R interval counter detects the output pulses from the
peak detector, and obtains the R-R intervals for 8196 x 64 SRAM. The efficient SRAM
discussed in previous section allows recording of up to 24 hours data of R-R intervals
80
continuously.
The function flow of peak: Detector is discussed in the following.
The R wave is detected from the ECG signals and converted into narrow square
pulses in the three following steps:
1) Setup a threshold value to eliminate other peaks by comparing the input data with
the threshold value within the small time interval;
2) Determine the position of the peak by looking for the maximum value in this
interval;
3) Generate a square pulse after obtaining the position of the peak:. The threshold value
depends on the DC level and amplitude of the input ECG signals and is thus
unknown ahead of time. Therefore, the peak: detector must initialize an adjustable
threshold to accommodate variations in the input signals.
The finite state machine block diagram, implemented in VHDL, illustrates the peak
detector algorithm in Fig. 4.6. SOO state resets all signals. SOl starts an internal counter to
count from 0 to 2s and finds the maximum and minimum values. S02 initializes threshold
to the sum of3/4 of maximum value and 114 of minimum values from SOL SI determines
R waves by comparing input data with the threshold. S2 determines the maximum value
again. S31, S33, and S34 check if the input data is smaller than the maximum value
determined in S2 for four more clock cycle to validate the peak. S4 updates the peak: by
changing the output to 1. S41 changes the output back to 0 to generate a square pulse, and
updates the threshold by adding the different value between the current peak and the
81
previous peak to the current threshold. Finally SS is on hold until the input data is lower
than the threshold to transfer back to S 1 state [29].
datain<=th datain old<=datain
datain old<=datain
Reset
datain>=th
Fig. 4.6. Finite state machine of peak detector[29].
Where SOO: Reset all signals;
SOl: Start an internal counter to count from 0 to 2s and find the maximum and
minimum values;
S02: Initialize threshold = ! max+ ~ min where max and min are respectively the
maximum and minimum values determined at SOl;
SI: Determine R waves by comparing input data with the threshold;
82
S2: Find the maximum value;
S3I-S34: Check if input data are smaller than the maximum value determined at S2
for four more clock cycles in order to ensure it is really a peak;
S4: Let the output be 1 and update the peak;
S4I: Change the output back to 1 so as to generate a square pulse and update the
threshold by adding to the current threshold the difference between the current peak and
the previous peak;
S5: Wait lUltil the input data is lower than the threshold and it transfers back to S 1.
The RR-interval colUlter receives the beats coming from the peak detector and
outputs an II-bit data which COlUlts the number of clock periods between every two
adjacent R-peaks for 8196 x 64 SRAM. The ll-bit R-R interval COlUlter can detect the
RR-intervals up to 2047 clock cycles, which is two seconds of range for R-R intervals.
The single-port synchronous RAM is a fully atatic memory, which has four pins,
namely, write enable (WEN), chip enable (CEN), data in (D) and data out (Q).
The finite state machine block diagrams implemented in VHDL, illustrate the
efficient SRAM writing and reading algorithms in Fig. 4.7 (a) and (b).
In Fig. 4.7 (a) which illustrates the state transfer of writing status, the state sOw
initializes all signals. The next two states, s 1 w and s 1 w2, wait for the coming two
consecutive R-R intervals. The difference of the two R-R intervals is calculated at s2w,
the state s3w prepares control signals for writing the differences to RAM. The next two
83
states. s4wl and s4w2. set the signal WEN and the address for writing. When the R-R
interval is a normal one. the state s4w3 goes back to slw; if the interval is an abnormal
one. the state will transfer to s4w4. together with s4wS. s4w6. which are three writing
states to store the complete abnormal R-R intervals associated with flags. Finally s4w6
will transfer back to s 1 w state.
In Fig. 4.7 (b). illustrating the reading protocol, sOr is also the initializing state. From
sIr. it starts retrieving the R-R intervals from the RAM. S2r. s2r2 and s2r3 will update the
address when it finishes reading one cell, then the state moves on to 83rl which is used to
judge if the value of the current cell is normal or abnormal. If it is a normal value. s3rl
will jump to s4r to calculate the output data, then goes to next state sSr to output the
retrieved R-R interval; if it is abnormal value. s3rl state will keep on processing the data
through s3r2. s3r3 and s3r4. and then moves on to s4r and sSr. Finally it goes back to sir
to complete one cycle.
(a)
84
eDJ"'O'
0uIput the R-R Cakulate the intervalo ouIpUI daIa
Process the aImmmaI daIa
(b)
Fig. 4.7 Finite state machine of RAM (a) writing (b) reading protocol.
4.2.4. Verification and Layout of the SoC
The hardware core whose design is detailed in the previous sections has been
described in synthesizable VHDL targeted for an implementation using a commercial
0.18 vm technology and its associated memory libraries.
After a pre-synthesis verification of the functionality, we proceeded with a synthesis
using Synopsys' Design Compiler (TM). The cell and memory occupation after synthesis
gives an overall area of2.5x2.5 mm2 for the entire system.
The synthesis results show that the standard cell logic used in the design is a small
fraction of the overall area, which is mainly occupied by the memory. This indicates that
there is plenty of space for incorporating more functionality (such as histogram
classification, triangular index, standard deviation of R-R intervals, and possibly spectral
measures) in a single chip. As expected, the timing constraints are not significant, and this
implies a light clock tree with low power dissipation. The dynamic power dissipation
reported after synthesis (without the clock tree, but see the previous observation) is 5.5
nW, which is much smaller than the cell leakage power of ISS )J.W.
Suppose we have an Energizer 393 button cell battery, which has volts of l.Sv, and
the mAh of 70, then the chip applied with such a battery can run l.Sv x 70
mAhllSSuW=672 hours.
Two abnOlrmal R-R intervals retrieved Fig. 4.8 VHDL post-synthesis simulation.
Fig. 4.8 shows the output of VHDL post-synthesis simulation of digital HRV chip
which illustrates that R-R intervals are retrieved successfully. A pre-recorder ECG trace
shown in Fig.4.3 from Physionet database [41] was used for this test. The two output
intervals 535 ms, 738 ms which are highlighted in both Fig. 4.3 and Fig. 4.8 are
abnormal R-R intervals. The output retrieved R-R intervals are exactly the same with the
input intervals, which indicates that the efficient algorithm for SRAM enables us to
obtain all R-R intervals regardless of their classification. With the result from the
synthesis, physical design of the chip has been completed using Cadence SoC Encounter
(TM). The final result, that includes power and clock routing, is shown in Fig. 4.9. It is
apparent that the standard cell area is underutilized, even though the ratio between
standard cell and memory block has been kept to a minimum, further emphasizing the
86
availability of silicon area to incorporate more complex functions. The overall laid out
core has dimensions of2.5 mm by 2.5 mm.
Fig.4.9 Layout of the chip.
4.3. Conclusions
This chapter has demonstrated a digital heart rate variability monitoring system on
chip with an efficient RAM in a commercial O.181ill1 process using VHDL, with a power
consumption of less than ISS 11 W. We have presented the algorithm of the efficient RAM,
the design of the system on chip, verification and the layout. The RAM employed an
efficient algorithm to store the differences between every two adjacent R-R intervals, thus
saving memory space. The SoC has the capability to store 24 hours of continuous ECG
87
data with a fixed resolution of lms. The chip has a core area of 2.Sx2.S mm2. Such a
system could be used with home based monitoring systems, such as Holter BCG monitors.
This chip will be fabricated in near future. While this chip was tested with BCG data.
Doppler heart rate data can be stored in this memory with same gains.
88
Chapter 5
5. Conclusions
This thesis focuses on the hardware design and integrated circuit implementation for
heart rate interval extraction in Doppler radar and BCG systems. The hardware includes
an RF mixer for frequency translation in a Doppler radar receiver, a pre-amplifier for
physiological base-band signal conditioning prior to analog-to-digital conversion, as well
as a digital ASIC for storing long-term heart rate intervals.
The 2.4 GHz (ISM band) 0.25 J.Un CMOS resistive ring mixer operating in the
near-threshold region and its IC implementation were discussed in Chapter 2. A novel
implementation with a small gate bias voltage just below the threshold voltage enables
very low LO power operation. The lowest conversion loss of 7 dB was achieved at 3.6
GHz, with LO power of 10 dBm, and with low RF insertion loss in the frequency range
of 2-8 GHz. If the LO power is reduced to -10 dBm, the conversion loss of this mixer is
increased by 14 dB. For comparison, if the mixer is not biased, conversion loss would
increase by 85 dB for the change in LO power from 10 dBm to -10 dBm.
A pre-amplifier with the tunable bandwidth of 0.1-50Hz and tunable gain of
500-10,000 was implemented on a proto-board as well as PCB. It can be connected to IF
port of mixer described in Chapter 2 to amplifY and filter the signals and remove the DC
as required. The amplifier was tested using BCG, finger pressure pulse, and Doppler radar
signals, and it was demonstrated that it has a lower noise floor than a commercial
instrumentation amplifier. This preamplifier can be integrated on a single chip with the
89
exception of two big capacitors.
Finally, a digital ASIC design with an efficient memory that can store up to 24 hours
of continuous heart rate interval data by recording the difference between every two
adjacent intervals in a single-port synchronous, high-perfonnance SRAM, with a fixed
resolution of Ims, was discussed. The system has been laid out in a commercial 0.18 JLIIl
CMOS process in a 2.5 mm x 2.5 mm hardware core with a low power consumption of
1551lW. This chip will be fabricated in the near future.
The suggestions for future include hardware perfonnance improvements, further
integrstion, and implementation of additional functions. First, the linearity of the mixer,
PldB, IIP2 and IIP3, could be improved by using different matching network, while
preserving broadband matching. Second, the preamplifier can be integrsted on chip,
potentially changing the architecture to achieve tunable not only high pass but also low
pass cut off frequency. Third, the digital ASIC design can incorporate more functionality
(such as histogram classification, triangular index, standard deviation of R-R intervals,
and possibly spectral measures) in a single chip. The hardware described in this thesis
may enable future miniaturization ofHRV monitoring devices.
Acknowledgements
The author would like to thank Prof. Olga Boric-Lubecke. Prof. Victor M. Lubecke.
and Prof. Luca Macchiarulo for very useful advices and discussions, especially Prof. Olga
Boric-Lubecke for her great supports and wise supervisions. The author would also like
to thank Ivy Lo and Byung-Kwon Park for their great help on chip testing. thank Mingqi
Chen and Shuhei Yamada on simulation debugging. and thank Dung Phuong Nguyen and
Yun-pyo Hong for their warm encouragements during thesis writing.
91
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96
Appendix
I.VHDL Code of Efficient SRAM
-Efficient 128*8 RAM for HRV version 5.1 -replace the internal ram with Artisan ram -add s3wb, sSw and s2rb to write and read correctly: - Write and read of the Artisan ram has 1 clock cycle delay. Therefore, for write, you - have to make both the clock and the addr _ w ready; similarly, for read, you have to - ~teaddrJoofu~~Mgram_~ -Able to write and read all the Artisan ram
library IEEE; use lEEE.stcUogic _1164.all; use IEEE.atd_logic_unsigned.aIl; use lEEE.atd_logic_arith.aIl; -use WORK.RAlSHD ..Jlkgs.aIl;
entityeffiamSplia port (clk: in atd_logic;
reset: in atd_logic; en_in: in atd_logic; datain: in atd_logic_vector(I0 downto 0); ram_full:out std_logic; en_r: in atd_logic; read_end: out atd_logic; dataout: out atd_logic_vector(lO downto 0»;
end effiamSp 1;
archi~ rtl of effiamSpl is component RAlSHD port(
clk : in atd _logic; CEN: in atd_logic; WEN: in atd_logic_vector(7 downto 0); A: in atd_logic_vector( 12 downto 0); D: in atd_logic_vector( 63 downto 0); OEN: in atd_logic; Q: out atd_logic_vector( 63 downto 0)
); end component;
type States_w ia (sOw, slw, s1w2, s2w, s3w, s4wl, s4w2, s4w3, s4w4, s4wS, s4w6); type StatesJ is (sOr, sir, s2rl, s2r2, s2r3, s3rl, s3r2, s3r3, s3r4, s4r, sSr);
signal currencstate_w,next_state_w: States_w; signal current_stateJ.next_state_r: States_r; signal addr_w,addr_w_old,addr_r,addr_r_old: atd_logic_vector(I2 downto 0);
97
signal datain1,datainl,datain _1st, v _ rri _abn. v _rri _ abs,dataouUemp,dataout_ old: suUogic _ vector(l 0 downto 0); signal ranuemp2, tam_ten1p,v_rri_reg:suUogic_vector(7 downto 0); signal caI_v_rri,update_v_rri,update_addr_w,update_addr_w_old,v_rri_sign,regular,reaICaIUlag,enJ_ old,update_addr_r,update_addrJ_old,update_ram_ten1p,dataout_ten1p_caI,update_dataout_old: std_logic; signal dataout_flag: std_logic_vector(l downto 0);
signal counter_datain: std_logic_vector(63 downto 0); signal update_dataout,update_ram_ten1p2,en_w: std_logic; signal counter_col_w,counter_coIJ: std_logic_vector(2 downto 0);
signal CEN: std_logic; signal WEN: std_logic_vector(7 downto 0); signal A; std_logic_vector(12 downto 0); signal D: std_logic_vector(63 downtoO); signal OEN: std_logic; signal Q: std_logic_vector(63 downto 0);
begin
CEN<='O'; OEN<='O'; addr..Jlroc: process(addr_w, addr_r, WEN) begin
~:Dll111111n)then
A<=addU; else
A<=addr_W; end if;
end process;
-mem: RA1SHD generic map(timingcheckson=>FALSE) port map( mem: RAlSHDportmap(
clk , CEN • WEN, A, D, OEN, Q
); ------------write:----------------------------
state_des_w: process(current_state_w,en_in,counter_datain,datain2,regular) begin
case currenC state _ w is when sOw => -initialize
next_state_ w<=s1 W; cal_v _rri<='O'; update_v_rri<='O';
98
update_addr_w<='O'; update_addr_ w _old<='O'; -WEN<="11111111"; en w<='O" - .
when slw => -wait fordatain_lst ordatain -if (en_in='l ' and datain_lst_on='l ') then if (en_in=' l' and counter_datain>=x"OOOOOOOOOOOOOOOl") then
next_state_W<=slw2; else
next_state_ w<=sl w; end if; caC v _rri<='O';
update _ v _ rri<='O'; update_addr_w<='O'; update_addr_ w _old<='O'; -WEN<="11111111"; en_w<='O';
when slw2=> if (datain2="OOOOOOOOOOO" or counter_ datain<x"OOOOOOOOOOOOOOO2n
) then next_state_W<=sl~
else next_state_ w<=s2~
end if; cal_v_rri<='O'; update _ v _ rri<='O'; update_addr_ w<='O'; update_addr_ w _old<='O'; -WEN<=" 1 1111111"; -etl_W<='O';
when s2w => -caIculate the difference of the RR interval next_state_w<=s3~ cal_v_rri<='l'; update _ v _ rri<='O'; update_addr_w<='O'; update_addr_w_old<='O'; -WEN<="l1l1l1l1"; -etl_W<='O';
when s3w => -prepare the difference and addr_w for writing next_state_w<=s4wl; cal_ v _ rri<='O'; update_v_rri<='l'; update_addr_w<='O'; update_addr_w_old<='l'; -WEN<="llllllll "; -en_w<ctOI
;
when s4wl => -prepare WEN and addr_w for writing to ensure the data to be written in the right address
next_state_ w<=s4w2; cal_v _rri<='O'; update_v_rri<='O'; update_addr_ W<='1';
update_addr_w_old<='O'; -WEN<="l1l1l1 10"; en_W<='I';
when s4w2 => -prepare WEN and addr_w for writing to ensure the data to be written in the right address
next_state_w<=s4w3; cal_v _ rri<='O'; update_v_rri<='O'; update_addr_w<='O'; update_addr_w_old<='O'; -WEN<=" I 1111110"; en_W<='I';
when s4w3 => -write
x"OOOOOOOOOOOO";
x"OOOOOOOOOO";
x"OOOOOOOO";
x"OOOOOO";
if (regular='1 ') then
else
case counter _ col_ w is when "000· =>
D<=v _rri_reg & x"OOOOOOOOOOOOOO"; when "001" =>
D<=x"00" & v_rri_reg & x"OOOOOOOOOOOO"; when "010" =>
D<=x"0000" & v_rri_reg & x"OOOOOOOOOO"; when "011" =>
D<=x"000000" & v_rri_reg & x"OOOOOOOO"; when "100" =>
D<=x"OOOOOOOO" & v _rri_reg & x"OOOOOO"; when "101" =>
D<=x"OOOOOOOOOO" & v_rri_reg & x"OOOO"; when "110" =>
D<=x"OOOOOOOOOOOO" & v_rri_reg & X"OO"; when "111" =>
D<=x"OOOOOOOOOOOOOO" & v_rri_reg; when others =>
end case; nexcstate_ w<=s1 W;
case counter_col_ w is when "000" =>
D<="11111" & v_rri_abn(10 downto 8) & x"OOOOOOOOOOOOOO"; when "001" =>
D<=x"00" & "11111" & v_rri_abn(10 downto 8) &
when "010" => D<=x"0000" & "11111" & v_rri_abn(10 downto 8) &
when "011" => D<=x"OOOOOO" & "11111" & v_rri_abn(1O downto 8) &
when "100" => D<=x"00000000" & "11111" & v_rri_abn(lO downto 8) &
when "101" =>
100
x"OOOO"j
x"OO"j
0<=x"0000000000" & "1IllI" & vJri_abn(IO downto 8) &
when "llO" => 0<=x"000000000000" & "lllll" & v_rri_abn(lO downto 8) &
when "lll" => 0<=x"00000000000000" & "I III I " & v_rri_abn(IO downto 8)j
when others => endcasej next_state_w<=s4w4j
end ifj cae v _rri<='O'j update _ v _ rri<='O'j update_addr_ w<='O'j update_addr_ w _old<='O'j -WEN<=" III III 10"j en_w<='I'j
when s4w4 => -prepare for writing the next 8-bit segment of the abnonnal data next_state_w<=s4w5j cal_v _rri<='O'j update _ v _ rri<='O'j update_addr_W<='l'j update_addr_w_old<='O'j -WEN<="llI llllO"j en_W<='I';
when s4w5 => -prepare for writing the next 8-bit segment of the abnonnal data next_state_w<=s4w6; cal_v _ rri<='O'; update_v_rri<='O'; update_addr_W<='O'; update_addr_w_old<='O'; -WEN<="lllllllO"j en_W<='I';
when s4w6 => -write next_state_w<=slw; case counter_col_w is
when "000" => 0<=V_rri_abn(7 downto 0) & x"OOooooooOOOOOO";
when "001" => 0<=x"00" & v_rri_abn(7 downto 0) & x"OOOOoooOoooO";
when "010" => 0<=x"0000" & v_rri_abn(7 downto 0) & x"OOOooooooO";
when "011" => 0<=x"000000" & v_rri_abn(7 downto 0) & x"OooooooO";
when "100" => 0<=x"00000000" & v _rri_abn(7 downto 0) & x"oooOOO";
when "101" => 0<=x"0000000000" & v_rri_abn(7 downto 0) & x·OOOO";
when" llO" => 0<=x"000000000000" & v_rri_abn(7 downto 0) & x"OO";
when "lll" =>
101
D<=x"OOOOOOOOOOOOOO" & v_rrCabn(7 downto 0);
end case; end process;
when others => end case; caCv_rri<='O'; update _ v _ rri<='O'; update_addr_ w<='O'; update_addr_w_old<='O'; -WEN<="llll II 10"; en_W<='I';
state_trmls_w: process(clk,reset) begin
if (reset='1 ') then cmrent_state_ w<=sOw;
else if (clk='J' and clk'event) then
cmrent_state_ w<=next_state_ w; end if;
end if; end process;
datain_register: process(clk,reset) begin
if (reset='1 ') then datain I <=( others=>'O'); datain2<=( others=>'O');
elsif (clk'event and clk='l ') then if (en jn='1 ') then
datainl <=datain; datain2<=datain I;
end if; end if;
end process;
-datain_lst_switch: process(reset, datain_lst) -begin
if (reset='1 ') then datain 1st on<='O" - - ,
~Isif (clk'event and clk='l,) then else
if (datain _I st>"OOOOOOOOOOO") then dataiit 1st on<='I" - - ,
else datain_lst_on<='O';
end if; end if;
-end process;
102
begin if (reset='l ') then
datain _lst<=( othenF'>'O,); elsif (clk'event and c!k='l ') then
-if (enjn=' l' and datain_lst_on='O') then if (counter _datain<x"OOOOOOOOOOOOOOO2n) then
datain_lst<=datainl; end if;
end if; end process;
v _rrCcalculstion: process(reset,cal_ v Jri) begin
if (reset='l ') then v_rrCabs<=(others=>'O'); v_rrCsign<='O';
elsif (cal_ v _ rri='l ') then if(datainl>=datain2) then
v_rri_abs<=datainI-datain2; v_rri_sign<='O';-positive
elsif (datain 1 <datain2) then v _ rri _ abs<=datain2-datain I; v _ rri_sign<='l';-negative
end if; end if;
end process;
regular_switch: process(reset, v _ rri _ abs) begin
if (reset='l ') then regular<='O';
else if(v_rri_abs<"OOOOI11 looon)then
regular<='l'; else
regular<='O'; end if;
end if; end process;
v_rri_ready4w: process(clk,reset) begin
if (reset='l ') then v_rri_reg<=(othenF'>'O'); v_rri_abn<=(othenF'>'O');
elsif(clk'event and clk='l ') then if (update_ v_rri='l' and regular='l ') then
v_rri_reg(6 downto 0)<=v_rri_abs(6 downto 0); v _rri_reg(7)<=V _ rri _ sign;
elsif(update_v_rri='l' and regular='O') then v_rri_abn<=datainl;
103
end if; end if;
end process;
addr _ w _update: process(reset,clk) begin
if (reset='1 ') then addr _ W<=( others=>'O');
elsif\:clk'event and clk='l ')then if(update_addr_w='l,) then addr_ w<=addr_ w+ 1; end if;
end if; end process;
addr_w_old_update: process(reset,clk) begin
if (reset='1 ') then addr _ w _ old<=( others=>'O');
elsif\: clk'event and c]k='l ')then if(update_addr_w_old='l') then
addr_ w _old<=addr_ W;
end if; end if;
end process;
WEN_update: process(reset,en_w) begin
if (reset='1 ') then WEN<=" 11111111 ";
elsif(en_w='l') then
else
case counter_col_w is when "000" =>
WEN<="01111111 "; when ·001" =>
WEN<=" 10111111 "; when "010" =>
WEN<="11011111"; when "OIl" =>
WEN<=" 11101111 "; when "100" =>
WEN<="11110111 "; when "101" =>
WEN<="1ll1l011 "; when "110" =>
WEN<="l1l1 1101 "; when "Ill" =>
WEN<="11111110"; whenothers=>
end case;
104
WEN<="llllllll "; end if;
end process;
co1unm_counter_w: process(n:set,addr_w) begin
if (reset='1 ') then counter_coC w<="000";
elsif (clk'event and cJk='l,) then if (addr _ w _old=" 1111111111111" and addr _ w="0000000000000") then
counter_coCW<=counter_col_w+1; end if:
end if; end process;
ramjulUlag: process(n:set,addr_w_old,addr_w) begin
if (reset='1 ') then ramjull<='O';
--elsif «addr_w_old="1111111111110" or addr_w_old="1111111111111") and (addr_ w="0000000000000" or addr_ w="0000000000001"» then
elsif(addr_w="11111111111" and WEN="11111110") then ramjull<='l ';
end if; end process;
count_datain: process(n:set,clk) begin
if (reset='1 ') then counter _ datain<=( others=>'O');
elsif(clk'event and cJk='l ')then if(en_in='l') then
counter _ datain<=counter _ datain+ I; end if;
end if; end process;
------~~I----------------, state_des_r: process(current_state_r,en_r,read_aIUlag) begin
case current_state J is when sOr => -initialize
next_state J<=S 1r; update_ addr _r _ old<='O'; update_addrJ<='O'; update_ram_temp<='O'; update_ram_temp2<='0'; update _ dataout_ old<='O'; dataout_temp _ caI<='O'; -dataout<=( others=>'O,); reaICend<='O';
lOS
update _ dataout<='O'; when slr=> -read the ram
if(en_r='O~ then next_state_r<=slr; update_addr_r<='O';
elsif(en_r='l ~ then if (read_alUlag='O~ then
next_state _r<=s2r 1; if(en_r_old='O~ then
update_addr_r<='l '; else
update_addr_r<='O'; end if;
elsif (read _alUlag='1 ~ then nexCstate_r<=slr; read_end<='l '; update _addr _r<='0';
end if; end if; update_addr_r_old<='O'; update_ram_temp<='O'; update_ram_temp2<='0'; update_dstaout_old<='O'; -dataout_temp_ca1<='O'; update _ dataout<='O'; whens2rl =>
next_state _r<=s2r2; update_addr_r_oJd<='l '; update_addr_r<='O'; update_ram_temp<='O'; update_ram_temp2<='0'; update_dataout_old<='l '; -dataout_temp_ca1<='O';
when s2r2 => next_state_r<=s2r3; update_addr_r_old<='O'; update_addr_r<='O'; update ram temp<='l '. - - , update_ratn_temp2<='O'; update _ dataout_ old<='O'; -dataout_temp_cal<='O';
whens2r3=> next_stateJ<=s3rl; update_addr_r_old<='O'; update_addr_r<='O'; update_ratn_temp<='O'; update_ratn_temp2<='0'; update_dataout_old<='O'; -dataout_temp_ca1<='O';
whens3rl => if (dataout_fIag="l1") then
106
next_stale_r<=s3r2; update_addr_r<='l ';
else next_stale_r<=s4r; update_addr_r<='O';
end if; -update_addr_r<='O'; update_ratn_temp<='O'; update_ratn_temp2<='O'; update_addrJ_old<='O'; update_dataouCold<='O'; -dataout_temp _ caI<='O';
when s3r2 => nexCstaIe_r<=s3r3; update_addr_r_old<='O'; update_addr_r<='O'; update_ratn_temp<='O'; update_ram_temp2<='O'; update_dataout_old<='O'; -dataout_temp _ caI<='O';
whens3r3 => next_stale_r<=s3r4; update_addr_r_old<='O'; update_addr_r<='O'; update_ratn_temp<='O'; update_ratn_temp2<='1 '; update_dataout_old<='O'; -dataout_temp_caI<='O';
whens3r4=> nexcstate_r<=s4r; update_addr_r_old<='O'; update_addr_r<='O'; update_ratn_temp<='O'; update_ratn_temp2<='O'; update3ataout_old<='O'; -dataouCtemp_caI<='O';
whens4r=> nexC state _r<=s5r; update_addrJ_old<='O'; update_addr_r<='l'; update_ratn_temp<='O'; update_ratn_temp2<='O': update_dataout_old<='O': dataout_temp_caI<='l':
whensSr=> next_ staIe_r<=s Ir; update_addr_r_old<='O': update_addr_r<='O': update_ratn_temp<='O': update_ratn_temp2<='O': update_dataout_old<='O':
107
end case; end process;
dataouCtemp_cal<='O'; update_dataout<='l'; -dataout<"'IIataouCtemp;
state_trans _r: process( clk,reset) begin
if (reset='l ') then currenCstate_t<=sOr;
else if (clk='l , and clk'event) then
cmrent_state_r<=nexCstate_r; enJ_old<=en_r;
end if; end if;
end process;
dataoutjudge: process(reset,ram_temp) -a flag begin
if (reset='l ') then dataout_flag<="OO";
-elsif (clk='l' and clk'event) then else
if (ram _ temp(7 downto 3)=" 11111 ") then dataout_flag<="11 ";
elsif (ram_temp(7)='O') then dataout_flag<="Ol ";
elsif (ram _temp(7)='1 ') then dataouCflag<=" 10";
end if; end if;
end process;
read_end_flag: process(reset,enJ,addu_old) begin
if (reset='l , or (en_r='l' and addr_r_old<addr_w_old» then read_all_flag<='O';
elsif(enJ='I' and addrJ_old>=addr_w_old and oounter_ooIJ>=counter_col_w) then read_all_flag<='l';
end if; end process;
dataout_old_update: process(clk,reset) begin
if (reset=' 1 ') then dataouC old<=( others=>'O');
elsif (clk='l' and clk'event) then if(update_dataout_old='l') then
dataout_old<=dataout_temp; end if;
108
end if; end process;
dataout_temp_calcuIate: process(clk,reset) begin
if (reset='1 ') then dataouUemp<=(others=>'O');
elsif(clk='l' and clk'event) then if (en_r=' I , and en_r_old='O') then
dataout_temp<=datain _1st; elsif(dataout_temp_cal='I') then
if (dataout_flag=n II n) then dataout_temp(IO downto 8)<=ram_temp(2 downto 0); dataout_temp(7 downto 0)<=ram_temp2;
elsif(dataout_flag=nOln) then dataout_temp<=dataout_old+("oooon & ram_temp(6 downto 0»;
elsif(dataout_f1ag=nlon) then dataout_temp<=dataout_old-(noooon & ram_temp(6 downto 0»;
end if;
end if; end process;
end if;
addu_update: process(clk,reset) begin
if (reset='1 ') then addU<=(others=>'O');
elsif(clk='l' and clk'event) then if(update_addr_r='I') then
addr_r<=addr_r+ I; end if;
end if; end process;
addr_r_old_update: process(clk,reset) begin
if (reset='1 ') then addr _r _ old<=( others=>'O');
elsif(c1k='I' and clk'event) then if (update _addr _r _old='1 ') then
addr_r_old<=addr_r; end if;
end if; end process;
ram_temp_update: process(clk,reset) begin
if (reset='1 ') then ram_temp<=(others=>'O');
elsif (clk='l ' and clk'event) then if(update_ram_temp='I') then
109
case counter_colJ is when "000· =>
ram_temp<=Q(63 downto 56); when "001" =>
ram_temp<=Q(55 downto 48); when "010" =>
ram_temp<=Q(47 downto 40); when "011" =>
ram_temp<=Q(39 downto 32); when "100" =>
ram_temp<=Q(31 downto24); when "101" =>
ram_temp<=Q(23 downto 16); when "110" =>
ram_temp<=Q(15 downto 8); when "111" =>
ram_temp<=Q(7 downto 0); when others =>
end case; end if;
end if; end process;
ram_teJnp2_update: process( cIk,reset) begin
if (reset='l ') then ram_teJnp2<=(others=>'0');
elsif(cIk='I' and clk'event) then if(update_ram_teJnp2='1') then
case counter_col_r is when "000" =>
ram_teJnp2<=Q(63 downto 56); when "001" =>
ram_teJnp2<=Q(SS downto 48); when "010" =>
ram_teJnp2<=Q(47 downto 40); when "011" =>
ram_teJnp2<=Q(39 downto 32); when "100" =>
ram_teJnp2<=Q(31 downto 24); when "101" =>
ram_teJnp2<=Q(23 downto 16); when "110" =>
ram_teJnp2<=Q(15 downto 8); when "111" =>
ram_teJnp2<=Q(7 downto 0); when others =>
end case; end if;
end if; end process;
110
column_counter J: process(reset,addr _r) begin
if (reset='l ') then counter col r<="OOO"' - - .
elsif (addr J _ old="lllllllllllll" and addr _r="OOOOOOOOOOOOO") then counter_col_r<=counter_coIJ"'I;
end if; end process;
dataout _update: process( clk,reset) begin
if (reset=' I ') then dataout<=( others=>'O,);
elsif(cIk='I' and clk'event) then if (update _ dataout='l ') then
dataout<=dataout _temp; end if;
end if; end process;
end rtI;
111
