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Analysis and Design of Sub threshold CMOS Voltage Reference using Low Voltage-

Comparator and a Charge pump circuit

KomandurRaghunandanM.tech .VLSI DesignElectronics and Communication Department

SRM university, ChennaiTamil Nadu

e-mail:[email protected]

Prof. J. SelvakumarAsst.prof (Sr.grade)

Electronics and Communication DepartmentSRM university, Chennai

Tamil Nadu

Abstract — This paper presents a subthreshold CMOS

voltage reference circuit implemented by replacing the

analog amplifier in the conventional CMOS voltagereference with alow voltage comparator, a charge pump

circuit and digital control unit .The main objective of the

proposed circuit is to operate at low supply voltage and

which should be less than the conventional design. The

circuit designed by using 90nm CMOS technology and

simulations are verified by using Cadence Virtuoso. The

simulated result shows that the proposed voltage

reference circuit used to produce a reference voltage of

274mV when operating at the supply voltage of 374.3

mV.By comparing with the conventional design the

proposed voltage reference circuit requires 250mV

minimum supplyvoltage.

Keywords — Subthreshold;voltage reference;charge pump;

control unit; low voltage comparator

I. I NTRODUCTION

Voltage Reference is an electronic device that ideally produces a fixed voltage irrespective of the loading on the

device, power supply variations, temperature changes, and the

passage of time. A bandgap reference circuit is one of the core

functional blocks in both analog and digital systems.

In 1971, Wildar demonstrated that the sum of base-emitter

voltage and properly scaled PTAT voltage could lead to astable reference circuit whose value was close to 1.2 V

[1].Then the resulting circuit is referred to as Bandgap Voltage

Reference (BVR).Since then several BVRs have been reportedfor use in a wide range of applications [2]-[4].

Low voltage and Low power operation are two important

design criteria for voltage reference. As process technologies

scale down and the demand for battery-operated portable

equipment increases, the supply voltage has to be scale down.

This low supply voltage requires new circuit topologies for

voltage reference circuits. In CMOS technology, a parasitic

vertical bipolar junction transistor is often used in voltagereference circuits.Filanovsky and Allam studied MOSFET

temperature behavior pointing out that below a certain

technology dependent bias point ,the gate-source voltage of a

MOSFET,biased with a fixed drain current ,decreases with

temperature in a quasilinear fashion[5].Starting from thisobservation, a gate to source voltage can be used instead of a

base-emitter voltage to design a voltage reference independentof temperature. Many circuits, including voltage regulators,

analog-digital and digital-analog converters, require a voltage

reference that is as precise as possible. Their precision

depends on it. That means that the voltage reference would

ideally be PVT independent.

• P: manufacturing process variations • V: Supply voltage • T: Temperature

To keep pace with the supply voltage requirement of state-of-

the-art CMOS process, several low voltage reference voltagecircuits have been proposed.

II. LITERATURE REVIEW

Supply voltage is scaling down because of reducing oxide

thickness and increasing demand for low power portable

battery requirement. Normally 1.8 V power supplies are

commonly used; soon, circuits operating with 1.2 V or less

will be introduced. The threshold voltage of MOS transistors

however is not scaling down as much as the supply voltage.

Therefore, this relatively high threshold calls for new

techniques in the design of basic analog blocks. One keycomponent for analog systems is the bandgap voltage

generator.

The Bandgap Voltage Reference (BVR) circuits are

commonly used owing to their high accuracy. These have

been implemented in standard CMOS technology exploiting

parasitic vertical Bipolar Junction Transistors (BJT).SeveralBandgap voltage reference circuits are implemented in

submicron BICMOS technology [6].This circuit operates with

a supply voltage of 1 V. Later several low voltage low power

voltage reference (VR) based on new circuit topology and on


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subthreshold MOSFETS.It exploits the fact that the gate

source voltage of MOSFET, after biasing with constant drain

current decreases linearly with temperature [7].Severaltechniques for sub 1-V operation has been proposed to reduce

the supply voltage [8].In this technique the supply voltage of

the BGR circuit was reduced to 0.75 V.The minimum supply

voltage cannot be lower than the forward biased p-n junction

voltage of 0.7 V.

The other techniques are implemented by substituting the p-n junction circuit with the diode-connected NMOS transistors

biased in the subthreshold region [9].The CMOS voltage

reference circuits can operate at lower supply voltages than the

BGR circuit because the gate-source voltage of the diode

connected NMOS transistors in the subthreshold region is

much lower than the turn on voltage of p-n junction diode.

Therefore the turn on voltage of the CMOS voltage reference

circuit could be reduced to 0.45 V. This brief proposed a

subthreshold CMOS voltage reference circuit, which is based

on conventional CMOS voltage reference circuit in Fig. 1.The

circuit reduces the supply voltage by replacing the analog

amplifier to a low voltage comparator, a charge pump circuit,and a digital control unit operating at the supply voltage under

the threshold voltage.

III. CONVENTIONAL CIRCUIT

Fig. 1. Conventional CMOS voltage reference circuit

This conventional CMOS voltage reference circuit, where thediode connected NMOS transistors M1 and M2 in the

subthreshold region replace the BJTs in the traditional

bandgap reference circuits.

MOSFET in subthreshold region:

In this section we will explore the behavior of the MOS

transistor in the subthreshold regime where the channel is

weakly inverted.

In sub threshold region:

When


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So the output reference voltage is defined as follows

= (n ln() +

) (4)

ThermalvoltageU T andgate –

sourcevoltageV GS havepositiveandnegativeTCs,respectively.Th

evoltagereferencecircuitmakesatemperature-

insensitivereferencevoltage byselectingthe R3 /R1

value.OutputreferencevoltageV REFiscontrolledbychoosingthe R4value.Theoutputreferencevoltagec

hangeduetotheprocessvariationoftheNMOStransistorscanbewe

llcontrolled by trimmingthe valuesofresistors R3and R4.In the

simulation the differential amplifier uses the PMOS input

transistors instead of NMOS input transistors to sense low

input voltages.

Fig 2 : PMOS and NMOS differential Amplifier stages

Fig.3 and Fig.4 shows the schmetic and simulation of the

conventional voltage reference implemented in 90nm CMOS

technology using cadence virtuoso.The simulation result

shows the variation of supply voltage with respect to the

reference voltage.The simulated waveform shows that theconventional circuit used to produce 274 mV reference

voltage at 430 mV supply voltage and the design requires

350mV minimum supply voltage.

Fig.3 Conventional Voltage Reference circuit

Fig.4 Variation of supply voltage vs Reference voltage in

conventional design

IV. PROPOSED METHOD

Fig.5 Proposed voltage reference circuit

This circuit is implemented by using the conventional design

as shown in Fig. 5 . It has been implemented by replacing the

analog amlifier in the conventional design by a low voltage

comparator and a charge pump circuit and control unit circuit.

As the control circuit is supplied by the clock source it is

going to generate the control signals SAE1, SAE2, CS, and PC

respectively. And these signals are used for the analysis of

charge pump and low voltage comparator circuits. When the

Low voltage comparator is supplied by _ and_ and thecontrol signals SAE1 and SAE2 are used to enable the sense

amplifier and auxiliary amplifier, then the comparatoramplifies the low voltage input signals and produce the

comparator output. This output will be given to charge pump


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circuit and it will increase or decrease the Gate voltage

according to comparator output value. This gate voltage isapplied to , , 5 to control currents , , . Thereference voltage will be generated at the output node with

less supply voltage due to subthreshold operation of

transistors.

Control unit:

This control circuit going to generate four control signalsnamed as follows:

1) SAE1 (Sense amplifier enable1)

2) SAE2 (Sense amplifier enable2)

3) CS (charge sharing)

4) PC (Pre charge)

FIG.6 Digital control unit

D Flipflop is implemented by using transmission gates andthe Fig.7 and Fig.8 shows the schmeatic of D Flipflop and the

trasient respponse of the D Flipflop.

Fig.7 D Flipflop schematic

Here D flipflop is supplied by 600mV supply voltage and

delay in the control unit is implemented by using series

connection of two invereters.The Control circuit schematic

and the simulation result is shown in the Fig. 9and Fig.10. and

it is going generate control signals SAE1 (600mV),SAE2

(32mV) ,PC (1 V),CS (1 V) by applying 1 V clock pulse.

Fig.8 D Flipflop simulation result

Fig. 9 .Control circuit schematic


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Fig.10 Transient response of control circuit

Low voltage comparator:

Fig.10 Low voltage comparator schematic

The proposed Low voltage comparator as shown in Fig 10

detects the voltage difference between _ and _. And isis going to add an auxiliary amplifier to the conventional sense

amplifier type comparator. The comparator without auxiliary

amplifier operates slowly in some conditions when difference

between two input voltages is very small if we apply small

input voltages. The auxiliary amplifier will improve the

sensing speed and expanse the range of input voltages of

comparator because its amplification is independent of Vin.

The comparator without the auxiliary amplifier operates very

slowly when two input voltages (i.e._ _) are lowand the input voltage difference (∆ = _ _) issmall. When is low, the current difference between and(∆= , × ∆) becomes quite small; hence, thevoltage difference on nodes and (∆,= − ) increasesvery slowly. In addition, the voltage amplification on the

nodes and by the cross- coupled latch (−6) is veryslow because the pull-down current of the cross-coupled latchis limited to the drain currents of and6 (i.e., and ).Then, the drain currents significantly decrease proportional to

VIN. Moreover, the comparator without the auxiliaryamplifier does not operate at very low input voltage where the

pull-down current of the cross-coupled latch is very weak. The

auxiliary amplifier (7−9) pulls node or down duringthe second amplifying operation. The comparator with

auxiliary amplifier however increases the sensing speed with

its rapid voltage amplification.The low voltage comparator

schematic and simulation result is shown in the Fig.11 and Fig

12.In the simulation the supply voltage is 600mV and input

voltage difference is 1 mV, _is 130 mV and is_changed from 129 to 131mV.The comparator without theauxilary amplifier canot sense the 1-mV input voltage

difference because of its slow amplifications on the nodes

and .In the comparator,capacitors and are added torecuce the voltage ripples in _ and _.

Fig .11 Low voltage comparator schematic


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Fig.12 Transient response of Low voltage comparator

Charge Pump circuit:

The proposed charge pump circuit as shown Fig.13 adjusts the

gate voltage according to the comparator output value

(CMP_out).

Fig.13 Charge pump circuit

Initially, is discharged to the ground by a positive pulsestartup signal. Transistors , , and 5in Fig. 5 begin toflow currents ,, and, respectively. Two input voltages ofthe comparator (i.e., _and_) increase to near . Afterthe start-up operation, the charge-pump circuit changes

slightly every clock cycle. At the precharge (PC) phase,node is connected to the ground by the PC signal andnode is connected to the ground or according to thecomparator output. At the charge-sharing (CS) phase,

nodeis connected to node by the CS signal and changes from the ground to or from to theground. Output reference voltage is controlled by .TheCharge pump circuit schematic is as shown in Fig. 13 .

Fig.13 Charge pump circuit schmetic

Fig.14 shows the schematic of the proposed volage reference

and the simulation result is shown in Fig 15.The proposedvoltage refere is given by 600mV clock pulse and it is going to

generate required control signals for producing the reference

voltage.This proposed method produces 274 mV reference

voltage at 374 mV and it requires 250mV minimum supply

voltage.

Fig.14 Proposed Subthreshold CMOS voltage reference circuit


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Fig.14 Transient response of proposed voltage reference

Fig.15Variation of supply voltage vs reference voltage

TABLE 1

COMPARSIONS OF LOW-VOLTAGEVOLTAGE REFERENCES

CICC08

[10]

Conventional This work

Process(nm) 90 90 90

Type CMOS CMOS CMOS

Power(µw) 482 7.33 5.35

550 472 374

241 274 274

V. CONCLUSION

In this paper a supply subthreshold CMOS voltage reference

circuit has been proposed.This circuit is based on the CMOS

voltage reference circuit operating at low supply voltage. It

reduces the minimum required supply voltage by replacing the

analog amplifier with the low voltage comparator, charge-

pump circuit, and a control unit circuit. This circuit has been

implemented in 90nm CMOS technology and simulated by

using Cadence virtuoso. The simulated results shown that it

exhibits a reference voltage of 274mv at 374mV supply

voltage. The comparison between the conventional and the proposed design is depicted in Table 1.From this it can be

concluded that the proposed design operates at a low supply

voltage and consumes less power.


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REFERENCES

[1] R.J.Wildar, “New developments in IC voltageregulators,” IEEE J.Solid-State Circuits, vol, SC-6, pp. 2-

7, Feb. 1971.

[2] K. E. Kuijk, “A precision reference voltage source,” IEEE J.Solid-State Circuits, vol, SC-8, pp. 222-226, June 1973.

[3] A.P.Brokaw, “A simple three-terminal IC bandgap

reference,” IEEE J.Solid-State Circuits, vol, SC-9, pp.388-393, Dec.1974.

[4] Y. P. Tsividis and R. W. Uimer, “A CMOS voltagereference,” IEEE J.Solid-State Circuits, vol, SC-13, pp.

774-778, Dec.1978.

[5] Y.Cheng and C. Hu, MOSFET Modeling&BSIM3 user’sGuide, New York: Kluwer, 1999.

[6] P.Malcovati, F. Maloberti, C. Fiocchi and M. Pruzzi ,

“Curvature compensated BiCMOSbandgap with 1-Vsupply voltage", IEEE J. Solid-State Circuits, vol. 36,

no. 7, pp.1076-1081, Jul. 2001

[7] G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrl, “Alow-voltage low-power voltage reference based on

subthreshold MOSFETs,” IEEE J. Solid-State Circuits,

vol. 38, no. 1, pp. 151 – 154, Jan. 2003.[8] V. Ivanov, R. Brederlow, and J. Gerber, “An ultra -low

power bandgap operational at supply from 0.75 V,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1515 – 1523, Jul.2012.

[9] Y. Yang, D. M. Binkley, L. Li, C. Gu, and C. Li, “All-CMOS subbandgap reference circuit operating at low

supply voltage,” in Proc.IEEE ISCAS, 2011, pp. 893 – 896[10] P. Kinget, C. Vezyrtzis, E. Chiang. B. Hung, and T. L.

Li, “Voltage references for ultra-low supply voltages,”inProc. IEEE Custom Integer.Circuits Conf., 2008, pp.715-

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