Cmos and Finfet Tech

7/25/2019 Cmos and Finfet Tech

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FD-SOISphere:Technologies | back-bias, bonded wafer,FD-SOI,multi-t design, partiall! depleted

SOI, Soitec,ST-"ricsson

#hat is FD-SOI and wh! is it useful$

Full! depleted silicon-on-insulator %FD-SOI&, also known as ultra-thin or e'tremel!

thin silicon-on-insulator %"T-SOI&, is an alternati(e to bulk silicon as a substrate for

building )*OS de(ices+ SOI wafers ha(e a shallow la!er of epita'ial silicon grown on

top of an o'ide la!er that acts as an insulator+ The top silicon la!er is full! depleted,

that is, it doesnt ha(e an! intrinsic charge carriers, which has a number of

ad(antages when building deep submicron de(ices+

Transistors built on FD-SOI ha(e a (er! thin %shallow& channel, which impro(es the

gates abilit! to remo(e carriers from that channel when the de(ice needs to be

switched O+ In principle, FD-SOI oers better performance than con(entional bulksilicon on deep submicron process technologies, with particular bene.ts for low-

power circuits+ /roponents of FD-SOI argue that, although the resultant de(ices

current dri(e is poorer than in bulk processes, the drain-induced barrier lowering

%DI01& that plagues deep submicron processes b! making it more di2cult to turn

de(ices O is greatl! reduced b! the presence of the insulating o'ide la!er directl!

beneath the channel+

3ccording to the SOI Industr! )onsortium, benchmarks show that using FD-SOI

makes it possible to reduce the operating (oltage in S43* cells b! 566-576m+

)utting the (oltage in regular )*OS has pro(ed di2cult because of concerns o(er

(ariabilit!, as it slashes the static noise margin and so increases the probabilit! of

errors in the memor! arra!+ The )onsortium claims that the operating-(oltage

reduction aorded b! FD-SOI enables a 86 per cent reduction in memor!-arra!

power consumption+

3nother potential ad(antage of FD-SOI o(er the .nF"T, its nearest competitor for

sub-9nm processes, is that the approach makes it possible to back-bias the

channel and so gain greater control o(er the charge carriers ;owing through it+

#hat eect does FD-SOI ha(e on design$

The use of a (er! thin channel deals with one of the main design problems ofpre(ious, partiall! depleted SOI implementations that used thicker silicon channels+

This is the tendenc! for electrical charge to remain under the gate once a transistor

has been turned O+ This


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In principle, it is possible to directl! port a cell librar! from a bulk process on to an

FD-SOI process+ =owe(er, the results will not be as good as dedicated cell libraries

designed to take ad(antage of the dierent balance of capacitances in FD-SOI

de(ices and the reduced (ariabilit! of undoped channels, which should impro(e

static noise margin in S43*s+ Subthreshold leakage should be greatl! reduced with

FD-SOI and the SOI )onsortium claims that criteria important to analog design, suchas transconductance, also bene.t from undoped channels+

The SOI )onsortium has proposed that a bulk co-integration+ In this approach, I/ cores that are deemed

too risk! to redesign are placed on to areas of the wafer that e'pose the bulk

silicon, while s!nthesi?ed logic optimi?ed to use FD-SOI structures and design rules

is placed on to areas of the wafer that e'pose FD-SOI+

0asic models are a(ailable for simulating FD-SOI designs in Spice although more

ad(anced models that take into account surface eects are still in de(elopment,

with industriali?ation e'pected in the near future+

The biggest impact on design will come from a proposed ad(antage of FD-SOI: the

abilit! to d!namicall! back-bias the channel, which gi(es better control and so

impro(es de(ice switching speed+ One ad(antage of using back-bias in FD-SOI is

that its eect does not diminish with decreasing de(ice si?e in the wa! that it does

for bulk silicon+

*ulti-t circuitr! is more complicated to implement on FD-SOI than with bulk silicon

processes because channel doping cannot be used to alter the threshold (oltage+

Instead, the threshold (oltage is controlled b! tuning the gate stack materials+

=owe(er, a combination of doping and acti(e biasing can be used to alter thethreshold of a target group of transistors that ha(e a common sub-o'ide backplane+

The contacts and implant regions for these groups ha(e to be de.ned at design

time+ One further possibilit! is to use channel-length modulation, similar to that

used in bulk processes to reduce leakage in slower transistors+ =owe(er, the t

rollo is less pronounced in FD-SOI than with comparable bulk-silicon de(ices+

One potential issue with designing for FD-SOI is that of self-heating, similar to that

encountered with .nF"Ts, because the ultra-thin narrow channel lies on top of a

poor thermal conductor+ =owe(er, this is not e'pected to aect low-power circuits,

which remain the primar! target for proponents of FD-SOI-based designs+

#hen and where can I use FD-SOI$

Following a deal between @lobalFoundries and ST*icroelectronics, which said at the

beginning of 9659 it would bu! suitable wafers from bonded-wafer specialist Soitec

for 9nm FD-SOI mobile-phone de(ices, foundr! users will be able to access the

technolog! at @lobalFoundries fabs from 965A+ ST will run its own de(ices either at
http://www.soiconsortium.org/pdf/fullydepletedsoi/SOIconsortium_FDSOI_design.pdfhttp://www.soiconsortium.org/pdf/fullydepletedsoi/SOIconsortium_FDSOI_design.pdfhttp://www.techdesignforums.com/blog/2012/06/11/fd-soi-st-globalfoundries-deal/http://www.soiconsortium.org/pdf/fullydepletedsoi/SOIconsortium_FDSOI_design.pdfhttp://www.soiconsortium.org/pdf/fullydepletedsoi/SOIconsortium_FDSOI_design.pdfhttp://www.techdesignforums.com/blog/2012/06/11/fd-soi-st-globalfoundries-deal/


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its relati(el! small )rolles plant, where its FD-SOI process was de(eloped, or at the

@lobalFoundries 9nm and 96nm-capable fabs+

#hat are the risks and downsides of FD-SOI$

The primar! problems with FD-SOI lie in the suppl! chain+ 3lthough it is possible to

create the o'ide la!ers on bulk silicon wafers and then use epita'! to de.ne silicon

channels on the surface, the surface Bualit! needed for nanometer processes is best

supported through the use of speciali?ed, bonded SOI wafers+ 3s with an! non-

mainstream process, these wafers are more e'pensi(e although some cost sa(ings

could be achie(ed through simpler processing at the transistor-building stage+ For

e'ample, the channel does not need to be doped, which causes fewer problems

with (ariabilit! and, therefore, de(ice !ield+

3lthough basic models are a(ailable and research eorts ha(e generated

increasingl! accurate de(ice-le(el models, some of the eects seen in nanometre-

scale FD-SOI de(ices are not !et taken into account in industrial-grade models+

Double patterning for sub-28nm ICs

Sphere:Technologies | double patterning, lithograph!

What is it?

Double patterning is a techniBue used in the lithographic process that de.nes thefeatures of integrated circuits at ad(anced process nodes+ It will enable designers to

de(elop chips for manufacture on sub-A6nm process nodes using current optical

lithograph! s!stems+ The alternati(e is to wait for the de(elopment of commerciall!

(iable steppers using e'treme ultra(iolet illumination sources, masks and stepper

technologies+

The downsides of using double patterning include increased mask %reticle& and

lithograph! costs, and the imposition of further restrictions on the wa!s in which

circuits can be laid out on chip+ This aects the comple'it! of the design process

and the performance, (ariabilit! and densit! of the resultant de(ices+

What does double patterning do and why do we need it?

Double patterning counters the eects of diraction in optical lithograph!, which

happens because the minimum dimensions of ad(anced process nodes are a

fraction of the 5CAnm wa(elength of the illuminating light source+ These diraction

eects makes it di2cult to produce accuratel! de.ned deep sub-micron patterns

using e'isting lighting sources and con(entional masks: sharp corners and edges
http://www.techdesignforums.com/practice/sphere/technologies/http://www.techdesignforums.com/practice/tag/double-patterning/http://www.techdesignforums.com/practice/tag/lithography/http://www.techdesignforums.com/practice/sphere/technologies/http://www.techdesignforums.com/practice/tag/double-patterning/http://www.techdesignforums.com/practice/tag/lithography/


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become blurs, and some small features on the mask wont appear on the wafer at

all+

3 number of reticle enhancement techniquesha(e been introduced to counteract

the diraction problem as it has become more acute with each new process node+

Phase-shift maskswere introduced at the 56nm process node+ The! alter the

phase of the light passing through some areas of the mask, changing the wa! it is

diracted and so reducing the defocusing eect of mask dimensions that are less

than the wa(elength of the illuminating light+ The downside of using phase-shift

techniBues is that the masks are more di2cult and e'pensi(e to make+

Optical-proximity correction%O/)& techniBues work out how to distort the patterns

on a mask to counter diraction eects, for e'ample b! adding small


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Theres a look at how computational lithograph! has e(ol(ed o(er the past 59

!ears here, and an interesting discussion of the potential of source-mask

optimisation and alternati(e illumination techniBues in a paper here+

Double patterning is another techniBue used to e'tend the useful lifetime of 5CAnm

lithograph!+ The process splits dense patterns into two interlea(ed patterns of less-dense features, de.ned b! two masks+ @i(en su2cientl! accurate alignment, the

two patterns marr! up on the wafer surface to create much denser features than

could be achie(ed with one mask+

Where an I use it?

Double patterning will be necessar! to de.ne the critical la!ers of designs being

built using 5CAnm illumination on process nodes below A6nm+

What are the ris!s of using double patterning?

Design restrictions+ Double patterning will work best on designs whose criticalla!ers can be split into two separatel! de.ned but aligned patterns in a

predictable wa!+ This means that producing a design la!out that looks like a

diraction grating is good, while a design littered with diagonal lines, ogs,

and (ias between la!ers ma! be less eas! to split eecti(el!+

)ost+ Double patterning is e'pensi(e because it uses two masks to de.ne a

la!er that was de.ned with one at pre(ious process nodes+ This means

bu!ing more steppers to maintain a fabs throughput+

ariabilit!+ The emphasis on more regular la!out with long linear tracks ma!

make designs more susceptible to the performance (ariabilit! brought on b!limited control of the roughness of the edges of patterned +

3lignment issues+ Double patterning brings alignment issues on to critical

la!ers, rather than between la!ers as before, with a potential impact on

design performance and production !ield+

Who is in"ol"ed in de"eloping double patterning?

Successfull! implementing double patterning means drawing on skills and insight

from across the semiconductor industr!, including I) makers, eBuipment and

materials companies, mask makers, meteorologists, design-tools companies andresearch organisations+ For e'ample, the "uropean 1"ES proect is a consortium of

59 companies working together to create the technological infrastructure and

suppl! chain for double patterning+
http://www.techdesignforums.com/eda/document/computational-lithography-enabling-12-technology-nodes-in-12-years/http://www.techdesignforums.com/eda/document/demonstrating-the-benefits-of-source-mask-optimization-and-enabling-technologies-through-experiment-and-simulations-2/http://www.techdesignforums.com/eda/document/computational-lithography-enabling-12-technology-nodes-in-12-years/http://www.techdesignforums.com/eda/document/demonstrating-the-benefits-of-source-mask-optimization-and-enabling-technologies-through-experiment-and-simulations-2/

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