Cluster-based Localization of IR-drop in TestApplication considering Parasitic Elements

Harshad Dhotre∗ Stephan Eggersglu߇ Rolf Drechsler∗†∗Institute of Computer Science, University of Bremen, 28359 Bremen, Germany

†Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany‡Mentor, A Siemens Business, Hamburg, Germanydhotre@uni-bremen.de, drechsler@uni-bremen.de

Abstract—Highly compact test patterns are vulnerable to IR-drop during testing which might lead to failures or breakdowns.An accurate analysis of all test patterns is infeasible due to theexcessive analysis run time. Previous switching activity based IR-drop prediction methods are highly approximate since less data isused to analyze the test set. In this paper, we propose a dynamicIR-drop prediction methodology, which considers resistive andcapacitive parasitic elements of the circuit together with theswitching activity. The proposed method uses machine-learningbased clustering and is more accurate than the general switchingbased method. More importantly, the methodology is fast enoughthat the complete test set can be processed to identify vulnerablepatterns prone to IR-drop failure. The experiments show theeffectiveness of the proposed approach for the approximateanalysis of the complete test set.

I. INTRODUCTION

The testing standards are becoming more complex with theroll out of the sub-nano range process technology. Due tothe increasing design sizes (in terms of number of gates), theamount of test data is steadily increasing. The use of DFT andscan architectures leads to a highly non-functional behaviorduring the test, resulting often in increased switching activity.The high switching of power demand during testing may resultinto test failures. This failure during testing results into yieldloss thereby increasing the production cost per unit. Hence,a pre-production test pattern analysis is typically performedin order to mitigate this effect and identify power-risky tests.This is particularly done for IR-drop [5], [10].

The identification of power-risky tests from the test setis difficult, since previous methods are mainly based onswitching activity. However, dynamic IR-drop effects do notonly depend on the switching activity but also on the resistiveand capacitive elements of the local area. The accurate analysisof all test patterns needs very long run time and can last forweeks or even months for complex designs. Especially thefact that the needed technology-relevant data is only availablevery late in the design flow makes the analysis infeasible forthe complete test set. Previous methods, e.g. using WeightedSwitching Activity (WSA), to speed-up the analysis are highlyapproximate since they are mainly based on toggle informa-tion and neglect circuit elements like capacitive and resistivecomponents. ATPG tools typically provide only the WSAvalues of tests and report only the global power dissipation.However, it is also important to identify localized hot spots.These approximate methods are fast but not accurate enoughto provide a reliable result whether a test is power-risky or not.

In previous work, we proposed a separate test pattern analysismethodology [2], [3], which uses machine-learning techniquesto analyze all tests and localize critical areas.

In this work, we improve the proposed methodology forthe localization of dynamic IR-drop. Additional parametersare considered to localize the possible voltage drop acrossthe layout more accurately. In the proposed method, weuse machine-learning based unsupervised dynamic clusteringtechniques. Besides technology and layout data as well as thepower activity, the integration of parasitic elements like net,pin resistance and capacitance is proposed. A combined viewis used to localize possible IR-drop hot spots. This informationmakes it able to take necessary actions to avoid pattern failure.Even though the method considers limited data, it is ableto process all test patterns, which is not possible for highlyaccurate IR-drop analysis. The experimental results show thatthe localization can be improved as compared to the previousmethod.

II. RELATED WORK

The voltage drop across the line or grid area can be ideallyestimated with the help of a transistor level model and asimulation, where the current and voltage variation graph andother material characteristics are used to calculate IR-drop.However, applying the same method for a large circuit withbillions of transistors is infeasible. For an accurate enough sim-ulation of complex circuits, cell level information is used byEDA tools. However, it still involves a very high computationalcomplexity and much resources [6], [11]. Since it is dependenton various levels of simulation results like SPICE, timing,STA, VCD data etc. it is highly time consuming. Several othermethods have been proposed before which are approximatebut fast enough to estimate the IR-drop effect. However, mostmethods deal with the analysis of the functional mode as wellas with corner case scenarios and not with test patterns. Themethod proposed in [8] estimates the IR-drop by using libraryinformation and gate level data but in an analytical way. Themodel used in [7] uses uniform current profiles and someapproximations to predict IR-drop at grid centers.

The method proposed in [1] uses Switching Cycle AveragePower (SCAP) to correlate and estimate the IR-drop and usedit for noise-aware pattern generation for transition delay faults.A similar other method [12] uses global cycle average poweras measurement to predict IR-drop for a few at-speed testpatterns. However these methods are also approximate andthe complete test pattern set cannot be analyzed. In contrast978-1-7281-1756-0/19/$31.00 c©2019 IEEE

to previous methods, the proposed method (although beingapproximate) is able to integrate a large range of data tobe more accurate, but still is fast enough to process all testpatterns. This makes the methodology suitable to be used forpower-risky test pattern identification.

III. PRELIMINARIES

During the system design flow, many analysis and simula-tion tasks are performed in order to avoid failures and preventyield loss. The analysis on higher abstraction levels likeESL or SystemC is not much accurate especially for effectslike IR-drop since these require the physical implementation.The power analysis, specifically IR-drop analysis, is thereforeperformed when the physical design is completed and frozen.In the following, the effect of IR-drop is discussed in moredetail followed by its consequences on testing.

IR-drop Background: The voltage drop is an unavoidable(even though it may range from mV to nV) phenomenon whichoccurs in-between the power source and the design unit. Themulti-layer structure of the circuit has different metal layers fordifferent routing purposes and other circuits elements layeredby deposition, itching and other lithographic processes. Thepower grid is routed from a supply ’Pin’ to power strips attop layers and runs through ’Vias’ following different routesto supply ’VDD’ at lower layers. Thus, the long route of the’VDD’ to reach each individual circuit element or design unitresults into a voltage drop referred to as IR-drop. Due to thematerial dependent characteristics like resistance, capacitanceand other system dependent parameters like switching activity,they are broadly classified into Static and Dynamic IR-drop.Different power grid structures are used like power rings,patches, strips, macro lines etc. at various levels of the die.

ATPG, Test Patterns and IR-drop Failure: The test syn-thesis involves scan chain formation and the integration of atest architecture during the RTL to GDS synthesis process.Test synthesis is an important step since it also generates thetiming related information, scan chain loading-unloading dataand other useful information which is used for the patterngeneration, simulation, debugging, diagnosis as well as forthe Automatic Testing Equipment (ATE) test application inreal time. The test patterns are generated with the help ofan Automatic Test Pattern Generator (ATPG). This task isperformed after the test synthesis.

A generated test pattern may fail during the post-productiontest due to IR-drop effects and other reasons if precautionarymeasures are not taken before. Therefore, test pattern simula-tion, debugging and diagnosis is used to prevent failures duringthe post-production test. The false capture in scan cells mayhappen due to timing violations caused by a high voltage dropin that area where a clear cluster of failing flip-flops can beobserved. But the tool provides only mesh like information ofvoltage values or contours of voltage. The remaining diagnosiseffort is mostly manual with high human efforts. Whereasin our proposed work, the machine-learning based dynamicclustering helps to identify the scan cells and other instancesresponsible for the same. With our automated approach, theanalysis and planning of further protective actions like patternretargeting [4] to prevent test failures becomes easier.

Fig. 1: Proposed analysis with major inputs

IV. PROPOSED METHOD

The pre-production simulation and power analysis havebecome sign-off standard. But this kind of power analysis ishighly resource consuming. Therefore, it is only performedfor the corner cases. However, the corner cases are difficultto predict for testing because most of the test patterns havecorrelated switching activity. The timing simulation is usedto generate switching data, e.g. a VCD file, and huge otherdatabases required to perform dynamic IR-drop analysis. TheIR-drop analysis for all the test patterns is not feasible dueto excessive run time. Our method addresses this problem byusing limited data to approximately identify the test patternsprone to IR-drop failure and localizes the area with clusteringtechniques. More importantly, it analyzes all the test patternswith more accuracy (compared to WSA) as it considerstechnology and layout data, as well as parasitic elements.

Figure 1 shows the proposed method and major inputblocks. The pattern analysis and IR-drop hotspot block isthe processing block which integrates all the data as well asperforms the calculations, clustering and smoothed hot spotestimation. The estimation process is explained in the sectionbelow. The required data is extracted from different files andused as input. The following itemization lists the informationblocks needed for the calculation.

• The cell tech library, i.e. liberty (.lib), is processed toextract the cell features like pin capacitance, resistanceand power factors of library elements used for the TPAcalculation [2].

• The verilog netlist (.v) is processed to extract the nameof instances, nets and other data.

• Physical location features of the cells are extracted fromthe Layout Exchange Format(.lef) file.

• Physical layout of the design (.def) file is used for theextraction of the location of the power grid, instances,pins, wires, vias etc.

• Parasitic elements values as features are extracted fromthe SPEF file.

• The test pattern simulation database provides the togglinginformation of each instance for each pattern. This isparticularly used to calculate the TPA values [2].

For the prediction of the IR-drop hotspots for each pattern,we calculate the Transient Power Activity (TPA) value (moreaccurate version of WSA [2]) for each and every instance inthe design. Unsupervised learning-based k-means clustering

is then used to dynamically cluster the power activity onthe layout [3]. The switching activity (in our case poweractivity) is a major factor causing the dynamic IR-drop effect.However, it is not the only factor because the resistive and thecapacitive features are also important. It may be possible thatthe power distribution is sufficiently strong enough to drivethe load in a high switching area without causing a voltagedrop. Vice-versa, IR-drop can be caused when the power orswitching activity is low in a particular area but the resistiveand capacitive factors are high. Hence, the consideration ofcapacitive and resistive elements is necessary.

Fig. 2: Clustered smoothing resistance, capacitance and poweractivity

In the proposed extended approach, the cluster-basedmethod is used to determine the resistive and capacitive profileof the layout. It is followed by a smoothing of the results toestimate and identify the hotspot. Each individual value of apin capacitance and instance is not useful on its own becauseof the discrete nature. The dynamically clustered versionprovides the profile indicating the cluster prone to IR-drop dueto the high capacitive nature of the corresponding area as wellas the volatility to voltage drop. The latter also depends on theswitching in the corresponding area. The clustering of the pincapacitance is performed with the k-means clustering approachwhich is also used to cluster the power activity. Similarly, thenet resistance and capacitance values are clustered and thecluster results are stored for the further integration with theswitching or power activity clusters.

The complete integration can be imagined as the over-lapping of all the cluster results together, i.e. combiningthe normalized values of the capacitive, resistive and poweractivity clusters of each test pattern. It is computed withthe help of Matrices, where the rows and columns representthe X,Y coordinates and their corresponding values. Figure 2shows a pictorial representation of the Clustered Power (C P)activity layout layer, overlapped on the Clustered Smoothed(C S) Resistance layer and the Clustered Smoothed (C S)Capacitance layer. The overall output is a new layer whichis a combination and overlapping of all these layers accordingto their X,Y coordinates. This new layer is then smoothed to

Fig. 3: Estimated IR-drop hotspot of the ’wb conmax’ design

identify the critical regions. Red-brown areas indicate areasprone for IR-drop which can be further analyzed.

The normalization and smoothing process causes that thevalues lose their units. Therefore, the result provides thepotential dynamic IR-drop areas only and not the actual valuesof the voltage drop. The advantage of the proposed methodis that it does not involve the actual specific voltage dropcalculation which is computationally expensive (infeasible forall test patterns) but the combination of the relevant data suchas the power/switching activity and parasitic elements in anapproximation process to pinpoint to IR-drop prone regions.

V. EXPERIMENTAL RESULTS

The experiments were performed on benchmarks circuits,i.e. OpenCores. Industrial tools were used for synthesis, testpattern generation and simulation purpose. The test patternanalysis, clustering and the complete methodology is per-formed with the help of inhouse tools [3] and python scripts[9]. For the integration into a design flow, tcl and perl scriptingis used. The power metric used for the experiments is TPA [2]as well as WSA.

Table I shows the results of the analysis. The table is dividedinto two parts. At the left hand side, the results for the analysiswithout the consideration of parasitic elements is given. Atthe right hand side, the results of the proposed approachconsidering parasitic elements are given. Since the dynamicIR-drop estimation is pattern-dependent, the integration of allparasitic elements and the switching activity of each patternresults in different values and hot-spots for each pattern. Allthe test patterns of a generated test set are analyzed andinformation about the worst test patterns are shown in thetable. The id of the pattern as well as the id for the clusterwhich were identified as highest IR-drop prone is given.Additionally, X, Y coordinates are given to identify the clustercenter and the corresponding Low-power Metric comparativevalue (#LM). Figure 3 depicts the dynamic IR-drop hot spotsestimated for the test pattern number ’50’ of the ’wb conmax’benchmark. The normalized local metric does not provide theactual value of the voltage drop but the comparative value withreference to its neighboring values. Additionally, the cluster

TABLE I: IR-drop prone areas without and with parasitic elements consideration

Benchmarks Before considering parasitic elements After considering parasitic elementsPattern Cluster X coordinate Y coordinate #LM Pattern Cluster X coordinate Y coordinate #LM

ac97 ctrl

38 19 978.6563 823.5846 0.1535 6 20 699.4555 811.9013 0.137345 15 577.8820 1178.7561 0.1434 29 28 581.1795 825.2170 0.132827 19 978.6563 823.5846 0.1429 66 30 577.2790 915.9127 0.130826 19 499.2171 799.8614 0.1427 70 28 577.2790 915.9127 0.1299

wb conmax

30 1 248.4026 931.4846 0.2196 30 3 912.7167 1081.5489 0.1964136 36 565.6710 1146.1777 0.2123 118 31 633.6348 1030.2816 0.1958

93 25 1419.3021 2057.0292 0.2110 161 26 1226.7602 1609.8023 0.1950116 17 1026.6603 1190.1135 0.2110 122 3 912.7167 1081.5489 0.1923

pci bridge32

116 37 1419.0831 428.5870 0.1494 116 31 1264.6494 1080.3577 0.182134 31 1164.9611 617.8995 0.1476 111 14 1126.1164 1446.5122 0.181079 37 1419.0831 428.5870 0.1474 34 14 1126.1164 1446.5122 0.1809

118 0 1467.6890 1120.4654 0.1426 79 31 1264.6494 1080.3577 0.1775

ethernet

59 12 2268.4379 1272.9824 0.1285 59 12 1983.7354 1253.1622 0.124427 20 346.8780 3097.7883 0.1257 25 9 1286.7491 1633.6190 0.100264 36 2259.9814 1795.7272 0.1250 64 20 1290.4436 2291.5658 0.099759 3 1780.6550 1043.7184 0.1237 14 18 1330.1136 1474.9029 0.0977

data contains the corresponding instance information wherethe voltage drop is severe.

The identification of the clusters is important since counter-actions to reduce the IR-drop depend on the cluster infor-mation. When comparing the results of the methods withoutand with considering parasitic elements, it can be observedthat slightly different clusters are identified and the accuracyis increased using the new method. For example, the patternnumber ’38’ and cluster ’19’ was estimated as critical for the’ac97 ctrl’ design but the capacitive and resistive network wasreliable enough. This can be seen by taking the new data intoaccount. The actual worst hotspot was in pattern number ’6’and cluster ’20’ which is the result of the proposed method.The location of this new determined cluster is on the boundaryof the old cluster, which can be seen by comparing the Ycoordinates. But for some rare cases like ’ethernet’, the samecluster (12) and the same pattern number (59) is identified.

In summary, it can be seen that the proposed method whichtakes more data into account results in a different IR-drophotspot identification and, by this, increases the accuracy ofthe IR-drop prediction.

VI. CONCLUSION AND FUTURE WORK

Failure analysis of the test patterns is a cumbersome task,the ATPG simulation is insufficient to consider the effects ofIR-drop because of the complexity of the calculations. Theprevious WSA-based methods are technology independent andnot much accurate. Whereas the accurate IR-drop analysisof all test patterns is infeasible due to resource constraints.Our proposed methodology balances both accuracy and com-pleteness of the IR-drop prediction for the complete testset. The method is approximate enough, as it considers thepower activity and parasitic elements together to estimate thedynamic IR-drop values for each pattern. The method depictsthe dynamic IR-drop hotspot along with the clustered resultset. The experiments show that the proposed improvementin estimation by considering the parasitic elements are moreaccurate as compared to previous methods. The cluster-basedmethodology provides ease of automation by the localization

of instances via clusters which helps to take precautionarymeasures, e.g. regenerating the test patterns to avoid dynamicIR-drop. The approach can be extended in future consideringadditional design data as well as moving towards simulation-less prediction through machine learning based regressionmethods.

VII. ACKNOWLEDGMENTThe work has been supported by the German Research

Foundation (DFG) under contract number EG 290/5-1.

REFERENCES

[1] N. Ahmed, M. Tehranipoor, and V. Jayaram, “Transition delay fault testpattern generation considering supply voltage noise in a soc design,” inDesign Automation Conf., 2007, pp. 533–538.

[2] H. Dhotre, S. Eggersgluß, M. Dehbashi, U. Pfannkuchen, and R. Drech-sler, “Machine learning based test pattern analysis for localizing criticalpower activity areas.” in IEEE Int’l Symp. on Defect and Fault Tolerancein VLSI Systems, 2017, pp. 1–6.

[3] H. Dhotre, S. Eggersgluß, and R. Drechsler, “Identification of efficientclustering techniques for test power activity on the layout,” in IEEEAsian Test Symp., 2017, pp. 108–113.

[4] H. Dhotre, S. Eggersgluss, R. Drechsler, M. Dehbashi, andU. Pfannkuchen, “Constraint-based pattern retargeting for reducinglocalized power activity during testing,” in IEEE Symp. on Design andDiagnosis of Electronic Circuits and Systems, 2018, pp. 79–84.

[5] P. Girard, N. Nicolici, and X. Wen(Eds.), Power-Aware Testing and TestStrategies for Low Power Devices. Springer, 2009.

[6] P. Girard, N. Nicolici, and X. Wen, Power-aware testing and teststrategies for low power devices. Springer Science & Business Media,2010.

[7] D. Khalil and Y. Ismail, “Optimum sizing of power grids for ir drop,”in IEEE Int’l Symp. on Circuits and Systems, 2006, pp. 4–pp.

[8] M.-S. M. Lee, K.-S. Lai, C.-L. Hsu, and C.-N. J. Liu, “Dynamic ir dropestimation at gate level with standard library information,” in IEEE Int’lSymp. on Circuits and Systems, 2010, pp. 2606–2609.

[9] F. Pedregosa, G. Varoquaux, A. Gramfort, V. Michel, B. Thirion,O. Grisel, M. Blondel, P. Prettenhofer, R. Weiss, V. Dubourg, J. Vander-plas, A. Passos, D. Cournapeau, M. Brucher, M. Perrot, and E. Duch-esnay, “Scikit-learn: Machine learning in Python,” Journal of MachineLearning Research, vol. 12, pp. 2825–2830, 2011.

[10] M. Tehranipoor and N. Ahmed, Nanometer Technology Designs: High-Quality Delay Tests. Springer, 2007.

[11] L.-T. Wang, Y.-W. Chang, and K.-T. T. Cheng, Electronic designautomation: synthesis, verification, and test. Morgan Kaufmann, 2009.

[12] Y. Yamato, T. Yoneda, K. Hatayama, and M. Inoue, “A fast and accurateper-cell dynamic ir-drop estimation method for at-speed scan test patternvalidation,” in Int’l Test Conf., 2012, pp. 1–8.