7/28/2019 Clocked Cmos

1/24

40 60 80 100 120

40

60

80

mm

12. Dynamic CMOS Logic

J. A. Abraham

Department of Electrical and Computer Engineering

The University of Texas at AustinEE 382M.7 VLSI I

Fall 2011

October 10, 2011

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 1 / 23

7/28/2019 Clocked Cmos

2/24

40 60 80 100 120

40

60

80

mm

Dynamic Logic

Dynamic gates use a clocked pMOS pullup

Two modes of operation: precharge and evaluate

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 1 / 23

7/28/2019 Clocked Cmos

3/24

40 60 80 100 120

40

60

80

mm

The Foot Transistor

What if pulldown network is ON during precharge?Use series evaluation transistor to prevent fight betweenpMOS and nMOS transistors

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 2 / 23

7/28/2019 Clocked Cmos

4/24

40 60 80 100 120

40

60

80

mm

Logical Effort

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 3 / 23

7/28/2019 Clocked Cmos

5/24

40 60 80 100 120

40

60

80

mm

Monotonicity

Dynamic gates require monotonicallyrising inputs during evaluation

0 0

0 1

1 1

But not 1 0

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 4 / 23

7/28/2019 Clocked Cmos

6/24

40 60 80 100 120

40

60

80

mm

Monotonicity Woes

But dynamic gates produce monotonically falling outputsduring evaluation

Illegal for one dynamic gate to drive another!

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 5 / 23

7/28/2019 Clocked Cmos

7/24

40 60 80 100 120

40

60

80

mm

Domino Gates

Follow dynamic stage with inverting static gate

Dynamic/static pair is called domino gateProduces monotonic outputs

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 6 / 23

7/28/2019 Clocked Cmos

8/24

40 60 80 100 120

40

60

80

mm

Domino Optimizations

Each domino gate triggers next one, like a string of dominostoppling over

Gates evaluate sequentially, precharge in parallelEvaluation is more critical than prechargeHI-skewed static stages can perform logic

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 7 / 23

7/28/2019 Clocked Cmos

9/24

40 60 80 100 120

40

60

80

mm

Dual-Rail Domino

Domino only performs noninverting functions:

AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem

Takes true and complementary inputsProduces true and complementary outputs

sig h sig l Meaning

0 0 Precharged

0 1 01 0 1

1 1 Invalid

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 8 / 23

E l AND/NAND

7/28/2019 Clocked Cmos

10/24

40 60 80 100 120

40

60

80

mm

Example: AND/NAND

Given A h, A l, B h, B l

Compute Y h = A * B, Y l = (A * B)Pulldown networks are conduction complements

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 9 / 23

E l XOR/XNOR

7/28/2019 Clocked Cmos

11/24

40 60 80 100 120

40

60

80

mm

Example: XOR/XNOR

Sometimes possible to share transistorsSharing works well in implementations of symmetric functionsSee papers on relay logic published over 50 years ago

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 10 / 23

L k

7/28/2019 Clocked Cmos

12/24

40 60 80 100 120

40

60

80

mm

Leakage

Dynamic node floats high during evaluationTransistors are leaky (Ioff = 0)

Dynamic value will leak away over timeFormerly milliseconds, now nanoseconds!Use keeper to hold dynamic node

Must be weak enough not to fight evaluation

Leakage Power!

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 11 / 23

Ch Sh i

7/28/2019 Clocked Cmos

13/24

40 60 80 100 120

40

60

80

mm

Charge Sharing

Dynamic gates suffer from charge sharing

Vx = Vy =Cy

Cx + CyVDD

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 12 / 23

S d P h g

7/28/2019 Clocked Cmos

14/24

40 60 80 100 120

40

60

80

mm

Secondary Precharge

Solution: add secondary precharge transistors

Typically need to precharge every other node

Big load capacitance on Y helps as well

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 13 / 23

Noise Sensitivity

7/28/2019 Clocked Cmos

15/24

40 60 80 100 120

40

60

80

mm

Noise Sensitivity

Dynamic gates are very sensitive to noiseInputs: VIH VtnOutputs: floating output susceptible noise

Noise sourcesCapacitive crosstalkCharge sharingPower supply noiseFeedthrough noise

And more!Chip power supply voltage map

when executing a program

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 14 / 23

Alternating N & P Domino Logic

7/28/2019 Clocked Cmos

16/24

40 60 80 100 120

40

60

80

mm

Alternating N & P Domino Logic

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 15 / 23

Cascade Voltage Switch Logic (CVSL)

7/28/2019 Clocked Cmos

17/24

40 60 80 100 120

40

60

80

mm

Cascade Voltage Switch Logic (CVSL)

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 16 / 23

Dynamic CVSL XOR Gate

7/28/2019 Clocked Cmos

18/24

40 60 80 100 120

40

60

80

mm

Dynamic CVSL XOR Gate

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 17 / 23

Dual-Rail Domino Full Adder Design

7/28/2019 Clocked Cmos

19/24

40 60 80 100 120

40

60

80

mm

Dual-Rail Domino Full Adder Design

Very fast, but large and power hungry

Used in very fast multipliers

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 18 / 23

Manchester Adders

7/28/2019 Clocked Cmos

20/24

40 60 80 100 120

40

60

80

mm

Manchester Adders

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 19 / 23

Domino Summary

7/28/2019 Clocked Cmos

21/24

40 60 80 100 120

40

60

80

mm

Domino Summary

Domino logic is attractive for high-speed circuits

1.5 2x faster than static CMOS

Many Challenges

MonotonicityLeakageCharge sharingNoise

Used in previous generation high-performance microprocessors

and in some recent embedded processors

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 20 / 23

Domino Logic in Current Designs

7/28/2019 Clocked Cmos

22/24

40 60 80 100 120

40

60

80

mm

Domino Logic in Current Designs

Domino design from Intrinsity used in 1-GHz 0.75W ARMCortex A8 from Samsung (Intrinsity later acquired by Apple)

Fast Domino (called Fast14 NDL) gates are insertedselectively into critical speed paths, with custom SRAMs andoptimized synthesized logic elsewhereStandard power saving techniques are also usedDomino gates are clocked by multiphase clocks

A type of super-pipeline where the domino footers form thebarrier for the pipeline operation

(Source: Electronic Design Embedded, August 29, 2009)

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 21 / 23

Intrinsity OR/NOR Implementation with N-nary Logic

7/28/2019 Clocked Cmos

23/24

40 60 80 100 120

40

60

80

mm

Intrinsity OR/NOR Implementation with N nary Logic

2-bit function using 1-out-of-4 signals

Ref: U. S. Patent 6066965, Method and apparatus for a N-naryLogic Circuit Using 1 of 4 Signals

ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 22 / 23

Intrinsity XOR/Equivalence Implementation

7/28/2019 Clocked Cmos

24/24

40 60 80 100 120

40

60

80

mm

y O / q p

Using 1-out-of-2 signals

Ref: U. S. Patent 6066965, Method and apparatus for a N-nary

Logic Circuit Using 1 of 4 SignalsECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic J. A. Abraham, October 10, 2011 23 / 23