Clock & Control Card Status 31 March 2009 Martin Postranecky / Matt Warren

Clock & Control Card StatusClock & Control Card Status

31 March 200931 March 2009

Martin Postranecky / Matt WarrenMartin Postranecky / Matt Warren

31 Mar. 2009 Martin Postranecky / Matt Warren 2

CALICE CCC – First PrototypeCALICE CCC – First Prototype


CALICE CCC – First PrototypeCALICE CCC – First Prototype


CCC - Custom HardwareCCC - Custom Hardware

CPLD

Debug Header

SMAs (vertical)

Add-ons interface

HDMIs

LEMO (NIM)

RS232


SW

PCB HeaderPCB Header

4x4x44

44

8x LVDS 8x LVDS on HDMIon HDMI

8x LVDS 8x LVDS on SMAon SMA




LVDS LVDS on SMAon SMA

LVTTL LVTTL on Lemoon Lemo

NIM/TTLNIM/TTL on Lemo on Lemo


4x LVDS 4x LVDS on SMAon SMA4x NIM4x NIM on Lemo on Lemo

2x NIM2x NIM on Lemo on Lemo

2x LVTTL 2x LVTTL on Lemoon Lemo


NIMNIM on Lemo on Lemoo/c TTL o/c TTL on Lemoon Lemo

CLOCKCLOCK

ASYNCASYNC

GEN GEN (was BUSY)(was BUSY)

Controls Controls (SYNCCMD, BUSY-IN etc)(SYNCCMD, BUSY-IN etc)

X-TALX-TAL

MPX MPX +PLL+PLL

SW-2 SW-2 5->15->1

SW-3 SW-3 2->12->1

AUTO/ AUTO/ XTAL SWXTAL SW

~50 MHz~50 MHz

44

RS232RS232

CCC - Overview SchematicCCC - Overview Schematic

CPLDCPLD(Xilinx(Xilinx

CoolrunnerCoolrunnerXCR3128XL-7)XCR3128XL-7)

8x LVDS 8x LVDS on HDMIon HDMISPARE (DATA_D2L)SPARE (DATA_D2L)LVTTL LVTTL on Lemoon Lemo

DELAY

clock

DEBUG 4x 8way DIL

ECL ECL on 2pin Lemoon 2pin Lemo


CCC - Logic and InterfacesCCC - Logic and Interfaces

Signal Inputs:Signal Inputs:• CLOCKCLOCK

– 1x LVDS ( SMA DC1x LVDS ( SMA DC ))– 1x LVTTL DC ( Lemo )1x LVTTL DC ( Lemo )– 1x NIM / TTL ( Lemo ) 1x NIM / TTL ( Lemo )

AC/DCAC/DC• ASYNCASYNC

– LVDS ( SMA ) LVDS ( SMA ) DCDC– ECL ( 2 pin LEMO ) ECL ( 2 pin LEMO )

ACAC• Controls Controls

( SYNCCMD, BUSY ( SYNCCMD, BUSY etc. + more )etc. + more )

– 4x LVDS ( SMA )4x LVDS ( SMA )– 4x NIM / TTL ( Lemo ) 4x NIM / TTL ( Lemo )

AC/DCAC/DC

• CPLD ( XCR3128XL-7 )CPLD ( XCR3128XL-7 )• RS232 interface as a means of controlRS232 interface as a means of control• Many buffers, 0Many buffers, 0ΩΩ resistors resistors and solder links for better signal integrity, isolation and and solder links for better signal integrity, isolation and configurationconfiguration

Signal Outputs:Signal Outputs:• CLOCKCLOCK

– 2x LVTTL on Lemo2x LVTTL on Lemo– 2x NIM on Lemo2x NIM on Lemo– 2x LVDS on SMA2x LVDS on SMA– 8x LVDS on DIL 8x LVDS on DIL

HeaderHeader• TRAINSYNCTRAINSYNC

– LVTTL on LemoLVTTL on Lemo• GEN GEN ( was Busy )( was Busy )

– LVDS on SMALVDS on SMA– NIM on LemoNIM on Lemo– O/C-TTL on LemoO/C-TTL on Lemo

• Spare ( DATA_D2L )Spare ( DATA_D2L )– LVTTL on LemoLVTTL on Lemo

HDMI I/O: x8HDMI I/O: x8- LVDS AC/DC- LVDS AC/DCOUT:OUT: • CLOCKCLOCK• ASYNCASYNC• TRAINSYNCTRAINSYNCIN:IN:• GEN ( was BUSY )GEN ( was BUSY )• SPARE( DATA_D2LSPARE( DATA_D2L ) )


Some Hardware DetailsSome Hardware Details

• Clock:Clock:– PLL/MUX - PLL/MUX - ICS581-02ICS581-02

• +/-150 ps jitter+/-150 ps jitter• 45min/55max Duty Cycle45min/55max Duty Cycle• Failover if external clock missing for 3 cycles.Failover if external clock missing for 3 cycles.

– Local Osc. 100 MHz/2 = 50% duty-cycle 50MHzLocal Osc. 100 MHz/2 = 50% duty-cycle 50MHz• CPLD: CPLD: Xilinx CoolRunner XPLA3 XCR3128XL-7Xilinx CoolRunner XPLA3 XCR3128XL-7

– 3.3V, low power3.3V, low power– 128 macrocells with 3,000 usable gates128 macrocells with 3,000 usable gates– 5.5ns pin-to-pin logic delays5.5ns pin-to-pin logic delays

• Extra IO via IDC header. Extra IO via IDC header. • Single 6U PCB with connectors at both edgesSingle 6U PCB with connectors at both edges• Separate PSUSeparate PSU• Clock Delay Option to CPLD – 64 x 0.5nsClock Delay Option to CPLD – 64 x 0.5ns

– For For signalsignal de-skew ( CLOCK unaffected ) de-skew ( CLOCK unaffected )


LVTTL Output Stand-alone ClockLVTTL Output Stand-alone Clock


LVTTL – Output Clock JitterLVTTL – Output Clock Jitter


0

CCC - Current StatusCCC - Current Status

• 10x boards manufactured and assembled in 200810x boards manufactured and assembled in 2008• 10x separate Power Supply units being assembled in 200910x separate Power Supply units being assembled in 2009• 10x CCC undergoing testing in 2009 :10x CCC undergoing testing in 2009 : - 9x program OK- 9x program OK - number of irritating problems ( dry joints, missing connections, etc. )- number of irritating problems ( dry joints, missing connections, etc. ) - 1x fails firmware programming ( suspect CPLD connections )- 1x fails firmware programming ( suspect CPLD connections )• Aim to have 9x tested and working units in AprilAim to have 9x tested and working units in April• Basic ‘simple’ self-testing firmware now on CPLDBasic ‘simple’ self-testing firmware now on CPLD• ‘ ‘Run’ firmware is in development : Run’ firmware is in development : COMING SOON !COMING SOON !• Serial Interface details on TwikiSerial Interface details on Twiki

• Hardware Manual draft :Hardware Manual draft :http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_CCC-MANUAL-3.txthttp://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_CCC-MANUAL-3.txt

• TWIKI pages :TWIKI pages :https://twiki.cern.ch/twiki/bin/view/CALICE/ClockControlCardhttps://twiki.cern.ch/twiki/bin/view/CALICE/ClockControlCardhttps://twiki.cern.ch/twiki/bin/view/CALICE/CCCSerialInterfacehttps://twiki.cern.ch/twiki/bin/view/CALICE/CCCSerialInterface


1

Spare slides….Spare slides….

FEW PREVIOUSLY SHOWN / SPARE SLIDESFEW PREVIOUSLY SHOWN / SPARE SLIDES


2

DAQ PC

CALICE - DAQ architectureCALICE - DAQ architecture

Detector Unit: Detector Unit: ASICsASICs

DIF DIF :: DDetector etector IInternterFFace connects ace connects Generic DAQ and servicesGeneric DAQ and services

LDA LDA :: LLink / ink / DData ata AAggregator – fan-out / in ggregator – fan-out / in DIFs and drives link to ODRDIFs and drives link to ODR

LDA

LDA

ODR

CCC

DetectorUnit

DIF

ODR ODR :: OOff ff DDetector etector RReceiver – PC eceiver – PC interface for system.interface for system.CCC CCC :: CClock & lock & CControl ontrol CCard: Fanout ard: Fanout to ODRs ( or LDAs )to ODRs ( or LDAs )CONTROL PCCONTROL PC:: DOOCS GUI ( run DOOCS GUI ( run control )control )

StorageControl

PC (DOOCS)

DAQ PC

ODR

DetectorUnit

DIF

DetectorUnit

DIF

DetectorUnit

DIF


3

CCC - Timing OverviewCCC - Timing Overview

• C+C provides a fast clock ( C+C provides a fast clock ( CLOCK CLOCK ))– Assumed to be ~50 MHz, local or machineAssumed to be ~50 MHz, local or machine– Stand-alone clock can be 50 or 100 MHzStand-alone clock can be 50 or 100 MHz

• CCC does NOT support varied delays on individual CCC does NOT support varied delays on individual outputsoutputs

• CCC card can adjust timing of synchro-signals wrt. CCC card can adjust timing of synchro-signals wrt. CLOCKCLOCK


4

CCC - Link InterfaceCCC - Link Interface

• CCC can connects to LDA, DIF and ODR using the ‘standard’ CCC can connects to LDA, DIF and ODR using the ‘standard’ HDMI cabling and connectors and pinout ( HDMI cabling and connectors and pinout ( Clink Clink ))

– But only a subset of the signals/functions usedBut only a subset of the signals/functions used– CCC can be used as a pseudo-LDA for stand-alone DIF testingCCC can be used as a pseudo-LDA for stand-alone DIF testing

• A distinction is made between fast and fixed latency signals. A distinction is made between fast and fixed latency signals. – Fast signaling is asynchronous and uses a dedicated line to transfer a Fast signaling is asynchronous and uses a dedicated line to transfer a

pulse. No attempt is made to encode datapulse. No attempt is made to encode data– Fixed-latency signaling will not arrive fast, but will arrive a known Fixed-latency signaling will not arrive fast, but will arrive a known latency after reception by CCClatency after reception by CCC

HDMI SignalsCLink Signal Direction Function Type

CLOCK_L2D LDA→DIF Distributed DIF Clock STP

DATA_L2D LDA→DIF Data to DIF (mainly configuration) STP

DATA_D2L DIF→LDA Data from DIF (mainly events) STP

ASYNC_L2D LDA→DIF Asynchronous trigger UTP*

GEN_D2L DIF→LDA General use STP

* Twisted pair not guaranteed by HDMI specification but seen in commercial cables


5

CCC - Link SignalsCCC - Link Signals

• CLOCKCLOCK– Machine clock (50 -100 MHz)Machine clock (50 -100 MHz)

• TRAINSYNC_OUT TRAINSYNC_OUT – SynchronisationSynchronisation of all the front-end slow clocks of all the front-end slow clocks– An external signal will be synchronized to the clock and An external signal will be synchronized to the clock and transmittedtransmitted as a as a

single clock-period wide pulse to the LDAsingle clock-period wide pulse to the LDA– To allow communicating with a stand-alone DIF, the CCC board will can To allow communicating with a stand-alone DIF, the CCC board will can

be configured to send the LDA 8b/10b serialised command for train-syncbe configured to send the LDA 8b/10b serialised command for train-sync

• ASYNC_OUT ASYNC_OUT – Transfer asynchronous triggers as fast as possibleTransfer asynchronous triggers as fast as possible

• GEN_INGEN_IN– General purpose signal for use in communicating with the CCC ( and General purpose signal for use in communicating with the CCC ( and

therefore run control ) system. A hardware OR of these signals is therefore run control ) system. A hardware OR of these signals is available on the CCCavailable on the CCC

CCC HDMI SignalsCLink Signal CCC Signal Function

CLOCK_L2D CLOCK_OUT Clock

DATA_L2D TRAINSYNC_OUT Trainsync signal output

DATA_D2L Unused Unused

ASYNC_L2D ASYNC_OUT Asynchronous signal

GEN_D2L GEN_IN General purpose

Documents

Clock & Control Card Status 31 March 2009 Martin Postranecky / Matt Warren